drm/i915: Fix sandybridge status page setup.
Eric Anholt [Mon, 2 Nov 2009 20:08:22 +0000 (12:08 -0800)]
The register's moved to the same location as the one for the BCS, it seems.

Signed-off-by: Eric Anholt <eric@anholt.net>

drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_reg.h

index 742bd8f..b57efca 100644 (file)
@@ -136,6 +136,12 @@ const static struct intel_device_info intel_ironlake_m_info = {
        .has_hotplug = 1,
 };
 
+const static struct intel_device_info intel_sandybridge_d_info = {
+       .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
+       .has_pipe_cxsr = 1,
+       .has_hotplug = 1,
+};
+
 const static struct pci_device_id pciidlist[] = {
        INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
        INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
@@ -167,6 +173,7 @@ const static struct pci_device_id pciidlist[] = {
        INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
        INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
        INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
+       INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
        {0, 0, 0}
 };
 
index 715eaac..c73da40 100644 (file)
@@ -4581,8 +4581,13 @@ i915_gem_init_hws(struct drm_device *dev)
        }
        dev_priv->hws_obj = obj;
        memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
-       I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
-       I915_READ(HWS_PGA); /* posting read */
+       if (IS_GEN6(dev)) {
+               I915_WRITE(HWS_PGA_GEN6, dev_priv->status_gfx_addr);
+               I915_READ(HWS_PGA_GEN6); /* posting read */
+       } else {
+               I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
+               I915_READ(HWS_PGA); /* posting read */
+       }
        DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
 
        return 0;
index 1232229..2a312b6 100644 (file)
 #define INSTDONE1      0x0207c /* 965+ only */
 #define ACTHD_I965     0x02074
 #define HWS_PGA                0x02080
+#define HWS_PGA_GEN6   0x04080
 #define HWS_ADDRESS_MASK       0xfffff000
 #define HWS_START_ADDRESS_SHIFT        4
 #define PWRCTXA                0x2088 /* 965GM+ only */