drm/radeon/kms: display watermark fixes
Alex Deucher [Wed, 17 Mar 2010 00:54:38 +0000 (20:54 -0400)]
- rs780/880 were using the wrong bandwidth functions
- convert r1xx-r4xx to use the same pm sclk/mclk structs as
r5xx+
- move bandwidth setup to a common function

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

12 files changed:
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/r300.c
drivers/gpu/drm/radeon/r520.c
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/radeon_device.c
drivers/gpu/drm/radeon/rs600.c
drivers/gpu/drm/radeon/rs690.c
drivers/gpu/drm/radeon/rv515.c
drivers/gpu/drm/radeon/rv770.c

index db78d93..647a0ef 100644 (file)
@@ -437,7 +437,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
 
 int evergreen_mc_init(struct radeon_device *rdev)
 {
-       fixed20_12 a;
        u32 tmp;
        int chansize, numchan;
 
@@ -482,12 +481,8 @@ int evergreen_mc_init(struct radeon_device *rdev)
                rdev->mc.real_vram_size = rdev->mc.aper_size;
        }
        r600_vram_gtt_location(rdev, &rdev->mc);
-       /* FIXME: we should enforce default clock in case GPU is not in
-        * default setup
-        */
-       a.full = rfixed_const(100);
-       rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
-       rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+       radeon_update_bandwidth_info(rdev);
+
        return 0;
 }
 
index 9d634c8..e35cf19 100644 (file)
@@ -2025,6 +2025,7 @@ void r100_mc_init(struct radeon_device *rdev)
        radeon_vram_location(rdev, &rdev->mc, base);
        if (!(rdev->flags & RADEON_IS_AGP))
                radeon_gtt_location(rdev, &rdev->mc);
+       radeon_update_bandwidth_info(rdev);
 }
 
 
@@ -2416,11 +2417,8 @@ void r100_bandwidth_update(struct radeon_device *rdev)
        /*
         * determine is there is enough bw for current mode
         */
-       mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
-       temp_ff.full = rfixed_const(100);
-       mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
-       sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
-       sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
+       sclk_ff = rdev->pm.sclk;
+       mclk_ff = rdev->pm.mclk;
 
        temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
        temp_ff.full = rfixed_const(temp);
index 6d75f81..63fe275 100644 (file)
@@ -482,6 +482,7 @@ void r300_mc_init(struct radeon_device *rdev)
        radeon_vram_location(rdev, &rdev->mc, base);
        if (!(rdev->flags & RADEON_IS_AGP))
                radeon_gtt_location(rdev, &rdev->mc);
+       radeon_update_bandwidth_info(rdev);
 }
 
 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
index f6d8541..3c44b8d 100644 (file)
@@ -122,19 +122,13 @@ static void r520_vram_get_type(struct radeon_device *rdev)
 
 void r520_mc_init(struct radeon_device *rdev)
 {
-       fixed20_12 a;
 
        r520_vram_get_type(rdev);
        r100_vram_init_sizes(rdev);
        radeon_vram_location(rdev, &rdev->mc, 0);
        if (!(rdev->flags & RADEON_IS_AGP))
                radeon_gtt_location(rdev, &rdev->mc);
-       /* FIXME: we should enforce default clock in case GPU is not in
-        * default setup
-        */
-       a.full = rfixed_const(100);
-       rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
-       rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+       radeon_update_bandwidth_info(rdev);
 }
 
 void r520_mc_program(struct radeon_device *rdev)
index d568262..1aac8bf 100644 (file)
@@ -676,7 +676,6 @@ void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 
 int r600_mc_init(struct radeon_device *rdev)
 {
-       fixed20_12 a;
        u32 tmp;
        int chansize, numchan;
 
@@ -720,14 +719,10 @@ int r600_mc_init(struct radeon_device *rdev)
                rdev->mc.real_vram_size = rdev->mc.aper_size;
        }
        r600_vram_gtt_location(rdev, &rdev->mc);
-       /* FIXME: we should enforce default clock in case GPU is not in
-        * default setup
-        */
-       a.full = rfixed_const(100);
-       rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
-       rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+
        if (rdev->flags & RADEON_IS_IGP)
                rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+       radeon_update_bandwidth_info(rdev);
        return 0;
 }
 
index 46bfff9..4ee5cb9 100644 (file)
@@ -699,6 +699,7 @@ struct radeon_pm {
        fixed20_12              ht_bandwidth;
        fixed20_12              core_bandwidth;
        fixed20_12              sclk;
+       fixed20_12              mclk;
        fixed20_12              needed_bandwidth;
        /* XXX: use a define for num power modes */
        struct radeon_power_state power_state[8];
@@ -1179,6 +1180,7 @@ extern void radeon_gart_restore(struct radeon_device *rdev);
 extern int radeon_modeset_init(struct radeon_device *rdev);
 extern void radeon_modeset_fini(struct radeon_device *rdev);
 extern bool radeon_card_posted(struct radeon_device *rdev);
+extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
 extern int radeon_clocks_init(struct radeon_device *rdev);
 extern void radeon_clocks_fini(struct radeon_device *rdev);
index dd23dcf..a4b4bc9 100644 (file)
@@ -543,6 +543,43 @@ static struct radeon_asic r600_asic = {
        .ioctl_wait_idle = r600_ioctl_wait_idle,
 };
 
+static struct radeon_asic rs780_asic = {
+       .init = &r600_init,
+       .fini = &r600_fini,
+       .suspend = &r600_suspend,
+       .resume = &r600_resume,
+       .cp_commit = &r600_cp_commit,
+       .vga_set_state = &r600_vga_set_state,
+       .gpu_reset = &r600_gpu_reset,
+       .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
+       .gart_set_page = &rs600_gart_set_page,
+       .ring_test = &r600_ring_test,
+       .ring_ib_execute = &r600_ring_ib_execute,
+       .irq_set = &r600_irq_set,
+       .irq_process = &r600_irq_process,
+       .get_vblank_counter = &rs600_get_vblank_counter,
+       .fence_ring_emit = &r600_fence_ring_emit,
+       .cs_parse = &r600_cs_parse,
+       .copy_blit = &r600_copy_blit,
+       .copy_dma = &r600_copy_blit,
+       .copy = &r600_copy_blit,
+       .get_engine_clock = &radeon_atom_get_engine_clock,
+       .set_engine_clock = &radeon_atom_set_engine_clock,
+       .get_memory_clock = NULL,
+       .set_memory_clock = NULL,
+       .get_pcie_lanes = NULL,
+       .set_pcie_lanes = NULL,
+       .set_clock_gating = NULL,
+       .set_surface_reg = r600_set_surface_reg,
+       .clear_surface_reg = r600_clear_surface_reg,
+       .bandwidth_update = &rs690_bandwidth_update,
+       .hpd_init = &r600_hpd_init,
+       .hpd_fini = &r600_hpd_fini,
+       .hpd_sense = &r600_hpd_sense,
+       .hpd_set_polarity = &r600_hpd_set_polarity,
+       .ioctl_wait_idle = r600_ioctl_wait_idle,
+};
+
 static struct radeon_asic rv770_asic = {
        .init = &rv770_init,
        .fini = &rv770_fini,
@@ -673,9 +710,11 @@ int radeon_asic_init(struct radeon_device *rdev)
        case CHIP_RV620:
        case CHIP_RV635:
        case CHIP_RV670:
+               rdev->asic = &r600_asic;
+               break;
        case CHIP_RS780:
        case CHIP_RS880:
-               rdev->asic = &r600_asic;
+               rdev->asic = &rs780_asic;
                break;
        case CHIP_RV770:
        case CHIP_RV730:
index 581b75a..6bedc21 100644 (file)
@@ -241,6 +241,36 @@ bool radeon_card_posted(struct radeon_device *rdev)
 
 }
 
+void radeon_update_bandwidth_info(struct radeon_device *rdev)
+{
+       fixed20_12 a;
+       u32 sclk, mclk;
+
+       if (rdev->flags & RADEON_IS_IGP) {
+               sclk = radeon_get_engine_clock(rdev);
+               mclk = rdev->clock.default_mclk;
+
+               a.full = rfixed_const(100);
+               rdev->pm.sclk.full = rfixed_const(sclk);
+               rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+               rdev->pm.mclk.full = rfixed_const(mclk);
+               rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a);
+
+               a.full = rfixed_const(16);
+               /* core_bandwidth = sclk(Mhz) * 16 */
+               rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
+       } else {
+               sclk = radeon_get_engine_clock(rdev);
+               mclk = radeon_get_memory_clock(rdev);
+
+               a.full = rfixed_const(100);
+               rdev->pm.sclk.full = rfixed_const(sclk);
+               rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+               rdev->pm.mclk.full = rfixed_const(mclk);
+               rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a);
+       }
+}
+
 bool radeon_boot_test_post_card(struct radeon_device *rdev)
 {
        if (radeon_card_posted(rdev))
index 3630c16..df7a855 100644 (file)
@@ -475,8 +475,10 @@ void rs600_mc_init(struct radeon_device *rdev)
        rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
        base = RREG32_MC(R_000004_MC_FB_LOCATION);
        base = G_000004_MC_FB_START(base) << 16;
+       rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
        radeon_vram_location(rdev, &rdev->mc, base);
        radeon_gtt_location(rdev, &rdev->mc);
+       radeon_update_bandwidth_info(rdev);
 }
 
 void rs600_bandwidth_update(struct radeon_device *rdev)
index 6c92ae3..e356935 100644 (file)
@@ -132,7 +132,6 @@ void rs690_pm_info(struct radeon_device *rdev)
 
 void rs690_mc_init(struct radeon_device *rdev)
 {
-       fixed20_12 a;
        u64 base;
 
        rs400_gart_adjust_size(rdev);
@@ -146,18 +145,10 @@ void rs690_mc_init(struct radeon_device *rdev)
        base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
        base = G_000100_MC_FB_START(base) << 16;
        rs690_pm_info(rdev);
-       /* FIXME: we should enforce default clock in case GPU is not in
-        * default setup
-        */
-       a.full = rfixed_const(100);
-       rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
-       rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
-       a.full = rfixed_const(16);
-       /* core_bandwidth = sclk(Mhz) * 16 */
-       rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
        rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
        radeon_vram_location(rdev, &rdev->mc, base);
        radeon_gtt_location(rdev, &rdev->mc);
+       radeon_update_bandwidth_info(rdev);
 }
 
 void rs690_line_buffer_adjust(struct radeon_device *rdev,
index f85499f..d94291a 100644 (file)
@@ -280,19 +280,13 @@ static void rv515_vram_get_type(struct radeon_device *rdev)
 
 void rv515_mc_init(struct radeon_device *rdev)
 {
-       fixed20_12 a;
 
        rv515_vram_get_type(rdev);
        r100_vram_init_sizes(rdev);
        radeon_vram_location(rdev, &rdev->mc, 0);
        if (!(rdev->flags & RADEON_IS_AGP))
                radeon_gtt_location(rdev, &rdev->mc);
-       /* FIXME: we should enforce default clock in case GPU is not in
-        * default setup
-        */
-       a.full = rfixed_const(100);
-       rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
-       rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+       radeon_update_bandwidth_info(rdev);
 }
 
 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
index 86d39cb..ef946a3 100644 (file)
@@ -868,7 +868,6 @@ static void rv770_gpu_init(struct radeon_device *rdev)
 
 int rv770_mc_init(struct radeon_device *rdev)
 {
-       fixed20_12 a;
        u32 tmp;
        int chansize, numchan;
 
@@ -912,12 +911,8 @@ int rv770_mc_init(struct radeon_device *rdev)
                rdev->mc.real_vram_size = rdev->mc.aper_size;
        }
        r600_vram_gtt_location(rdev, &rdev->mc);
-       /* FIXME: we should enforce default clock in case GPU is not in
-        * default setup
-        */
-       a.full = rfixed_const(100);
-       rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
-       rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+       radeon_update_bandwidth_info(rdev);
+
        return 0;
 }