ARM: tegra: xusb: read usb_calib once in common file
Ajay Gupta [Tue, 14 May 2013 20:16:36 +0000 (13:16 -0700)]
Moved usb_calib read part in arch/arm/mach-tegra/xusb.c from
Dalmore and Pluto board files.

Bug 1268244

Change-Id: I1188499da7138c5b02c8d26d298646ad179226e1
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/228501
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

arch/arm/mach-tegra/board-dalmore.c
arch/arm/mach-tegra/board-pluto.c
arch/arm/mach-tegra/include/mach/xusb.h
arch/arm/mach-tegra/xusb.c
drivers/usb/host/xhci-tegra.c
include/linux/platform_data/tegra_xusb.h

index fb34b45..4c682a3 100644 (file)
@@ -583,27 +583,8 @@ static void dalmore_xusb_init(void)
 {
        int usb_port_owner_info = tegra_get_usb_port_owner_info();
 
-       if (usb_port_owner_info & UTMI2_PORT_OWNER_XUSB) {
-               u32 usb_calib0 = tegra_fuse_readl(FUSE_SKU_USB_CALIB_0);
-
-               pr_info("dalmore_xusb_init: usb_calib0 = 0x%08x\n", usb_calib0);
-               /*
-                * read from usb_calib0 and pass to driver
-                * set HS_CURR_LEVEL (PAD0)     = usb_calib0[5:0]
-                * set TERM_RANGE_ADJ           = usb_calib0[10:7]
-                * set HS_SQUELCH_LEVEL         = usb_calib0[12:11]
-                * set HS_IREF_CAP              = usb_calib0[14:13]
-                * set HS_CURR_LEVEL (PAD1)     = usb_calib0[20:15]
-                */
-
-               xusb_padctl_data.hs_curr_level_pad0 = (usb_calib0 >> 0) & 0x3f;
-               xusb_padctl_data.hs_term_range_adj = (usb_calib0 >> 7) & 0xf;
-               xusb_padctl_data.hs_squelch_level = (usb_calib0 >> 11) & 0x3;
-               xusb_padctl_data.hs_iref_cap = (usb_calib0 >> 13) & 0x3;
-               xusb_padctl_data.hs_curr_level_pad1 = (usb_calib0 >> 15) & 0x3f;
-
+       if (usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)
                tegra_xusb_init(&xusb_bdata);
-       }
 }
 
 static struct gpio modem_gpios[] = { /* Nemo modem */
index 2b12e9a..6e8bf21 100644 (file)
@@ -1166,27 +1166,8 @@ static void pluto_xusb_init(void)
 {
        int usb_port_owner_info = tegra_get_usb_port_owner_info();
 
-       if (usb_port_owner_info & UTMI1_PORT_OWNER_XUSB) {
-               u32 usb_calib0 = tegra_fuse_readl(FUSE_SKU_USB_CALIB_0);
-
-               pr_info("dalmore_xusb_init: usb_calib0 = 0x%08x\n", usb_calib0);
-               /*
-                * read from usb_calib0 and pass to driver
-                * set HS_CURR_LEVEL (PAD0)     = usb_calib0[5:0]
-                * set TERM_RANGE_ADJ           = usb_calib0[10:7]
-                * set HS_SQUELCH_LEVEL         = usb_calib0[12:11]
-                * set HS_IREF_CAP              = usb_calib0[14:13]
-                * set HS_CURR_LEVEL (PAD1)     = usb_calib0[20:15]
-                */
-
-               xusb_padctl_data.hs_curr_level_pad0 = (usb_calib0 >> 0) & 0x3f;
-               xusb_padctl_data.hs_term_range_adj = (usb_calib0 >> 7) & 0xf;
-               xusb_padctl_data.hs_squelch_level = (usb_calib0 >> 11) & 0x3;
-               xusb_padctl_data.hs_iref_cap = (usb_calib0 >> 13) & 0x3;
-               xusb_padctl_data.hs_curr_level_pad1 = (usb_calib0 >> 15) & 0x3f;
-
+       if (usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)
                tegra_xusb_init(&xusb_bdata);
-       }
 }
 #else
 static void pluto_usb_init(void) { }
index f9abc80..a14cd2a 100644 (file)
@@ -51,6 +51,11 @@ struct tegra_xusb_board_data {
 
 struct tegra_xusb_platform_data {
        struct tegra_xusb_board_data *bdata;
+       u32 hs_curr_level_pad0;
+       u32 hs_curr_level_pad1;
+       u32 hs_iref_cap;
+       u32 hs_term_range_adj;
+       u32 hs_squelch_level;
 };
 
 extern void tegra_xusb_init(struct tegra_xusb_board_data *bdata);
index 20c5d72..3a96f43 100644 (file)
 #include <linux/types.h>
 #include <mach/xusb.h>
 #include "devices.h"
+#include "fuse.h"
 
 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
 static struct tegra_xusb_platform_data tegra_xusb_plat_data = {};
+
+static void tegra_xusb_read_usb_calib(void)
+{
+       u32 usb_calib0 = tegra_fuse_readl(FUSE_SKU_USB_CALIB_0);
+
+       pr_info("tegra_xusb_read_usb_calib: usb_calib0 = 0x%08x\n", usb_calib0);
+       /*
+        * read from usb_calib0 and pass to driver
+        * set HS_CURR_LEVEL (PAD0)     = usb_calib0[5:0]
+        * set TERM_RANGE_ADJ           = usb_calib0[10:7]
+        * set HS_SQUELCH_LEVEL         = usb_calib0[12:11]
+        * set HS_IREF_CAP              = usb_calib0[14:13]
+        * set HS_CURR_LEVEL (PAD1)     = usb_calib0[20:15]
+        */
+
+       tegra_xusb_plat_data.hs_curr_level_pad0 = (usb_calib0 >> 0) & 0x3f;
+       tegra_xusb_plat_data.hs_term_range_adj = (usb_calib0 >> 7) & 0xf;
+       tegra_xusb_plat_data.hs_squelch_level = (usb_calib0 >> 11) & 0x3;
+       tegra_xusb_plat_data.hs_iref_cap = (usb_calib0 >> 13) & 0x3;
+       tegra_xusb_plat_data.hs_curr_level_pad1 = (usb_calib0 >> 15) & 0x3f;
+}
+
 void tegra_xusb_init(struct tegra_xusb_board_data *bdata)
 {
+       tegra_xusb_read_usb_calib();
        tegra_xusb_plat_data.bdata = bdata;
        tegra_xhci_device.dev.platform_data = &tegra_xusb_plat_data;
        platform_device_register(&tegra_xhci_device);
index 805c9a2..a3108d8 100644 (file)
@@ -1105,32 +1105,32 @@ tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra)
        reg = readl(tegra->padctl_base + USB2_OTG_PAD0_CTL_0_0);
        reg &= ~((0x3fff << 0) | (0x1f << 19));
        reg |= xusb_padctl->hs_slew | xusb_padctl->ls_rslew
-               | xusb_padctl->hs_curr_level_pad0 | xusb_padctl->otg_pad0_ctl0;
+               | tegra->pdata->hs_curr_level_pad0 | xusb_padctl->otg_pad0_ctl0;
        writel(reg, tegra->padctl_base + USB2_OTG_PAD0_CTL_0_0);
 
        reg = readl(tegra->padctl_base + USB2_OTG_PAD1_CTL_0_0);
        reg &= ~((0xfff << 0) | (0x1f << 19));
        reg |= xusb_padctl->hs_slew
-               | xusb_padctl->hs_curr_level_pad1 | xusb_padctl->otg_pad1_ctl0;
+               | tegra->pdata->hs_curr_level_pad1 | xusb_padctl->otg_pad1_ctl0;
        writel(reg, tegra->padctl_base + USB2_OTG_PAD1_CTL_0_0);
 
        reg = readl(tegra->padctl_base + USB2_OTG_PAD0_CTL_1_0);
        reg &= ~((0x7 << 0) | (0x3 << 9) | (0xf << 3));
        reg |= (xusb_padctl->otg_pad0_ctl1 << 0)
-               | (xusb_padctl->hs_iref_cap << 9)
-               | (xusb_padctl->hs_term_range_adj << 3);
+               | (tegra->pdata->hs_iref_cap << 9)
+               | (tegra->pdata->hs_term_range_adj << 3);
        writel(reg, tegra->padctl_base + USB2_OTG_PAD0_CTL_1_0);
 
        reg = readl(tegra->padctl_base + USB2_OTG_PAD1_CTL_1_0);
        reg &= ~((0x7 << 0) | (0xf << 3) | (0x3 << 9));
        reg |= (xusb_padctl->otg_pad1_ctl1 << 0)
-               | (xusb_padctl->hs_term_range_adj << 3)
-               | (xusb_padctl->hs_iref_cap << 9);
+               | (tegra->pdata->hs_term_range_adj << 3)
+               | (tegra->pdata->hs_iref_cap << 9);
        writel(reg, tegra->padctl_base + USB2_OTG_PAD1_CTL_1_0);
 
        reg = readl(tegra->padctl_base + USB2_BIAS_PAD_CTL_0_0);
        reg &= ~(0x1f << 0);
-       reg |= xusb_padctl->hs_squelch_level | xusb_padctl->hs_disc_lvl;
+       reg |= tegra->pdata->hs_squelch_level | xusb_padctl->hs_disc_lvl;
        writel(reg, tegra->padctl_base + USB2_BIAS_PAD_CTL_0_0);
 
        reg = readl(tegra->padctl_base + HSIC_PAD0_CTL_0_0);
index ebae033..2478f2a 100644 (file)
@@ -32,11 +32,6 @@ struct tegra_xusb_pad_data {
        u32 dfe_cntl;
        u32 hs_slew;
        u32 ls_rslew;
-       u32 hs_curr_level_pad0;
-       u32 hs_curr_level_pad1;
-       u32 hs_iref_cap;
-       u32 hs_term_range_adj;
-       u32 hs_squelch_level;
        u32 otg_pad0_ctl0;
        u32 otg_pad1_ctl0;
        u32 otg_pad0_ctl1;