video: tegra: dc: use trace events
Jon Mayo [Tue, 25 Sep 2012 23:55:24 +0000 (16:55 -0700)]
Use trace events instead of trace_printk.
Removed some unnecessary traces.

Bug 990469

Change-Id: I060369b12c852b5584634641b8971e23f60fc399
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/138797
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

drivers/video/tegra/dc/bandwidth.c
drivers/video/tegra/dc/dc.c
drivers/video/tegra/dc/dc_priv.h
drivers/video/tegra/dc/dc_priv_defs.h [new file with mode: 0644]
drivers/video/tegra/dc/dsi.c
drivers/video/tegra/dc/ext/dev.c
drivers/video/tegra/dc/hdmi.c
drivers/video/tegra/dc/mode.c
drivers/video/tegra/dc/window.c
include/trace/events/display.h [new file with mode: 0644]

index 0b307f4..0a631b9 100644 (file)
@@ -24,6 +24,7 @@
 #include <mach/mc.h>
 #include <linux/nvhost.h>
 #include <mach/latency_allowance.h>
+#include <trace/events/display.h>
 
 #include "dc_reg.h"
 #include "dc_config.h"
@@ -214,8 +215,7 @@ static unsigned long tegra_dc_get_bandwidth(
 /* to save power, call when display memory clients would be idle */
 void tegra_dc_clear_bandwidth(struct tegra_dc *dc)
 {
-       trace_printk("%s:%s rate=%d\n", dc->ndev->name, __func__,
-               dc->emc_clk_rate);
+       trace_clear_bandwidth(dc);
        if (tegra_is_clk_enabled(dc->emc_clk))
                clk_disable(dc->emc_clk);
        dc->emc_clk_rate = 0;
@@ -251,9 +251,8 @@ void tegra_dc_program_bandwidth(struct tegra_dc *dc, bool use_new)
                if ((use_new || w->bandwidth != w->new_bandwidth) &&
                        w->new_bandwidth != 0)
                        tegra_dc_set_latency_allowance(dc, w);
+               trace_program_bandwidth(dc);
                w->bandwidth = w->new_bandwidth;
-               trace_printk("%s:win%u bandwidth=%d\n", dc->ndev->name, w->idx,
-                       w->bandwidth);
        }
 }
 
@@ -277,8 +276,8 @@ int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
        if (tegra_dc_has_multiple_dc())
                new_rate = ULONG_MAX;
 
-       trace_printk("%s:new_emc_clk_rate=%ld\n", dc->ndev->name, new_rate);
        dc->new_emc_clk_rate = new_rate;
+       trace_set_dynamic_emc(dc);
 
        return 0;
 }
index 9d15778..7e26b30 100644 (file)
@@ -41,6 +41,9 @@
 #include <linux/switch.h>
 #endif
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/display.h>
+
 #include <mach/clk.h>
 #include <mach/dc.h>
 #include <mach/fb.h>
@@ -293,22 +296,11 @@ void tegra_dc_release_dc_out(struct tegra_dc *dc)
 }
 
 #define DUMP_REG(a) do {                       \
-       snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
+       snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
                 #a, a, tegra_dc_readl(dc, a));               \
        print(data, buff);                                    \
        } while (0)
 
-#define print_underflow_info(dc) do {                 \
-       trace_printk("%s:Underflow stats: underflows : %llu, "      \
-                       "undeflows_a : %llu, "                          \
-                       "underflows_b : %llu, "                         \
-                       "underflows_c : %llu\n",                        \
-                       dc->ndev->name,                                 \
-                       dc->stats.underflows,                           \
-                       dc->stats.underflows_a, dc->stats.underflows_b, \
-                       dc->stats.underflows_c);                        \
-       } while (0)
-
 static void _dump_regs(struct tegra_dc *dc, void *data,
                       void (* print)(void *data, const char *str))
 {
@@ -1247,21 +1239,15 @@ static void tegra_dc_underflow_handler(struct tegra_dc *dc)
        int i;
 
        dc->stats.underflows++;
-       if (dc->underflow_mask & WIN_A_UF_INT) {
+       if (dc->underflow_mask & WIN_A_UF_INT)
                dc->stats.underflows_a += tegra_dc_underflow_count(dc,
                        DC_WINBUF_AD_UFLOW_STATUS);
-               trace_printk("%s:Window A Underflow\n", dc->ndev->name);
-       }
-       if (dc->underflow_mask & WIN_B_UF_INT) {
+       if (dc->underflow_mask & WIN_B_UF_INT)
                dc->stats.underflows_b += tegra_dc_underflow_count(dc,
                        DC_WINBUF_BD_UFLOW_STATUS);
-               trace_printk("%s:Window B Underflow\n", dc->ndev->name);
-       }
-       if (dc->underflow_mask & WIN_C_UF_INT) {
+       if (dc->underflow_mask & WIN_C_UF_INT)
                dc->stats.underflows_c += tegra_dc_underflow_count(dc,
                        DC_WINBUF_CD_UFLOW_STATUS);
-               trace_printk("%s:Window C Underflow\n", dc->ndev->name);
-       }
 
        /* Check for any underflow reset conditions */
        for (i = 0; i < DC_N_WINDOWS; i++) {
@@ -1273,16 +1259,12 @@ static void tegra_dc_underflow_handler(struct tegra_dc *dc)
                                schedule_work(&dc->reset_work);
                                /* reset counter */
                                dc->windows[i].underflows = 0;
-                               trace_printk("%s:Reset work scheduled for "
-                                               "window %c\n",
-                                               dc->ndev->name, (65 + i));
+                               trace_display_reset(dc);
                        }
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
                        if (dc->windows[i].underflows > 4) {
-                               trace_printk("%s:window %c in underflow state."
-                                       " enable UF_LINE_FLUSH to clear up\n",
-                                       dc->ndev->name, (65 + i));
+                               trace_display_reset(dc);
                                tegra_dc_writel(dc, UF_LINE_FLUSH,
                                                DC_DISP_DISP_MISC_CONTROL);
                                tegra_dc_writel(dc, GENERAL_UPDATE,
@@ -1308,7 +1290,7 @@ static void tegra_dc_underflow_handler(struct tegra_dc *dc)
        dc->underflow_mask = 0;
        val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
        tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
-       print_underflow_info(dc);
+       trace_underflow(dc);
 }
 
 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
@@ -1593,7 +1575,7 @@ static int tegra_dc_init(struct tegra_dc *dc)
                        nvhost_syncpt_read_ext(dc->ndev, syncpt);
        }
 
-       print_mode_info(dc, dc->mode);
+       trace_display_mode(dc, &dc->mode);
 
        if (dc->mode.pclk)
                if (tegra_dc_program_mode(dc, &dc->mode))
@@ -1640,7 +1622,7 @@ static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
 
        tegra_dc_ext_enable(dc->ext);
 
-       trace_printk("%s:enable\n", dc->ndev->name);
+       trace_display_enable(dc);
 
        tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
        tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
@@ -1709,7 +1691,7 @@ static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
                _tegra_dc_controller_disable(dc);
        }
 
-       trace_printk("%s:reset enable\n", dc->ndev->name);
+       trace_display_reset(dc);
        return ret;
 }
 #endif
@@ -1767,7 +1749,7 @@ void tegra_dc_enable(struct tegra_dc *dc)
                dc->enabled = _tegra_dc_enable(dc);
 
        mutex_unlock(&dc->lock);
-       print_mode_info(dc, dc->mode);
+       trace_display_mode(dc, &dc->mode);
 }
 
 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
@@ -1802,13 +1784,13 @@ static void _tegra_dc_controller_disable(struct tegra_dc *dc)
 
                /* flush any pending syncpt waits */
                while (dc->syncpt[i].min < dc->syncpt[i].max) {
-                       trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
-                               dc->syncpt[i].id);
+                       trace_display_syncpt_flush(dc, dc->syncpt[i].id,
+                               dc->syncpt[i].min, dc->syncpt[i].max);
                        dc->syncpt[i].min++;
                        nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
                }
        }
-       trace_printk("%s:disabled\n", dc->ndev->name);
+       trace_display_disable(dc);
 }
 
 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
@@ -1899,7 +1881,7 @@ void tegra_dc_disable(struct tegra_dc *dc)
 #endif
 
        mutex_unlock(&dc->lock);
-       print_mode_info(dc, dc->mode);
+       trace_display_mode(dc, &dc->mode);
 }
 
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
@@ -1954,7 +1936,7 @@ static void tegra_dc_reset_worker(struct work_struct *work)
 unlock:
        mutex_unlock(&dc->lock);
        mutex_unlock(&shared_lock);
-       trace_printk("%s:reset complete\n", dc->ndev->name);
+       trace_display_reset(dc);
 }
 #endif
 
@@ -2243,7 +2225,7 @@ static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
 {
        struct tegra_dc *dc = nvhost_get_drvdata(ndev);
 
-       trace_printk("%s:suspend\n", dc->ndev->name);
+       trace_display_suspend(dc);
        dev_info(&ndev->dev, "suspend\n");
 
        tegra_dc_ext_disable(dc->ext);
@@ -2277,7 +2259,7 @@ static int tegra_dc_resume(struct nvhost_device *ndev)
 {
        struct tegra_dc *dc = nvhost_get_drvdata(ndev);
 
-       trace_printk("%s:resume\n", dc->ndev->name);
+       trace_display_resume(dc);
        dev_info(&ndev->dev, "resume\n");
 
        mutex_lock(&dc->lock);
index 09df9dd..1d12c09 100644 (file)
 #ifndef __DRIVERS_VIDEO_TEGRA_DC_DC_PRIV_H
 #define __DRIVERS_VIDEO_TEGRA_DC_DC_PRIV_H
 
-#include <linux/io.h>
-#include <linux/mutex.h>
-#include <linux/wait.h>
-#include <linux/fb.h>
-#include <linux/clk.h>
-#include <linux/completion.h>
-#include <linux/switch.h>
-#include <linux/nvhost.h>
-
-#include <mach/dc.h>
-
-#include <mach/tegra_dc_ext.h>
-#include <mach/clk.h>
-
-#include "dc_reg.h"
-
-#define WIN_IS_TILED(win)      ((win)->flags & TEGRA_WIN_FLAG_TILED)
-#define WIN_IS_ENABLED(win)    ((win)->flags & TEGRA_WIN_FLAG_ENABLED)
-
-#define NEED_UPDATE_EMC_ON_EVERY_FRAME (windows_idle_detection_time == 0)
-
-/* DDR: 8 bytes transfer per clock */
-#define DDR_BW_TO_FREQ(bw) ((bw) / 8)
-
-/* 29 bit offset for window clip number */
-#define CURSOR_CLIP_SHIFT_BITS(win)    (win << 29)
-#define CURSOR_CLIP_GET_WINDOW(reg)    ((reg >> 29) & 3)
-
-#if defined(CONFIG_TEGRA_EMC_TO_DDR_CLOCK)
-#define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * CONFIG_TEGRA_EMC_TO_DDR_CLOCK)
-#else
-#define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * 2)
-#endif
-
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
-#define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
-#else
-/* ignore underflows when on simulation and fpga platform */
-#define ALL_UF_INT (0)
-#endif
-
-struct tegra_dc;
-
-struct tegra_dc_blend {
-       unsigned z[DC_N_WINDOWS];
-       unsigned flags[DC_N_WINDOWS];
-};
-
-struct tegra_dc_out_ops {
-       /* initialize output.  dc clocks are not on at this point */
-       int (*init)(struct tegra_dc *dc);
-       /* destroy output.  dc clocks are not on at this point */
-       void (*destroy)(struct tegra_dc *dc);
-       /* detect connected display.  can sleep.*/
-       bool (*detect)(struct tegra_dc *dc);
-       /* enable output.  dc clocks are on at this point */
-       void (*enable)(struct tegra_dc *dc);
-       /* disable output.  dc clocks are on at this point */
-       void (*disable)(struct tegra_dc *dc);
-       /* hold output.  keeps dc clocks on. */
-       void (*hold)(struct tegra_dc *dc);
-       /* release output.  dc clocks may turn off after this. */
-       void (*release)(struct tegra_dc *dc);
-       /* idle routine of output.  dc clocks may turn off after this. */
-       void (*idle)(struct tegra_dc *dc);
-       /* suspend output.  dc clocks are on at this point */
-       void (*suspend)(struct tegra_dc *dc);
-       /* resume output.  dc clocks are on at this point */
-       void (*resume)(struct tegra_dc *dc);
-       /* mode filter. to provide a list of supported modes*/
-       bool (*mode_filter)(const struct tegra_dc *dc,
-                       struct fb_videomode *mode);
-};
-
-struct tegra_dc {
-       struct nvhost_device            *ndev;
-       struct tegra_dc_platform_data   *pdata;
-
-       struct resource                 *base_res;
-       void __iomem                    *base;
-       int                             irq;
-
-       struct clk                      *clk;
-       struct clk                      *emc_clk;
-       int                             emc_clk_rate;
-       int                             new_emc_clk_rate;
-       u32                             shift_clk_div;
-
-       bool                            connected;
-       bool                            enabled;
-       bool                            suspended;
-
-       struct tegra_dc_out             *out;
-       struct tegra_dc_out_ops         *out_ops;
-       void                            *out_data;
-
-       struct tegra_dc_mode            mode;
-       s64                             frametime_ns;
-
-       struct tegra_dc_win             windows[DC_N_WINDOWS];
-       struct tegra_dc_blend           blend;
-       int                             n_windows;
-#ifdef CONFIG_TEGRA_DC_CMU
-       struct tegra_dc_cmu             cmu;
-#endif
-       wait_queue_head_t               wq;
-       wait_queue_head_t               timestamp_wq;
-
-       struct mutex                    lock;
-       struct mutex                    one_shot_lock;
-
-       struct resource                 *fb_mem;
-       struct tegra_fb_info            *fb;
-
-       struct {
-               u32                     id;
-               u32                     min;
-               u32                     max;
-       } syncpt[DC_N_WINDOWS];
-       u32                             vblank_syncpt;
-
-       unsigned long                   underflow_mask;
-       struct work_struct              reset_work;
-
-#ifdef CONFIG_SWITCH
-       struct switch_dev               modeset_switch;
-#endif
-
-       struct completion               frame_end_complete;
-
-       struct work_struct              vblank_work;
-       long                            vblank_ref_count;
-
-       struct {
-               u64                     underflows;
-               u64                     underflows_a;
-               u64                     underflows_b;
-               u64                     underflows_c;
-       } stats;
-
-       struct tegra_dc_ext             *ext;
-
-       struct tegra_dc_feature         *feature;
-       int                             gen1_blend_num;
-
-#ifdef CONFIG_DEBUG_FS
-       struct dentry                   *debugdir;
+#include "dc_priv_defs.h"
+#ifndef CREATE_TRACE_POINTS
+# include <trace/events/display.h>
 #endif
-       struct tegra_dc_lut             fb_lut;
-       struct delayed_work             underflow_work;
-       u32                             one_shot_delay_ms;
-       struct delayed_work             one_shot_work;
-       s64                             frame_end_timestamp;
-};
-
-#define print_mode_info(dc, mode) do {                                 \
-       trace_printk("%s:Mode settings: "                               \
-                       "ref_to_sync: H = %d V = %d, "                  \
-                       "sync_width: H = %d V = %d, "                   \
-                       "back_porch: H = %d V = %d, "                   \
-                       "active: H = %d V = %d, "                       \
-                       "front_porch: H = %d V = %d, "                  \
-                       "pclk = %d, stereo mode = %d\n",                \
-                       dc->ndev->name,                                 \
-                       mode.h_ref_to_sync, mode.v_ref_to_sync,         \
-                       mode.h_sync_width, mode.v_sync_width,           \
-                       mode.h_back_porch, mode.v_back_porch,           \
-                       mode.h_active, mode.v_active,                   \
-                       mode.h_front_porch, mode.v_front_porch,         \
-                       mode.pclk, mode.stereo_mode);                   \
-       } while (0)
 
 static inline void tegra_dc_io_start(struct tegra_dc *dc)
 {
@@ -212,7 +45,7 @@ static inline unsigned long tegra_dc_readl(struct tegra_dc *dc,
                WARN(1, "DC is clock-gated.\n");
 
        ret = readl(dc->base + reg * 4);
-       trace_printk("readl %p=%#08lx\n", dc->base + reg * 4, ret);
+       trace_display_readl(dc, ret, dc->base + reg * 4);
        return ret;
 }
 
@@ -223,7 +56,7 @@ static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long val,
        if (!tegra_is_clk_enabled(dc->clk))
                WARN(1, "DC is clock-gated.\n");
 
-       trace_printk("writel %p=%#08lx\n", dc->base + reg * 4, val);
+       trace_display_writel(dc, val, dc->base + reg * 4);
        writel(val, dc->base + reg * 4);
 }
 
diff --git a/drivers/video/tegra/dc/dc_priv_defs.h b/drivers/video/tegra/dc/dc_priv_defs.h
new file mode 100644 (file)
index 0000000..6c022a4
--- /dev/null
@@ -0,0 +1,179 @@
+
+/*
+ * drivers/video/tegra/dc/dc_priv.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Author: Erik Gilling <konkers@android.com>
+ *
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __DRIVERS_VIDEO_TEGRA_DC_DC_PRIV_DEFS_H
+#define __DRIVERS_VIDEO_TEGRA_DC_DC_PRIV_DEFS_H
+#include <linux/io.h>
+#include <linux/mutex.h>
+#include <linux/wait.h>
+#include <linux/fb.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/switch.h>
+#include <linux/nvhost.h>
+#include <linux/types.h>
+
+#include <mach/dc.h>
+
+#include <mach/tegra_dc_ext.h>
+#include <mach/clk.h>
+
+#include "dc_reg.h"
+
+#define WIN_IS_TILED(win)      ((win)->flags & TEGRA_WIN_FLAG_TILED)
+#define WIN_IS_ENABLED(win)    ((win)->flags & TEGRA_WIN_FLAG_ENABLED)
+
+#define NEED_UPDATE_EMC_ON_EVERY_FRAME (windows_idle_detection_time == 0)
+
+/* DDR: 8 bytes transfer per clock */
+#define DDR_BW_TO_FREQ(bw) ((bw) / 8)
+
+/* 29 bit offset for window clip number */
+#define CURSOR_CLIP_SHIFT_BITS(win)    (win << 29)
+#define CURSOR_CLIP_GET_WINDOW(reg)    ((reg >> 29) & 3)
+
+#if defined(CONFIG_TEGRA_EMC_TO_DDR_CLOCK)
+#define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * CONFIG_TEGRA_EMC_TO_DDR_CLOCK)
+#else
+#define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * 2)
+#endif
+
+#ifndef CONFIG_TEGRA_FPGA_PLATFORM
+#define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
+#else
+/* ignore underflows when on simulation and fpga platform */
+#define ALL_UF_INT (0)
+#endif
+
+struct tegra_dc;
+
+struct tegra_dc_blend {
+       unsigned z[DC_N_WINDOWS];
+       unsigned flags[DC_N_WINDOWS];
+};
+
+struct tegra_dc_out_ops {
+       /* initialize output.  dc clocks are not on at this point */
+       int (*init)(struct tegra_dc *dc);
+       /* destroy output.  dc clocks are not on at this point */
+       void (*destroy)(struct tegra_dc *dc);
+       /* detect connected display.  can sleep.*/
+       bool (*detect)(struct tegra_dc *dc);
+       /* enable output.  dc clocks are on at this point */
+       void (*enable)(struct tegra_dc *dc);
+       /* disable output.  dc clocks are on at this point */
+       void (*disable)(struct tegra_dc *dc);
+       /* hold output.  keeps dc clocks on. */
+       void (*hold)(struct tegra_dc *dc);
+       /* release output.  dc clocks may turn off after this. */
+       void (*release)(struct tegra_dc *dc);
+       /* idle routine of output.  dc clocks may turn off after this. */
+       void (*idle)(struct tegra_dc *dc);
+       /* suspend output.  dc clocks are on at this point */
+       void (*suspend)(struct tegra_dc *dc);
+       /* resume output.  dc clocks are on at this point */
+       void (*resume)(struct tegra_dc *dc);
+       /* mode filter. to provide a list of supported modes*/
+       bool (*mode_filter)(const struct tegra_dc *dc,
+                       struct fb_videomode *mode);
+};
+
+struct tegra_dc {
+       struct nvhost_device            *ndev;
+       struct tegra_dc_platform_data   *pdata;
+
+       struct resource                 *base_res;
+       void __iomem                    *base;
+       int                             irq;
+
+       struct clk                      *clk;
+       struct clk                      *emc_clk;
+       int                             emc_clk_rate;
+       int                             new_emc_clk_rate;
+       u32                             shift_clk_div;
+
+       bool                            connected;
+       bool                            enabled;
+       bool                            suspended;
+
+       struct tegra_dc_out             *out;
+       struct tegra_dc_out_ops         *out_ops;
+       void                            *out_data;
+
+       struct tegra_dc_mode            mode;
+       s64                             frametime_ns;
+
+       struct tegra_dc_win             windows[DC_N_WINDOWS];
+       struct tegra_dc_blend           blend;
+       int                             n_windows;
+#ifdef CONFIG_TEGRA_DC_CMU
+       struct tegra_dc_cmu             cmu;
+#endif
+       wait_queue_head_t               wq;
+       wait_queue_head_t               timestamp_wq;
+
+       struct mutex                    lock;
+       struct mutex                    one_shot_lock;
+
+       struct resource                 *fb_mem;
+       struct tegra_fb_info            *fb;
+
+       struct {
+               u32                     id;
+               u32                     min;
+               u32                     max;
+       } syncpt[DC_N_WINDOWS];
+       u32                             vblank_syncpt;
+
+       unsigned long                   underflow_mask;
+       struct work_struct              reset_work;
+
+#ifdef CONFIG_SWITCH
+       struct switch_dev               modeset_switch;
+#endif
+
+       struct completion               frame_end_complete;
+
+       struct work_struct              vblank_work;
+       long                            vblank_ref_count;
+
+       struct {
+               u64                     underflows;
+               u64                     underflows_a;
+               u64                     underflows_b;
+               u64                     underflows_c;
+       } stats;
+
+       struct tegra_dc_ext             *ext;
+
+       struct tegra_dc_feature         *feature;
+       int                             gen1_blend_num;
+
+#ifdef CONFIG_DEBUG_FS
+       struct dentry                   *debugdir;
+#endif
+       struct tegra_dc_lut             fb_lut;
+       struct delayed_work             underflow_work;
+       u32                             one_shot_delay_ms;
+       struct delayed_work             one_shot_work;
+       s64                             frame_end_timestamp;
+};
+
+#endif
index e1536cc..ca1e700 100644 (file)
@@ -276,7 +276,7 @@ inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
 
        BUG_ON(!nvhost_module_powered_ext(nvhost_get_parent(dsi->dc->ndev)));
        ret = readl(dsi->base + reg * 4);
-       trace_printk("readl %p=%#08lx\n", dsi->base + reg * 4, ret);
+       trace_display_readl(dsi->dc, ret, dsi->base + reg * 4);
        return ret;
 }
 EXPORT_SYMBOL(tegra_dsi_readl);
@@ -284,7 +284,7 @@ EXPORT_SYMBOL(tegra_dsi_readl);
 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
 {
        BUG_ON(!nvhost_module_powered_ext(nvhost_get_parent(dsi->dc->ndev)));
-       trace_printk("writel %p=%#08x\n", dsi->base + reg * 4, val);
+       trace_display_writel(dsi->dc, val, dsi->base + reg * 4);
        writel(val, dsi->base + reg * 4);
 }
 EXPORT_SYMBOL(tegra_dsi_writel);
index 3fb1664..708852e 100644 (file)
@@ -285,10 +285,8 @@ static int tegra_dc_ext_set_windowattr(struct tegra_dc_ext *ext,
        if (timestamp_ns) {
                /* XXX: Should timestamping be overridden by "no_vsync" flag */
                tegra_dc_config_frame_end_intr(win->dc, true);
-               trace_printk("%s:Before timestamp wait\n", win->dc->ndev->name);
                err = wait_event_interruptible(win->dc->timestamp_wq,
                                tegra_dc_is_within_n_vsync(win->dc, timestamp_ns));
-               trace_printk("%s:After timestamp wait\n", win->dc->ndev->name);
                tegra_dc_config_frame_end_intr(win->dc, false);
        }
 #endif
index 961fc66..d31b71f 100644 (file)
@@ -973,14 +973,14 @@ unsigned long tegra_hdmi_readl(struct tegra_dc_hdmi_data *hdmi,
 {
        unsigned long ret;
        ret = readl(hdmi->base + reg * 4);
-       trace_printk("readl %p=%#08lx\n", hdmi->base + reg * 4, ret);
+       trace_display_readl(hdmi->dc, ret, hdmi->base + reg * 4);
        return ret;
 }
 
 void tegra_hdmi_writel(struct tegra_dc_hdmi_data *hdmi,
                                     unsigned long val, unsigned long reg)
 {
-       trace_printk("writel %p=%#08lx\n", hdmi->base + reg * 4, val);
+       trace_display_writel(hdmi->dc, val, hdmi->base + reg * 4);
        writel(val, hdmi->base + reg * 4);
 }
 
index 963ced6..2df036a 100644 (file)
@@ -22,6 +22,7 @@
 
 #include <mach/clk.h>
 #include <mach/dc.h>
+#include <trace/events/display.h>
 
 #include "dc_reg.h"
 #include "dc_priv.h"
@@ -230,7 +231,6 @@ int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
        rate = tegra_dc_clk_get_rate(dc);
 
        pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
-       trace_printk("%s:pclk=%ld\n", dc->ndev->name, pclk);
        if (pclk < (mode->pclk / 100 * 99) ||
            pclk > (mode->pclk / 100 * 109)) {
                dev_err(&dc->ndev->dev,
@@ -242,7 +242,6 @@ int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
        }
 
        div = (rate * 2 / pclk) - 2;
-       trace_printk("%s:div=%ld\n", dc->ndev->name, div);
 
        tegra_dc_writel(dc, 0x00010001,
                        DC_DISP_SHIFT_CLOCK_OPTIONS);
@@ -257,7 +256,7 @@ int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
        tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
        tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 
-       print_mode_info(dc, dc->mode);
+       trace_display_mode(dc, &dc->mode);
        return 0;
 }
 
index 0c10bed..0209a0d 100644 (file)
@@ -19,6 +19,7 @@
 #include <linux/types.h>
 #include <linux/moduleparam.h>
 #include <mach/dc.h>
+#include <trace/events/display.h>
 
 #include "dc_reg.h"
 #include "dc_config.h"
@@ -200,18 +201,15 @@ int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
        if (!windows[0]->dc->enabled)
                return -EFAULT;
 
+       trace_sync_windows(windows[0]->dc);
 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
        /* Don't want to timeout on simulator */
        ret = wait_event_interruptible(windows[0]->dc->wq,
                tegra_dc_windows_are_clean(windows, n));
 #else
-       trace_printk("%s:Before wait_event_interruptible_timeout\n",
-               windows[0]->dc->ndev->name);
        ret = wait_event_interruptible_timeout(windows[0]->dc->wq,
                tegra_dc_windows_are_clean(windows, n),
                HZ);
-       trace_printk("%s:After wait_event_interruptible_timeout\n",
-               windows[0]->dc->ndev->name);
 #endif
        return ret;
 }
@@ -315,6 +313,7 @@ int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
        int i;
 
        dc = windows[0]->dc;
+       trace_update_windows(dc);
 
        if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
                /* Acquire one_shot_lock to avoid race condition between
@@ -482,17 +481,7 @@ int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
 
                win->dirty = no_vsync ? 0 : 1;
 
-               dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
-                       "out_x=%u out_y=%u out_w=%u out_h=%u "
-                       "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
-                       __func__, win->idx, win->z,
-                       dfixed_trunc(win->x), dfixed_trunc(win->y),
-                       dfixed_trunc(win->w), dfixed_trunc(win->h),
-                       win->out_x, win->out_y, win->out_w, win->out_h,
-                       win->fmt, yuvp, Bpp, filter_h, filter_v);
-               trace_printk("%s:win%u in:%ux%u out:%ux%u fmt=%d\n",
-                       dc->ndev->name, win->idx, dfixed_trunc(win->w),
-                       dfixed_trunc(win->h), win->out_w, win->out_h, win->fmt);
+               trace_window_update(dc, win);
        }
 
        if (update_blend_par || update_blend_seq) {
@@ -534,7 +523,6 @@ int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
                update_mask |= NC_HOST_TRIG;
 
        tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
-       trace_printk("%s:update_mask=%#lx\n", dc->ndev->name, update_mask);
 
        tegra_dc_release_dc_out(dc);
        mutex_unlock(&dc->lock);
diff --git a/include/trace/events/display.h b/include/trace/events/display.h
new file mode 100644 (file)
index 0000000..c4e6853
--- /dev/null
@@ -0,0 +1,260 @@
+/*
+ * include/trace/events/display.h
+ *
+ * Display event logging to ftrace.
+ *
+ * Copyright (c) 2012, NVIDIA CORPORATION, All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM display
+
+#if !defined(_TRACE_DISPLAY_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_DISPLAY_H
+
+#include "../../../drivers/video/tegra/dc/dc_priv_defs.h"
+#include <linux/tracepoint.h>
+
+DECLARE_EVENT_CLASS(display_basic_template,
+       TP_PROTO(struct tegra_dc *dc),
+       TP_ARGS(dc),
+       TP_STRUCT__entry(
+               __field(        bool,           enabled)
+               __field(        u8,             dev_id)
+               __field(        int,            bw_rate)
+               __field(        int,            new_bw_rate)
+               __field(        int,            underflows_a)
+               __field(        int,            underflows_b)
+               __field(        int,            underflows_c)
+       ),
+       TP_fast_assign(
+               __entry->enabled = dc->enabled;
+               __entry->dev_id = dc->ndev->dev.id;
+               __entry->bw_rate = dc->emc_clk_rate;
+               __entry->new_bw_rate = dc->new_emc_clk_rate;
+               __entry->underflows_a = dc->stats.underflows_a;
+               __entry->underflows_b = dc->stats.underflows_b;
+               __entry->underflows_c = dc->stats.underflows_c;
+       ),
+       TP_printk("dc%u enabled=%d bw_rate=%d new_bw_rate=%d underflows=%d/%d/%d",
+               __entry->dev_id, __entry->enabled,
+               __entry->bw_rate, __entry->new_bw_rate,
+               __entry->underflows_a, __entry->underflows_b,
+               __entry->underflows_c)
+);
+
+DEFINE_EVENT(display_basic_template, display_enable,
+       TP_PROTO(struct tegra_dc *dc),
+       TP_ARGS(dc)
+);
+
+DEFINE_EVENT(display_basic_template, display_disable,
+       TP_PROTO(struct tegra_dc *dc),
+       TP_ARGS(dc)
+);
+
+DEFINE_EVENT(display_basic_template, display_suspend,
+       TP_PROTO(struct tegra_dc *dc),
+       TP_ARGS(dc)
+);
+
+DEFINE_EVENT(display_basic_template, display_resume,
+       TP_PROTO(struct tegra_dc *dc),
+       TP_ARGS(dc)
+);
+
+DEFINE_EVENT(display_basic_template, display_reset,
+       TP_PROTO(struct tegra_dc *dc),
+       TP_ARGS(dc)
+);
+
+DEFINE_EVENT(display_basic_template, update_windows,
+       TP_PROTO(struct tegra_dc *dc),
+       TP_ARGS(dc)
+);
+
+DEFINE_EVENT(display_basic_template, sync_windows,
+       TP_PROTO(struct tegra_dc *dc),
+       TP_ARGS(dc)
+);
+
+DEFINE_EVENT(display_basic_template, clear_bandwidth,
+       TP_PROTO(struct tegra_dc *dc),
+       TP_ARGS(dc)
+);
+
+DEFINE_EVENT(display_basic_template, program_bandwidth,
+       TP_PROTO(struct tegra_dc *dc),
+       TP_ARGS(dc)
+);
+
+DEFINE_EVENT(display_basic_template, set_dynamic_emc,
+       TP_PROTO(struct tegra_dc *dc),
+       TP_ARGS(dc)
+);
+
+DEFINE_EVENT(display_basic_template, underflow,
+       TP_PROTO(struct tegra_dc *dc),
+       TP_ARGS(dc)
+);
+
+TRACE_EVENT(display_syncpt_flush,
+       TP_PROTO(struct tegra_dc *dc, u32 id, u32 min, u32 max),
+       TP_ARGS(dc, id, min, max),
+       TP_STRUCT__entry(
+               __field(        bool,           enabled)
+               __field(        u8,             dev_id)
+               __field(        u32,            syncpt_id)
+               __field(        u32,            syncpt_min)
+               __field(        u32,            syncpt_max)
+       ),
+       TP_fast_assign(
+               __entry->enabled = dc->enabled;
+               __entry->dev_id = dc->ndev->dev.id;
+               __entry->syncpt_id = id;
+               __entry->syncpt_min = min;
+               __entry->syncpt_max = max;
+       ),
+       TP_printk("dc%u enabled=%d syncpt: id=%x min=%x max=%x",
+               __entry->dev_id, __entry->enabled,
+               __entry->syncpt_id, __entry->syncpt_min, __entry->syncpt_max)
+);
+
+DECLARE_EVENT_CLASS(display_io_template,
+       TP_PROTO(struct tegra_dc *dc, unsigned long val, const void *reg),
+       TP_ARGS(dc, val, reg),
+       TP_STRUCT__entry(
+               __field(        bool,           enabled)
+               __field(        u8,             dev_id)
+               __field(        const void *,   reg)
+               __field(        u32,            val)
+       ),
+       TP_fast_assign(
+               __entry->enabled = dc->enabled;
+               __entry->dev_id = dc->ndev->dev.id;
+               __entry->reg = reg;
+               __entry->val = val;
+       ),
+       TP_printk("dc%u enabled=%d reg=%p val=0x%08x",
+               __entry->dev_id, __entry->enabled,
+               __entry->reg, __entry->val)
+);
+
+DEFINE_EVENT(display_io_template, display_writel,
+       TP_PROTO(struct tegra_dc *dc, unsigned long val, const void *reg),
+       TP_ARGS(dc, val, reg)
+);
+
+DEFINE_EVENT(display_io_template, display_readl,
+       TP_PROTO(struct tegra_dc *dc, unsigned long val, const void *reg),
+       TP_ARGS(dc, val, reg)
+);
+
+TRACE_EVENT(display_mode,
+       TP_PROTO(struct tegra_dc *dc, struct tegra_dc_mode *mode),
+       TP_ARGS(dc, mode),
+       TP_STRUCT__entry(
+               __field(        bool,           enabled)
+               __field(        u8,             dev_id)
+               __field(        unsigned long,  pclk)
+               __field(        unsigned short, h_active)
+               __field(        unsigned short, v_active)
+               __field(        unsigned short, h_front_porch)
+               __field(        unsigned short, v_front_porch)
+               __field(        unsigned short, h_back_porch)
+               __field(        unsigned short, v_back_porch)
+               __field(        unsigned short, h_ref_to_sync)
+               __field(        unsigned short, v_ref_to_sync)
+               __field(        unsigned short, h_sync_width)
+               __field(        unsigned short, v_sync_width)
+               __field(        bool,           stereo_mode)
+       ),
+       TP_fast_assign(
+               __entry->enabled = dc->enabled;
+               __entry->dev_id = dc->ndev->dev.id;
+               __entry->pclk = mode->pclk;
+               __entry->stereo_mode = mode->stereo_mode;
+               __entry->h_active = mode->h_active;
+               __entry->v_active = mode->v_active;
+               __entry->h_front_porch = mode->h_front_porch;
+               __entry->v_front_porch = mode->v_front_porch;
+               __entry->h_back_porch = mode->h_back_porch;
+               __entry->v_back_porch = mode->v_back_porch;
+               __entry->h_sync_width = mode->h_sync_width;
+               __entry->v_sync_width = mode->v_sync_width;
+               __entry->h_ref_to_sync = mode->h_ref_to_sync;
+               __entry->v_ref_to_sync = mode->v_ref_to_sync;
+       ),
+       TP_printk("dc%u enabled=%d "
+                "ref_to_sync: H=%d V=%d "
+                "sync_width: H=%d V=%d "
+                "back_porch: H=%d V=%d "
+                "active: H=%d V=%d "
+                "front_porch: H=%d V=%d "
+                "pclk=%ld stereo mode=%d\n",
+               __entry->dev_id, __entry->enabled,
+                __entry->h_ref_to_sync, __entry->v_ref_to_sync,
+                __entry->h_sync_width, __entry->v_sync_width,
+                __entry->h_back_porch, __entry->v_back_porch,
+                __entry->h_active, __entry->v_active,
+                __entry->h_front_porch, __entry->v_front_porch,
+                __entry->pclk, __entry->stereo_mode
+       )
+);
+
+TRACE_EVENT(window_update,
+       TP_PROTO(struct tegra_dc *dc, struct tegra_dc_win *win),
+       TP_ARGS(dc, win),
+       TP_STRUCT__entry(
+               __field(        bool,           enabled)
+               __field(        u8,             dev_id)
+               __field(        u32,            win_fmt)
+               __field(        unsigned short, win_x)
+               __field(        unsigned short, win_y)
+               __field(        unsigned short, win_w)
+               __field(        unsigned short, win_h)
+               __field(        unsigned short, win_out_x)
+               __field(        unsigned short, win_out_y)
+               __field(        unsigned short, win_out_w)
+               __field(        unsigned short, win_out_h)
+       ),
+       TP_fast_assign(
+               __entry->enabled = dc->enabled;
+               __entry->dev_id = dc->ndev->dev.id;
+               __entry->win_fmt = win->fmt;
+               __entry->win_x = dfixed_trunc(win->x);
+               __entry->win_y = dfixed_trunc(win->y);
+               __entry->win_w = dfixed_trunc(win->w);
+               __entry->win_h = dfixed_trunc(win->h);
+               __entry->win_out_x = win->out_x;
+               __entry->win_out_y = win->out_y;
+               __entry->win_out_w = win->out_w;
+               __entry->win_out_h = win->out_h;
+       ),
+       TP_printk("dc%u enabled=%d fmt=%#x in=[x:%u y:%u w:%u h:%u] "
+               "out=[x:%u y:%u w:%u h:%u] ",
+               __entry->dev_id, __entry->enabled, __entry->win_fmt,
+               __entry->win_x, __entry->win_y,
+               __entry->win_w, __entry->win_h,
+               __entry->win_out_x, __entry->win_out_y,
+               __entry->win_out_w, __entry->win_out_h
+       )
+);
+#endif /* _TRACE_DISPLAY_H */
+
+/* This part must be outside protection */
+#include <trace/define_trace.h>