V4L/DVB (9475): cx18: Disable write retries for registers that always change - part 1.
Andy Walls [Sun, 26 Oct 2008 02:27:06 +0000 (23:27 -0300)]
cx18: Disable write retries for registers that always change - part 1.
Interrupt related registers will likely not read back the value we just wrote.
Disable retries for these registers for now to avoid accidently discarding
interrupts.  More intelligent read back verification criteria are needed for
these and other registers (e.g. GPIO line registers), which will be addressed in
subsequent changes.

Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

drivers/media/video/cx18/cx18-io.c
drivers/media/video/cx18/cx18-irq.c
drivers/media/video/cx18/cx18-mailbox.c

index 700ab94..31be5e8 100644 (file)
@@ -218,7 +218,7 @@ void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
 {
        u32 r;
-       cx18_write_reg(cx, val, SW1_INT_STATUS);
+       cx18_write_reg_noretry(cx, val, SW1_INT_STATUS);
        r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
        cx18_write_reg(cx, r | val, SW1_INT_ENABLE_PCI);
 }
@@ -233,7 +233,7 @@ void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
 void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
 {
        u32 r;
-       cx18_write_reg(cx, val, SW2_INT_STATUS);
+       cx18_write_reg_noretry(cx, val, SW2_INT_STATUS);
        r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
        cx18_write_reg(cx, r | val, SW2_INT_ENABLE_PCI);
 }
index 360330f..447fc9c 100644 (file)
@@ -149,9 +149,9 @@ irqreturn_t cx18_irq_handler(int irq, void *dev_id)
        sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU;
        sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask;
 
-       cx18_write_reg(cx, sw2&sw2_mask, SW2_INT_STATUS);
-       cx18_write_reg(cx, sw1&sw1_mask, SW1_INT_STATUS);
-       cx18_write_reg(cx, hw2&hw2_mask, HW2_INT_CLR_STATUS);
+       cx18_write_reg_noretry(cx, sw2&sw2_mask, SW2_INT_STATUS);
+       cx18_write_reg_noretry(cx, sw1&sw1_mask, SW1_INT_STATUS);
+       cx18_write_reg_noretry(cx, hw2&hw2_mask, HW2_INT_CLR_STATUS);
 
        if (sw1 || sw2 || hw2)
                CX18_DEBUG_HI_IRQ("SW1: %x  SW2: %x  HW2: %x\n", sw1, sw2, hw2);
index 9d18dd2..87f7c8e 100644 (file)
@@ -176,7 +176,7 @@ long cx18_mb_ack(struct cx18 *cx, const struct cx18_mailbox *mb)
 
        cx18_setup_page(cx, SCB_OFFSET);
        cx18_write_sync(cx, mb->request, &ack_mb->ack);
-       cx18_write_reg(cx, ack_irq, SW2_INT_SET);
+       cx18_write_reg_noretry(cx, ack_irq, SW2_INT_SET);
        return 0;
 }
 
@@ -225,7 +225,7 @@ static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
        }
        if (info->flags & API_FAST)
                timeout /= 2;
-       cx18_write_reg(cx, irq, SW1_INT_SET);
+       cx18_write_reg_noretry(cx, irq, SW1_INT_SET);
 
        while (!sig && cx18_readl(cx, &mb->ack) != cx18_readl(cx, &mb->request)
               && cnt < 660) {