Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Fri, 26 Mar 2010 22:10:56 +0000 (15:10 -0700)]
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86, amd: Restrict usage of c1e_idle()
  x86: Fix placement of FIX_OHCI1394_BASE
  x86: Handle legacy PIC interrupts on all the cpu's

arch/x86/include/asm/fixmap.h
arch/x86/include/asm/hw_irq.h
arch/x86/include/asm/msr-index.h
arch/x86/kernel/apic/io_apic.c
arch/x86/kernel/irqinit.c
arch/x86/kernel/process.c
arch/x86/kernel/smpboot.c

index 635f03b..d07b44f 100644 (file)
@@ -82,6 +82,9 @@ enum fixed_addresses {
 #endif
        FIX_DBGP_BASE,
        FIX_EARLYCON_MEM_BASE,
+#ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
+       FIX_OHCI1394_BASE,
+#endif
 #ifdef CONFIG_X86_LOCAL_APIC
        FIX_APIC_BASE,  /* local (CPU) APIC) -- required for SMP or not */
 #endif
@@ -132,9 +135,6 @@ enum fixed_addresses {
           (__end_of_permanent_fixed_addresses & (TOTAL_FIX_BTMAPS - 1))
         : __end_of_permanent_fixed_addresses,
        FIX_BTMAP_BEGIN = FIX_BTMAP_END + TOTAL_FIX_BTMAPS - 1,
-#ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
-       FIX_OHCI1394_BASE,
-#endif
 #ifdef CONFIG_X86_32
        FIX_WP_TEST,
 #endif
index a929c9e..46c0fe0 100644 (file)
@@ -133,6 +133,7 @@ extern void (*__initconst interrupt[NR_VECTORS-FIRST_EXTERNAL_VECTOR])(void);
 
 typedef int vector_irq_t[NR_VECTORS];
 DECLARE_PER_CPU(vector_irq_t, vector_irq);
+extern void setup_vector_irq(int cpu);
 
 #ifdef CONFIG_X86_IO_APIC
 extern void lock_vector_lock(void);
index 1cd58cd..4604e6a 100644 (file)
 #define MSR_AMD64_PATCH_LEVEL          0x0000008b
 #define MSR_AMD64_NB_CFG               0xc001001f
 #define MSR_AMD64_PATCH_LOADER         0xc0010020
+#define MSR_AMD64_OSVW_ID_LENGTH       0xc0010140
+#define MSR_AMD64_OSVW_STATUS          0xc0010141
 #define MSR_AMD64_IBSFETCHCTL          0xc0011030
 #define MSR_AMD64_IBSFETCHLINAD                0xc0011031
 #define MSR_AMD64_IBSFETCHPHYSAD       0xc0011032
index e4e0ddc..463de9a 100644 (file)
@@ -1268,6 +1268,14 @@ void __setup_vector_irq(int cpu)
        /* Mark the inuse vectors */
        for_each_irq_desc(irq, desc) {
                cfg = desc->chip_data;
+
+               /*
+                * If it is a legacy IRQ handled by the legacy PIC, this cpu
+                * will be part of the irq_cfg's domain.
+                */
+               if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
+                       cpumask_set_cpu(cpu, cfg->domain);
+
                if (!cpumask_test_cpu(cpu, cfg->domain))
                        continue;
                vector = cfg->vector;
index ef257fc..f01d390 100644 (file)
@@ -141,6 +141,28 @@ void __init init_IRQ(void)
        x86_init.irqs.intr_init();
 }
 
+/*
+ * Setup the vector to irq mappings.
+ */
+void setup_vector_irq(int cpu)
+{
+#ifndef CONFIG_X86_IO_APIC
+       int irq;
+
+       /*
+        * On most of the platforms, legacy PIC delivers the interrupts on the
+        * boot cpu. But there are certain platforms where PIC interrupts are
+        * delivered to multiple cpu's. If the legacy IRQ is handled by the
+        * legacy PIC, for the new cpu that is coming online, setup the static
+        * legacy vector to irq mapping:
+        */
+       for (irq = 0; irq < legacy_pic->nr_legacy_irqs; irq++)
+               per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq;
+#endif
+
+       __setup_vector_irq(cpu);
+}
+
 static void __init smp_intr_init(void)
 {
 #ifdef CONFIG_SMP
index ad95406..28ad9f4 100644 (file)
@@ -526,21 +526,37 @@ static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
 }
 
 /*
- * Check for AMD CPUs, which have potentially C1E support
+ * Check for AMD CPUs, where APIC timer interrupt does not wake up CPU from C1e.
+ * For more information see
+ * - Erratum #400 for NPT family 0xf and family 0x10 CPUs
+ * - Erratum #365 for family 0x11 (not affected because C1e not in use)
  */
 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
 {
+       u64 val;
        if (c->x86_vendor != X86_VENDOR_AMD)
-               return 0;
-
-       if (c->x86 < 0x0F)
-               return 0;
+               goto no_c1e_idle;
 
        /* Family 0x0f models < rev F do not have C1E */
-       if (c->x86 == 0x0f && c->x86_model < 0x40)
-               return 0;
+       if (c->x86 == 0x0F && c->x86_model >= 0x40)
+               return 1;
 
-       return 1;
+       if (c->x86 == 0x10) {
+               /*
+                * check OSVW bit for CPUs that are not affected
+                * by erratum #400
+                */
+               rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
+               if (val >= 2) {
+                       rdmsrl(MSR_AMD64_OSVW_STATUS, val);
+                       if (!(val & BIT(1)))
+                               goto no_c1e_idle;
+               }
+               return 1;
+       }
+
+no_c1e_idle:
+       return 0;
 }
 
 static cpumask_var_t c1e_mask;
index a02e80c..06d98ae 100644 (file)
@@ -247,7 +247,7 @@ static void __cpuinit smp_callin(void)
        /*
         * Need to setup vector mappings before we enable interrupts.
         */
-       __setup_vector_irq(smp_processor_id());
+       setup_vector_irq(smp_processor_id());
        /*
         * Get our bogomips.
         *