drm/radeon/dce6: add missing display reg for tiling setup
Alex Deucher [Fri, 5 Apr 2013 14:28:08 +0000 (10:28 -0400)]
commit 7c1c7c18fc752b2a1d07597286467ef186312463 upstream.

A new tiling config register for the display blocks was
added on DCE6.

May fix:
https://bugs.freedesktop.org/show_bug.cgi?id=62889
https://bugs.freedesktop.org/show_bug.cgi?id=57919

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

drivers/gpu/drm/radeon/ni.c
drivers/gpu/drm/radeon/nid.h
drivers/gpu/drm/radeon/si.c
drivers/gpu/drm/radeon/sid.h

index 7dffc57..0c3d182 100644 (file)
@@ -911,6 +911,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
        WREG32(GB_BACKEND_MAP, gb_backend_map);
        WREG32(GB_ADDR_CONFIG, gb_addr_config);
        WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
+       if (ASIC_IS_DCE6(rdev))
+               WREG32(DMIF_ADDR_CALC, gb_addr_config);
        WREG32(HDP_ADDR_CONFIG, gb_addr_config);
 
        /* primary versions */
index 2aa7046..d90b8b7 100644 (file)
 #define CAYMAN_MAX_TCC_MASK          0xFF
 
 #define DMIF_ADDR_CONFIG                               0xBD4
+
+/* DCE6 only */
+#define DMIF_ADDR_CALC                                 0xC00
+
 #define        SRBM_GFX_CNTL                                   0x0E44
 #define                RINGID(x)                                       (((x) & 0x3) << 0)
 #define                VMID(x)                                         (((x) & 0x7) << 0)
index 1197f21..5508ad7 100644 (file)
@@ -1799,6 +1799,7 @@ static void si_gpu_init(struct radeon_device *rdev)
        rdev->config.si.backend_map = gb_backend_map;
        WREG32(GB_ADDR_CONFIG, gb_addr_config);
        WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
+       WREG32(DMIF_ADDR_CALC, gb_addr_config);
        WREG32(HDP_ADDR_CONFIG, gb_addr_config);
 
        /* primary versions */
index 2c2bc63..45e240d 100644 (file)
@@ -55,6 +55,8 @@
 
 #define DMIF_ADDR_CONFIG                               0xBD4
 
+#define DMIF_ADDR_CALC                                 0xC00
+
 #define        SRBM_STATUS                                     0xE50
 
 #define        CC_SYS_RB_BACKEND_DISABLE                       0xe80