video: tegra: nvmap: enable iwb page pool if outer cache is present
Krishna Reddy [Wed, 20 Mar 2013 23:03:06 +0000 (16:03 -0700)]
If outer cache is not present, wb and iwb refer to same memory type
and page pool is not necessary.

Bug 1328248

Change-Id: I86713ccb4eb8d41b8129dd241dc72218039bbd26
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/256270
Reviewed-by: Ahung Cheng <ahcheng@nvidia.com>
Tested-by: Ahung Cheng <ahcheng@nvidia.com>
Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

drivers/video/tegra/nvmap/nvmap_handle.c

index e0f3c63..d4b7a60 100644 (file)
@@ -406,6 +406,16 @@ int nvmap_page_pool_init(struct nvmap_page_pool *pool, int flags)
        if (flags == NVMAP_HANDLE_CACHEABLE)
                return 0;
 
+#if !defined(CONFIG_OUTER_CACHE)
+       /* If outer cache is not enabled or don't exist, cacheable and
+        * inner cacheable memory are same. For cacheable memory, there
+        * is no need of page pool as there is no need to flush cache and
+        * change page attributes.
+        */
+       if (flags == NVMAP_HANDLE_INNER_CACHEABLE)
+               return 0;
+#endif
+
        si_meminfo(&info);
        if (!pool_size[flags] && !CONFIG_NVMAP_PAGE_POOL_SIZE)
                /* Use 3/8th of total ram for page pools.