arm: tegra: pl310: Enable dynamic clock gating and standy.
Krishna Reddy [Fri, 4 May 2012 02:16:24 +0000 (19:16 -0700)]
Bug 947861

Change-Id: Ib4ce7bfa3624562a766678a2ef20ebdcd3055d89
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/100462
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/common.c

index f0c0cb6..aef4201 100644 (file)
@@ -343,6 +343,7 @@ void tegra_init_cache(bool init)
        writel(0x770, p + L2X0_DATA_LATENCY_CTRL);
 #endif
 #endif
+       writel(0x3, p + L2X0_POWER_CTRL);
        aux_ctrl = readl(p + L2X0_CACHE_TYPE);
        aux_ctrl = (aux_ctrl & 0x700) << (17-8);
        aux_ctrl |= 0x7C000001;