ARM: tegra: mc: setup chip_specific fn ptrs before enabling interrupts
Chris Johnson [Mon, 29 Oct 2012 05:30:25 +0000 (10:30 +0530)]
There are instances when we see that the irq fires before we have setup
the actual chip specific function pointers causing a crash in the mc isr

Change-Id: Ied30c1aafca10d6a1b9745507455e40b55014dc9
Signed-off-by: Chris Johnson <cwj@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/159456
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

arch/arm/mach-tegra/mcerr.c

index 74a2c51..6a434e4 100644 (file)
@@ -326,15 +326,6 @@ static int __init tegra_mcerr_init(void)
        writel(reg, mc + MC_EMEM_ARB_OVERRIDE);
 #endif
 
-       if (request_irq(INT_MC_GENERAL, tegra_mc_error_isr, 0,
-                       "mc_status", NULL)) {
-               pr_err("%s: unable to register MC error interrupt\n", __func__);
-               ret = -ENXIO;
-       } else {
-               reg = MC_INT_EN_MASK;
-               writel(reg, mc + MC_INT_MASK);
-       }
-
        chip_specific.mcerr_type         = mcerr_default_type;
        chip_specific.mcerr_info         = mcerr_default_info;
        chip_specific.mcerr_info_update  = mcerr_default_info_update;
@@ -348,6 +339,15 @@ static int __init tegra_mcerr_init(void)
         */
        mcerr_chip_specific_setup(&chip_specific);
 
+       if (request_irq(INT_MC_GENERAL, tegra_mc_error_isr, 0,
+                       "mc_status", NULL)) {
+               pr_err("%s: unable to register MC error interrupt\n", __func__);
+               ret = -ENXIO;
+       } else {
+               reg = MC_INT_EN_MASK;
+               writel(reg, mc + MC_INT_MASK);
+       }
+
        /*
         * Init the debugfs node for reporting errors from the MC. If this
         * fails thats a shame, but not a big enough deal to warrent failing