Merge branch 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur...
Linus Torvalds [Mon, 7 Nov 2011 00:58:33 +0000 (16:58 -0800)]
* 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm:
  ARM: PXA: fix includes in pxa2xx_cm_x2xx PCMCIA driver
  ARM: PXA: fix gpio-pxa.h build errors
  ARM: 7142/1: davinci: mark GPIO implementation complex
  ARM: 7134/1: Revert "EXYNOS4: Fix routing timer interrupt to offline CPU"
  ARM: PXA: eseries: fix eseries_register_clks section mismatch warning
  ARM: PXA: fix lubbock PCMCIA driver build error

377 files changed:
Documentation/power/freezing-of-tasks.txt
Documentation/power/runtime_pm.txt
Documentation/watchdog/convert_drivers_to_kernel_api.txt [new file with mode: 0644]
MAINTAINERS
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/configs/exynos4_defconfig
arch/arm/mach-exynos/Kconfig [moved from arch/arm/mach-exynos4/Kconfig with 76% similarity]
arch/arm/mach-exynos/Makefile [moved from arch/arm/mach-exynos4/Makefile with 88% similarity]
arch/arm/mach-exynos/Makefile.boot [moved from arch/arm/mach-exynos4/Makefile.boot with 100% similarity]
arch/arm/mach-exynos/clock-exynos4210.c [moved from arch/arm/mach-exynos4/clock-exynos4210.c with 100% similarity]
arch/arm/mach-exynos/clock-exynos4212.c [moved from arch/arm/mach-exynos4/clock-exynos4212.c with 100% similarity]
arch/arm/mach-exynos/clock.c [moved from arch/arm/mach-exynos4/clock.c with 86% similarity]
arch/arm/mach-exynos/cpu.c [moved from arch/arm/mach-exynos4/cpu.c with 90% similarity]
arch/arm/mach-exynos/cpuidle.c [moved from arch/arm/mach-exynos4/cpuidle.c with 100% similarity]
arch/arm/mach-exynos/dev-ahci.c [moved from arch/arm/mach-exynos4/dev-ahci.c with 100% similarity]
arch/arm/mach-exynos/dev-audio.c [moved from arch/arm/mach-exynos4/dev-audio.c with 100% similarity]
arch/arm/mach-exynos/dev-dwmci.c [moved from arch/arm/mach-exynos4/dev-dwmci.c with 100% similarity]
arch/arm/mach-exynos/dev-pd.c [moved from arch/arm/mach-exynos4/dev-pd.c with 100% similarity]
arch/arm/mach-exynos/dev-sysmmu.c [moved from arch/arm/mach-exynos4/dev-sysmmu.c with 100% similarity]
arch/arm/mach-exynos/dma.c [moved from arch/arm/mach-exynos4/dma.c with 98% similarity]
arch/arm/mach-exynos/headsmp.S [moved from arch/arm/mach-exynos4/headsmp.S with 100% similarity]
arch/arm/mach-exynos/hotplug.c [moved from arch/arm/mach-exynos4/hotplug.c with 100% similarity]
arch/arm/mach-exynos/include/mach/debug-macro.S [moved from arch/arm/mach-exynos4/include/mach/debug-macro.S with 100% similarity]
arch/arm/mach-exynos/include/mach/dma.h [moved from arch/arm/mach-exynos4/include/mach/dma.h with 100% similarity]
arch/arm/mach-exynos/include/mach/dwmci.h [moved from arch/arm/mach-exynos4/include/mach/dwmci.h with 100% similarity]
arch/arm/mach-exynos/include/mach/entry-macro.S [moved from arch/arm/mach-exynos4/include/mach/entry-macro.S with 100% similarity]
arch/arm/mach-exynos/include/mach/exynos4-clock.h [moved from arch/arm/mach-exynos4/include/mach/exynos4-clock.h with 100% similarity]
arch/arm/mach-exynos/include/mach/gpio.h [moved from arch/arm/mach-exynos4/include/mach/gpio.h with 100% similarity]
arch/arm/mach-exynos/include/mach/hardware.h [moved from arch/arm/mach-exynos4/include/mach/hardware.h with 100% similarity]
arch/arm/mach-exynos/include/mach/io.h [moved from arch/arm/mach-exynos4/include/mach/io.h with 100% similarity]
arch/arm/mach-exynos/include/mach/irqs.h [moved from arch/arm/mach-exynos4/include/mach/irqs.h with 97% similarity]
arch/arm/mach-exynos/include/mach/map.h [moved from arch/arm/mach-exynos4/include/mach/map.h with 87% similarity]
arch/arm/mach-exynos/include/mach/memory.h [moved from arch/arm/mach-exynos4/include/mach/memory.h with 100% similarity]
arch/arm/mach-exynos/include/mach/pm-core.h [moved from arch/arm/mach-exynos4/include/mach/pm-core.h with 89% similarity]
arch/arm/mach-exynos/include/mach/pmu.h [moved from arch/arm/mach-exynos4/include/mach/pmu.h with 84% similarity]
arch/arm/mach-exynos/include/mach/regs-audss.h [moved from arch/arm/mach-exynos4/include/mach/regs-audss.h with 100% similarity]
arch/arm/mach-exynos/include/mach/regs-clock.h [moved from arch/arm/mach-exynos4/include/mach/regs-clock.h with 100% similarity]
arch/arm/mach-exynos/include/mach/regs-gpio.h [moved from arch/arm/mach-exynos4/include/mach/regs-gpio.h with 100% similarity]
arch/arm/mach-exynos/include/mach/regs-irq.h [moved from arch/arm/mach-exynos4/include/mach/regs-irq.h with 100% similarity]
arch/arm/mach-exynos/include/mach/regs-mct.h [moved from arch/arm/mach-exynos4/include/mach/regs-mct.h with 100% similarity]
arch/arm/mach-exynos/include/mach/regs-mem.h [moved from arch/arm/mach-exynos4/include/mach/regs-mem.h with 100% similarity]
arch/arm/mach-exynos/include/mach/regs-pmu.h [moved from arch/arm/mach-exynos4/include/mach/regs-pmu.h with 69% similarity]
arch/arm/mach-exynos/include/mach/regs-sysmmu.h [moved from arch/arm/mach-exynos4/include/mach/regs-sysmmu.h with 100% similarity]
arch/arm/mach-exynos/include/mach/regs-usb-phy.h [moved from arch/arm/mach-exynos4/include/mach/regs-usb-phy.h with 100% similarity]
arch/arm/mach-exynos/include/mach/sysmmu.h [moved from arch/arm/mach-exynos4/include/mach/sysmmu.h with 100% similarity]
arch/arm/mach-exynos/include/mach/system.h [moved from arch/arm/mach-exynos4/include/mach/system.h with 100% similarity]
arch/arm/mach-exynos/include/mach/timex.h [moved from arch/arm/mach-exynos4/include/mach/timex.h with 100% similarity]
arch/arm/mach-exynos/include/mach/uncompress.h [moved from arch/arm/mach-exynos4/include/mach/uncompress.h with 100% similarity]
arch/arm/mach-exynos/include/mach/vmalloc.h [moved from arch/arm/mach-exynos4/include/mach/vmalloc.h with 100% similarity]
arch/arm/mach-exynos/init.c [moved from arch/arm/mach-exynos4/init.c with 100% similarity]
arch/arm/mach-exynos/irq-combiner.c [moved from arch/arm/mach-exynos4/irq-combiner.c with 100% similarity]
arch/arm/mach-exynos/irq-eint.c [moved from arch/arm/mach-exynos4/irq-eint.c with 100% similarity]
arch/arm/mach-exynos/mach-armlex4210.c [moved from arch/arm/mach-exynos4/mach-armlex4210.c with 100% similarity]
arch/arm/mach-exynos/mach-nuri.c [moved from arch/arm/mach-exynos4/mach-nuri.c with 85% similarity]
arch/arm/mach-exynos/mach-origen.c [new file with mode: 0644]
arch/arm/mach-exynos/mach-smdk4x12.c [moved from arch/arm/mach-exynos4/mach-smdk4x12.c with 100% similarity]
arch/arm/mach-exynos/mach-smdkv310.c [moved from arch/arm/mach-exynos4/mach-smdkv310.c with 88% similarity]
arch/arm/mach-exynos/mach-universal_c210.c [moved from arch/arm/mach-exynos4/mach-universal_c210.c with 67% similarity]
arch/arm/mach-exynos/mct.c [moved from arch/arm/mach-exynos4/mct.c with 91% similarity]
arch/arm/mach-exynos/platsmp.c [moved from arch/arm/mach-exynos4/platsmp.c with 100% similarity]
arch/arm/mach-exynos/pm.c [moved from arch/arm/mach-exynos4/pm.c with 98% similarity]
arch/arm/mach-exynos/pmu.c [new file with mode: 0644]
arch/arm/mach-exynos/setup-fimc.c [moved from arch/arm/mach-exynos4/setup-fimc.c with 100% similarity]
arch/arm/mach-exynos/setup-fimd0.c [moved from arch/arm/mach-exynos4/setup-fimd0.c with 100% similarity]
arch/arm/mach-exynos/setup-i2c0.c [moved from arch/arm/mach-exynos4/setup-i2c0.c with 100% similarity]
arch/arm/mach-exynos/setup-i2c1.c [moved from arch/arm/mach-exynos4/setup-i2c1.c with 100% similarity]
arch/arm/mach-exynos/setup-i2c2.c [moved from arch/arm/mach-exynos4/setup-i2c2.c with 100% similarity]
arch/arm/mach-exynos/setup-i2c3.c [moved from arch/arm/mach-exynos4/setup-i2c3.c with 100% similarity]
arch/arm/mach-exynos/setup-i2c4.c [moved from arch/arm/mach-exynos4/setup-i2c4.c with 100% similarity]
arch/arm/mach-exynos/setup-i2c5.c [moved from arch/arm/mach-exynos4/setup-i2c5.c with 100% similarity]
arch/arm/mach-exynos/setup-i2c6.c [moved from arch/arm/mach-exynos4/setup-i2c6.c with 100% similarity]
arch/arm/mach-exynos/setup-i2c7.c [moved from arch/arm/mach-exynos4/setup-i2c7.c with 100% similarity]
arch/arm/mach-exynos/setup-keypad.c [moved from arch/arm/mach-exynos4/setup-keypad.c with 100% similarity]
arch/arm/mach-exynos/setup-sdhci-gpio.c [moved from arch/arm/mach-exynos4/setup-sdhci-gpio.c with 100% similarity]
arch/arm/mach-exynos/setup-sdhci.c [new file with mode: 0644]
arch/arm/mach-exynos/setup-usb-phy.c [moved from arch/arm/mach-exynos4/setup-usb-phy.c with 100% similarity]
arch/arm/mach-exynos4/include/mach/clkdev.h [deleted file]
arch/arm/mach-exynos4/mach-origen.c [deleted file]
arch/arm/mach-exynos4/pmu.c [deleted file]
arch/arm/mach-exynos4/setup-sdhci.c [deleted file]
arch/arm/mach-mmp/Makefile
arch/arm/mach-mmp/brownstone.c
arch/arm/mach-mmp/include/mach/mmp2.h
arch/arm/mach-mmp/include/mach/sram.h [new file with mode: 0644]
arch/arm/mach-mmp/mmp2.c
arch/arm/mach-mmp/sram.c [new file with mode: 0644]
arch/arm/mach-s3c2410/Kconfig
arch/arm/mach-s3c2410/include/mach/fb.h
arch/arm/mach-s3c2410/include/mach/gpio-fns.h
arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
arch/arm/mach-s3c2410/include/mach/gpio-track.h
arch/arm/mach-s3c2410/include/mach/irqs.h
arch/arm/mach-s3c2410/include/mach/map.h
arch/arm/mach-s3c2410/include/mach/pm-core.h
arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
arch/arm/mach-s3c2410/mach-h1940.c
arch/arm/mach-s3c2410/mach-qt2410.c
arch/arm/mach-s3c2410/s3c2410.c
arch/arm/mach-s3c2412/gpio.c [new file with mode: 0644]
arch/arm/mach-s3c2416/Kconfig
arch/arm/mach-s3c2416/clock.c
arch/arm/mach-s3c2416/s3c2416.c
arch/arm/mach-s3c2416/setup-sdhci.c
arch/arm/mach-s3c2440/Kconfig
arch/arm/mach-s3c2440/mach-rx1950.c
arch/arm/mach-s3c2440/s3c2440.c
arch/arm/mach-s3c2440/s3c2442.c
arch/arm/mach-s3c2443/Kconfig
arch/arm/mach-s3c2443/clock.c
arch/arm/mach-s3c2443/s3c2443.c
arch/arm/mach-s3c64xx/Kconfig
arch/arm/mach-s3c64xx/Makefile
arch/arm/mach-s3c64xx/clock.c
arch/arm/mach-s3c64xx/cpu.c
arch/arm/mach-s3c64xx/dev-onenand1.c [deleted file]
arch/arm/mach-s3c64xx/dma.c
arch/arm/mach-s3c64xx/gpiolib.c [deleted file]
arch/arm/mach-s3c64xx/include/mach/clkdev.h [deleted file]
arch/arm/mach-s3c64xx/include/mach/crag6410.h [new file with mode: 0644]
arch/arm/mach-s3c64xx/include/mach/pll.h [deleted file]
arch/arm/mach-s3c64xx/include/mach/pm-core.h
arch/arm/mach-s3c64xx/include/mach/pwm-clock.h [deleted file]
arch/arm/mach-s3c64xx/include/mach/regs-sys.h
arch/arm/mach-s3c64xx/mach-anw6410.c
arch/arm/mach-s3c64xx/mach-crag6410-module.c [new file with mode: 0644]
arch/arm/mach-s3c64xx/mach-crag6410.c
arch/arm/mach-s3c64xx/mach-hmt.c
arch/arm/mach-s3c64xx/mach-mini6410.c
arch/arm/mach-s3c64xx/mach-ncp.c
arch/arm/mach-s3c64xx/mach-real6410.c
arch/arm/mach-s3c64xx/mach-smartq5.c
arch/arm/mach-s3c64xx/mach-smartq7.c
arch/arm/mach-s3c64xx/mach-smdk6400.c
arch/arm/mach-s3c64xx/mach-smdk6410.c
arch/arm/mach-s3c64xx/pm.c
arch/arm/mach-s3c64xx/s3c6400.c
arch/arm/mach-s3c64xx/s3c6410.c
arch/arm/mach-s3c64xx/setup-sdhci.c
arch/arm/mach-s5p64x0/Kconfig
arch/arm/mach-s5p64x0/Makefile
arch/arm/mach-s5p64x0/clock-s5p6440.c
arch/arm/mach-s5p64x0/clock-s5p6450.c
arch/arm/mach-s5p64x0/cpu.c
arch/arm/mach-s5p64x0/include/mach/clkdev.h [deleted file]
arch/arm/mach-s5p64x0/include/mach/irqs.h
arch/arm/mach-s5p64x0/include/mach/map.h
arch/arm/mach-s5p64x0/include/mach/pm-core.h [new file with mode: 0644]
arch/arm/mach-s5p64x0/include/mach/pwm-clock.h [deleted file]
arch/arm/mach-s5p64x0/include/mach/regs-clock.h
arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
arch/arm/mach-s5p64x0/irq-eint.c
arch/arm/mach-s5p64x0/irq-pm.c [new file with mode: 0644]
arch/arm/mach-s5p64x0/mach-smdk6440.c
arch/arm/mach-s5p64x0/mach-smdk6450.c
arch/arm/mach-s5p64x0/pm.c [new file with mode: 0644]
arch/arm/mach-s5p64x0/setup-fb-24bpp.c [new file with mode: 0644]
arch/arm/mach-s5pc100/clock.c
arch/arm/mach-s5pc100/dma.c
arch/arm/mach-s5pc100/include/mach/clkdev.h [deleted file]
arch/arm/mach-s5pc100/include/mach/pwm-clock.h [deleted file]
arch/arm/mach-s5pc100/setup-sdhci.c
arch/arm/mach-s5pv210/Kconfig
arch/arm/mach-s5pv210/Makefile
arch/arm/mach-s5pv210/clock.c
arch/arm/mach-s5pv210/cpu.c
arch/arm/mach-s5pv210/dma.c
arch/arm/mach-s5pv210/include/mach/clkdev.h [deleted file]
arch/arm/mach-s5pv210/include/mach/irqs.h
arch/arm/mach-s5pv210/include/mach/map.h
arch/arm/mach-s5pv210/include/mach/pm-core.h
arch/arm/mach-s5pv210/include/mach/pwm-clock.h [deleted file]
arch/arm/mach-s5pv210/include/mach/regs-clock.h
arch/arm/mach-s5pv210/mach-goni.c
arch/arm/mach-s5pv210/setup-sdhci.c
arch/arm/mach-s5pv210/sleep.S [deleted file]
arch/arm/plat-s3c24xx/Kconfig
arch/arm/plat-s3c24xx/Makefile
arch/arm/plat-s3c24xx/dev-uart.c [new file with mode: 0644]
arch/arm/plat-s3c24xx/devs.c [deleted file]
arch/arm/plat-s3c24xx/gpio.c [deleted file]
arch/arm/plat-s3c24xx/gpiolib.c [deleted file]
arch/arm/plat-s3c24xx/include/mach/clkdev.h [deleted file]
arch/arm/plat-s3c24xx/include/mach/pwm-clock.h [deleted file]
arch/arm/plat-s3c24xx/include/plat/pll.h [deleted file]
arch/arm/plat-s3c24xx/include/plat/regs-iis.h [deleted file]
arch/arm/plat-s3c24xx/include/plat/regs-spi.h [deleted file]
arch/arm/plat-s3c24xx/s3c2443-clock.c
arch/arm/plat-s5p/Kconfig
arch/arm/plat-s5p/Makefile
arch/arm/plat-s5p/cpu.c
arch/arm/plat-s5p/dev-csis0.c [deleted file]
arch/arm/plat-s5p/dev-csis1.c [deleted file]
arch/arm/plat-s5p/dev-ehci.c [deleted file]
arch/arm/plat-s5p/dev-fimc0.c [deleted file]
arch/arm/plat-s5p/dev-fimc1.c [deleted file]
arch/arm/plat-s5p/dev-fimc2.c [deleted file]
arch/arm/plat-s5p/dev-fimc3.c [deleted file]
arch/arm/plat-s5p/dev-fimd0.c [deleted file]
arch/arm/plat-s5p/dev-mfc.c
arch/arm/plat-s5p/dev-onenand.c [deleted file]
arch/arm/plat-s5p/dev-pmu.c [deleted file]
arch/arm/plat-s5p/include/plat/pll.h [deleted file]
arch/arm/plat-s5p/irq-gpioint.c
arch/arm/plat-s5p/sleep.S [moved from arch/arm/mach-exynos4/sleep.S with 81% similarity]
arch/arm/plat-samsung/Kconfig
arch/arm/plat-samsung/Makefile
arch/arm/plat-samsung/adc.c
arch/arm/plat-samsung/dev-adc.c [deleted file]
arch/arm/plat-samsung/dev-asocdma.c [deleted file]
arch/arm/plat-samsung/dev-backlight.c
arch/arm/plat-samsung/dev-fb.c [deleted file]
arch/arm/plat-samsung/dev-hsmmc.c [deleted file]
arch/arm/plat-samsung/dev-hsmmc1.c [deleted file]
arch/arm/plat-samsung/dev-hsmmc2.c [deleted file]
arch/arm/plat-samsung/dev-hsmmc3.c [deleted file]
arch/arm/plat-samsung/dev-hwmon.c [deleted file]
arch/arm/plat-samsung/dev-i2c0.c [deleted file]
arch/arm/plat-samsung/dev-i2c1.c [deleted file]
arch/arm/plat-samsung/dev-i2c2.c [deleted file]
arch/arm/plat-samsung/dev-i2c3.c [deleted file]
arch/arm/plat-samsung/dev-i2c4.c [deleted file]
arch/arm/plat-samsung/dev-i2c5.c [deleted file]
arch/arm/plat-samsung/dev-i2c6.c [deleted file]
arch/arm/plat-samsung/dev-i2c7.c [deleted file]
arch/arm/plat-samsung/dev-ide.c [deleted file]
arch/arm/plat-samsung/dev-keypad.c [deleted file]
arch/arm/plat-samsung/dev-nand.c [deleted file]
arch/arm/plat-samsung/dev-onenand.c [deleted file]
arch/arm/plat-samsung/dev-pwm.c [deleted file]
arch/arm/plat-samsung/dev-rtc.c [deleted file]
arch/arm/plat-samsung/dev-ts.c [deleted file]
arch/arm/plat-samsung/dev-usb-hsotg.c [deleted file]
arch/arm/plat-samsung/dev-usb.c [deleted file]
arch/arm/plat-samsung/dev-wdt.c [deleted file]
arch/arm/plat-samsung/devs.c [new file with mode: 0644]
arch/arm/plat-samsung/gpio-config.c [deleted file]
arch/arm/plat-samsung/gpio.c [deleted file]
arch/arm/plat-samsung/include/plat/adc-core.h
arch/arm/plat-samsung/include/plat/audio-simtec.h [moved from arch/arm/plat-s3c24xx/include/plat/audio-simtec.h with 95% similarity]
arch/arm/plat-samsung/include/plat/camport.h [moved from arch/arm/plat-s5p/include/plat/camport.h with 86% similarity]
arch/arm/plat-samsung/include/plat/common-smdk.h [moved from arch/arm/plat-s3c24xx/include/plat/common-smdk.h with 87% similarity]
arch/arm/plat-samsung/include/plat/cpu-freq-core.h [moved from arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h with 98% similarity]
arch/arm/plat-samsung/include/plat/cpu.h
arch/arm/plat-samsung/include/plat/devs.h
arch/arm/plat-samsung/include/plat/ehci.h [moved from arch/arm/plat-s5p/include/plat/ehci.h with 84% similarity]
arch/arm/plat-samsung/include/plat/exynos4.h [moved from arch/arm/plat-s5p/include/plat/exynos4.h with 87% similarity]
arch/arm/plat-samsung/include/plat/fb-s3c2410.h [new file with mode: 0644]
arch/arm/plat-samsung/include/plat/fb.h
arch/arm/plat-samsung/include/plat/fiq.h [moved from arch/arm/plat-s3c24xx/include/plat/fiq.h with 88% similarity]
arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
arch/arm/plat-samsung/include/plat/gpio-cfg.h
arch/arm/plat-samsung/include/plat/gpio-core.h
arch/arm/plat-samsung/include/plat/gpio-fns.h [new file with mode: 0644]
arch/arm/plat-samsung/include/plat/iic.h
arch/arm/plat-samsung/include/plat/irq.h [moved from arch/arm/plat-s3c24xx/include/plat/irq.h with 81% similarity]
arch/arm/plat-samsung/include/plat/irqs.h [moved from arch/arm/plat-s5p/include/plat/irqs.h with 93% similarity]
arch/arm/plat-samsung/include/plat/mci.h [moved from arch/arm/plat-s3c24xx/include/plat/mci.h with 90% similarity]
arch/arm/plat-samsung/include/plat/mfc.h [moved from arch/arm/plat-s5p/include/plat/mfc.h with 90% similarity]
arch/arm/plat-samsung/include/plat/mipi_csis.h [moved from arch/arm/plat-s5p/include/plat/mipi_csis.h with 90% similarity]
arch/arm/plat-samsung/include/plat/pll.h [new file with mode: 0644]
arch/arm/plat-samsung/include/plat/pll6553x.h [deleted file]
arch/arm/plat-samsung/include/plat/pm.h
arch/arm/plat-samsung/include/plat/pwm-clock.h [moved from arch/arm/mach-exynos4/include/mach/pwm-clock.h with 68% similarity]
arch/arm/plat-samsung/include/plat/regs-adc.h
arch/arm/plat-samsung/include/plat/regs-dma.h [moved from arch/arm/plat-s3c24xx/include/plat/regs-dma.h with 58% similarity]
arch/arm/plat-samsung/include/plat/regs-iis.h [new file with mode: 0644]
arch/arm/plat-samsung/include/plat/regs-spi.h [new file with mode: 0644]
arch/arm/plat-samsung/include/plat/regs-srom.h [moved from arch/arm/plat-s5p/include/plat/regs-srom.h with 89% similarity]
arch/arm/plat-samsung/include/plat/regs-udc.h [moved from arch/arm/plat-s3c24xx/include/plat/regs-udc.h with 51% similarity]
arch/arm/plat-samsung/include/plat/reset.h [moved from arch/arm/plat-s5p/include/plat/reset.h with 66% similarity]
arch/arm/plat-samsung/include/plat/s3c2410.h [moved from arch/arm/plat-s3c24xx/include/plat/s3c2410.h with 93% similarity]
arch/arm/plat-samsung/include/plat/s3c2412.h [moved from arch/arm/plat-s3c24xx/include/plat/s3c2412.h with 92% similarity]
arch/arm/plat-samsung/include/plat/s3c2416.h [moved from arch/arm/plat-s3c24xx/include/plat/s3c2416.h with 92% similarity]
arch/arm/plat-samsung/include/plat/s3c2443.h [moved from arch/arm/plat-s3c24xx/include/plat/s3c2443.h with 87% similarity]
arch/arm/plat-samsung/include/plat/s3c244x.h [moved from arch/arm/plat-s3c24xx/include/plat/s3c244x.h with 94% similarity]
arch/arm/plat-samsung/include/plat/s3c6400.h [moved from arch/arm/mach-s3c64xx/include/mach/s3c6400.h with 94% similarity]
arch/arm/plat-samsung/include/plat/s3c6410.h [moved from arch/arm/mach-s3c64xx/include/mach/s3c6410.h with 93% similarity]
arch/arm/plat-samsung/include/plat/s5p-clock.h [moved from arch/arm/plat-s5p/include/plat/s5p-clock.h with 96% similarity]
arch/arm/plat-samsung/include/plat/s5p-time.h [moved from arch/arm/plat-s5p/include/plat/s5p-time.h with 94% similarity]
arch/arm/plat-samsung/include/plat/s5p6440.h [moved from arch/arm/plat-s5p/include/plat/s5p6440.h with 94% similarity]
arch/arm/plat-samsung/include/plat/s5p6450.h [moved from arch/arm/plat-s5p/include/plat/s5p6450.h with 94% similarity]
arch/arm/plat-samsung/include/plat/s5pc100.h [moved from arch/arm/plat-s5p/include/plat/s5pc100.h with 94% similarity]
arch/arm/plat-samsung/include/plat/s5pv210.h [moved from arch/arm/plat-s5p/include/plat/s5pv210.h with 94% similarity]
arch/arm/plat-samsung/include/plat/sdhci.h
arch/arm/plat-samsung/include/plat/sysmmu.h [moved from arch/arm/plat-s5p/include/plat/sysmmu.h with 96% similarity]
arch/arm/plat-samsung/include/plat/system-reset.h [moved from arch/arm/plat-s5p/include/plat/system-reset.h with 92% similarity]
arch/arm/plat-samsung/include/plat/tv-core.h [new file with mode: 0644]
arch/arm/plat-samsung/include/plat/udc.h [moved from arch/arm/plat-s3c24xx/include/plat/udc.h with 95% similarity]
arch/arm/plat-samsung/include/plat/usb-phy.h [moved from arch/arm/plat-s5p/include/plat/usb-phy.h with 83% similarity]
arch/arm/plat-samsung/platformdata.c
arch/arm/plat-samsung/pm-gpio.c
arch/arm/plat-samsung/pm.c
arch/arm/plat-samsung/pwm-clock.c
arch/arm/plat-samsung/pwm.c
drivers/acpi/sleep.c
drivers/base/power/runtime.c
drivers/firmware/edd.c
drivers/gpio/Kconfig
drivers/gpio/Makefile
drivers/gpio/gpio-exynos4.c [deleted file]
drivers/gpio/gpio-plat-samsung.c [deleted file]
drivers/gpio/gpio-s5pc100.c [deleted file]
drivers/gpio/gpio-s5pv210.c [deleted file]
drivers/gpio/gpio-samsung.c [new file with mode: 0644]
drivers/hwmon/coretemp.c
drivers/hwmon/w83627ehf.c
drivers/scsi/bnx2fc/bnx2fc.h
drivers/scsi/bnx2fc/bnx2fc_els.c
drivers/scsi/bnx2fc/bnx2fc_fcoe.c
drivers/scsi/bnx2fc/bnx2fc_io.c
drivers/scsi/device_handler/scsi_dh.c
drivers/scsi/device_handler/scsi_dh_alua.c
drivers/scsi/fcoe/fcoe.c
drivers/scsi/hosts.c
drivers/scsi/hpsa.c
drivers/scsi/hpsa.h
drivers/scsi/hpsa_cmd.h
drivers/scsi/ipr.c
drivers/scsi/ipr.h
drivers/scsi/isci/host.c
drivers/scsi/isci/init.c
drivers/scsi/isci/port.c
drivers/scsi/isci/port.h
drivers/scsi/isci/probe_roms.h
drivers/scsi/isci/remote_device.c
drivers/scsi/isci/remote_device.h
drivers/scsi/isci/request.c
drivers/scsi/isci/request.h
drivers/scsi/isci/task.c
drivers/scsi/isci/task.h
drivers/scsi/libfc/fc_exch.c
drivers/scsi/libfc/fc_lport.c
drivers/scsi/mpt2sas/mpi/mpi2.h
drivers/scsi/mpt2sas/mpi/mpi2_cnfg.h
drivers/scsi/mpt2sas/mpi/mpi2_ioc.h
drivers/scsi/mpt2sas/mpt2sas_base.c
drivers/scsi/mpt2sas/mpt2sas_base.h
drivers/scsi/mpt2sas/mpt2sas_config.c
drivers/scsi/mpt2sas/mpt2sas_ctl.c
drivers/scsi/mpt2sas/mpt2sas_scsih.c
drivers/scsi/mvsas/mv_init.c
drivers/scsi/pmcraid.c
drivers/scsi/qla2xxx/qla_isr.c
drivers/scsi/scsi_lib.c
drivers/scsi/scsi_scan.c
drivers/scsi/scsi_transport_iscsi.c
drivers/scsi/sd.c
drivers/scsi/sd.h
drivers/scsi/st.c
drivers/usb/core/driver.c
drivers/watchdog/Kconfig
drivers/watchdog/coh901327_wdt.c
drivers/watchdog/eurotechwdt.c
drivers/watchdog/iTCO_wdt.c
drivers/watchdog/mpcore_wdt.c
drivers/watchdog/octeon-wdt-main.c
drivers/watchdog/s3c2410_wdt.c
drivers/watchdog/sb_wdog.c
drivers/watchdog/sc520_wdt.c
drivers/watchdog/w83627hf_wdt.c
drivers/watchdog/wdt.c
drivers/watchdog/wdt_pci.c
drivers/watchdog/wm831x_wdt.c
include/linux/cpu.h
include/linux/freezer.h
include/linux/opp.h
include/linux/pci_ids.h
kernel/cpu.c
kernel/freezer.c
kernel/power/qos.c
sound/core/control.c
sound/pci/hda/hda_intel.c
sound/pci/hda/hda_local.h
sound/pci/hda/patch_realtek.c
sound/soc/samsung/dma.c
sound/usb/misc/ua101.c

index 38b5724..316c2ba 100644 (file)
@@ -22,12 +22,12 @@ try_to_freeze_tasks() that sets TIF_FREEZE for all of the freezable tasks and
 either wakes them up, if they are kernel threads, or sends fake signals to them,
 if they are user space processes.  A task that has TIF_FREEZE set, should react
 to it by calling the function called refrigerator() (defined in
-kernel/power/process.c), which sets the task's PF_FROZEN flag, changes its state
+kernel/freezer.c), which sets the task's PF_FROZEN flag, changes its state
 to TASK_UNINTERRUPTIBLE and makes it loop until PF_FROZEN is cleared for it.
 Then, we say that the task is 'frozen' and therefore the set of functions
 handling this mechanism is referred to as 'the freezer' (these functions are
-defined in kernel/power/process.c and include/linux/freezer.h).  User space
-processes are generally frozen before kernel threads.
+defined in kernel/power/process.c, kernel/freezer.c & include/linux/freezer.h).
+User space processes are generally frozen before kernel threads.
 
 It is not recommended to call refrigerator() directly.  Instead, it is
 recommended to use the try_to_freeze() function (defined in
@@ -95,7 +95,7 @@ after the memory for the image has been freed, we don't want tasks to allocate
 additional memory and we prevent them from doing that by freezing them earlier.
 [Of course, this also means that device drivers should not allocate substantial
 amounts of memory from their .suspend() callbacks before hibernation, but this
-is e separate issue.]
+is a separate issue.]
 
 3. The third reason is to prevent user space processes and some kernel threads
 from interfering with the suspending and resuming of devices.  A user space
index 0e85608..5336149 100644 (file)
@@ -789,6 +789,16 @@ will behave normally, not taking the autosuspend delay into account.
 Similarly, if the power.use_autosuspend field isn't set then the autosuspend
 helper functions will behave just like the non-autosuspend counterparts.
 
+Under some circumstances a driver or subsystem may want to prevent a device
+from autosuspending immediately, even though the usage counter is zero and the
+autosuspend delay time has expired.  If the ->runtime_suspend() callback
+returns -EAGAIN or -EBUSY, and if the next autosuspend delay expiration time is
+in the future (as it normally would be if the callback invoked
+pm_runtime_mark_last_busy()), the PM core will automatically reschedule the
+autosuspend.  The ->runtime_suspend() callback can't do this rescheduling
+itself because no suspend requests of any kind are accepted while the device is
+suspending (i.e., while the callback is running).
+
 The implementation is well suited for asynchronous use in interrupt contexts.
 However such use inevitably involves races, because the PM core can't
 synchronize ->runtime_suspend() callbacks with the arrival of I/O requests.
diff --git a/Documentation/watchdog/convert_drivers_to_kernel_api.txt b/Documentation/watchdog/convert_drivers_to_kernel_api.txt
new file mode 100644 (file)
index 0000000..ae1e900
--- /dev/null
@@ -0,0 +1,195 @@
+Converting old watchdog drivers to the watchdog framework
+by Wolfram Sang <w.sang@pengutronix.de>
+=========================================================
+
+Before the watchdog framework came into the kernel, every driver had to
+implement the API on its own. Now, as the framework factored out the common
+components, those drivers can be lightened making it a user of the framework.
+This document shall guide you for this task. The necessary steps are described
+as well as things to look out for.
+
+
+Remove the file_operations struct
+---------------------------------
+
+Old drivers define their own file_operations for actions like open(), write(),
+etc... These are now handled by the framework and just call the driver when
+needed. So, in general, the 'file_operations' struct and assorted functions can
+go. Only very few driver-specific details have to be moved to other functions.
+Here is a overview of the functions and probably needed actions:
+
+- open: Everything dealing with resource management (file-open checks, magic
+  close preparations) can simply go. Device specific stuff needs to go to the
+  driver specific start-function. Note that for some drivers, the start-function
+  also serves as the ping-function. If that is the case and you need start/stop
+  to be balanced (clocks!), you are better off refactoring a separate start-function.
+
+- close: Same hints as for open apply.
+
+- write: Can simply go, all defined behaviour is taken care of by the framework,
+  i.e. ping on write and magic char ('V') handling.
+
+- ioctl: While the driver is allowed to have extensions to the IOCTL interface,
+  the most common ones are handled by the framework, supported by some assistance
+  from the driver:
+
+       WDIOC_GETSUPPORT:
+               Returns the mandatory watchdog_info struct from the driver
+
+       WDIOC_GETSTATUS:
+               Needs the status-callback defined, otherwise returns 0
+
+       WDIOC_GETBOOTSTATUS:
+               Needs the bootstatus member properly set. Make sure it is 0 if you
+               don't have further support!
+
+       WDIOC_SETOPTIONS:
+               No preparations needed
+
+       WDIOC_KEEPALIVE:
+               If wanted, options in watchdog_info need to have WDIOF_KEEPALIVEPING
+               set
+
+       WDIOC_SETTIMEOUT:
+               Options in watchdog_info need to have WDIOF_SETTIMEOUT set
+               and a set_timeout-callback has to be defined. The core will also
+               do limit-checking, if min_timeout and max_timeout in the watchdog
+               device are set. All is optional.
+
+       WDIOC_GETTIMEOUT:
+               No preparations needed
+
+  Other IOCTLs can be served using the ioctl-callback. Note that this is mainly
+  intended for porting old drivers; new drivers should not invent private IOCTLs.
+  Private IOCTLs are processed first. When the callback returns with
+  -ENOIOCTLCMD, the IOCTLs of the framework will be tried, too. Any other error
+  is directly given to the user.
+
+Example conversion:
+
+-static const struct file_operations s3c2410wdt_fops = {
+-       .owner          = THIS_MODULE,
+-       .llseek         = no_llseek,
+-       .write          = s3c2410wdt_write,
+-       .unlocked_ioctl = s3c2410wdt_ioctl,
+-       .open           = s3c2410wdt_open,
+-       .release        = s3c2410wdt_release,
+-};
+
+Check the functions for device-specific stuff and keep it for later
+refactoring. The rest can go.
+
+
+Remove the miscdevice
+---------------------
+
+Since the file_operations are gone now, you can also remove the 'struct
+miscdevice'. The framework will create it on watchdog_dev_register() called by
+watchdog_register_device().
+
+-static struct miscdevice s3c2410wdt_miscdev = {
+-       .minor          = WATCHDOG_MINOR,
+-       .name           = "watchdog",
+-       .fops           = &s3c2410wdt_fops,
+-};
+
+
+Remove obsolete includes and defines
+------------------------------------
+
+Because of the simplifications, a few defines are probably unused now. Remove
+them. Includes can be removed, too. For example:
+
+- #include <linux/fs.h>
+- #include <linux/miscdevice.h> (if MODULE_ALIAS_MISCDEV is not used)
+- #include <linux/uaccess.h> (if no custom IOCTLs are used)
+
+
+Add the watchdog operations
+---------------------------
+
+All possible callbacks are defined in 'struct watchdog_ops'. You can find it
+explained in 'watchdog-kernel-api.txt' in this directory. start(), stop() and
+owner must be set, the rest are optional. You will easily find corresponding
+functions in the old driver. Note that you will now get a pointer to the
+watchdog_device as a parameter to these functions, so you probably have to
+change the function header. Other changes are most likely not needed, because
+here simply happens the direct hardware access. If you have device-specific
+code left from the above steps, it should be refactored into these callbacks.
+
+Here is a simple example:
+
++static struct watchdog_ops s3c2410wdt_ops = {
++       .owner = THIS_MODULE,
++       .start = s3c2410wdt_start,
++       .stop = s3c2410wdt_stop,
++       .ping = s3c2410wdt_keepalive,
++       .set_timeout = s3c2410wdt_set_heartbeat,
++};
+
+A typical function-header change looks like:
+
+-static void s3c2410wdt_keepalive(void)
++static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
+ {
+...
++
++       return 0;
+ }
+
+...
+
+-       s3c2410wdt_keepalive();
++       s3c2410wdt_keepalive(&s3c2410_wdd);
+
+
+Add the watchdog device
+-----------------------
+
+Now we need to create a 'struct watchdog_device' and populate it with the
+necessary information for the framework. The struct is also explained in detail
+in 'watchdog-kernel-api.txt' in this directory. We pass it the mandatory
+watchdog_info struct and the newly created watchdog_ops. Often, old drivers
+have their own record-keeping for things like bootstatus and timeout using
+static variables. Those have to be converted to use the members in
+watchdog_device. Note that the timeout values are unsigned int. Some drivers
+use signed int, so this has to be converted, too.
+
+Here is a simple example for a watchdog device:
+
++static struct watchdog_device s3c2410_wdd = {
++       .info = &s3c2410_wdt_ident,
++       .ops = &s3c2410wdt_ops,
++};
+
+
+Register the watchdog device
+----------------------------
+
+Replace misc_register(&miscdev) with watchdog_register_device(&watchdog_dev).
+Make sure the return value gets checked and the error message, if present,
+still fits. Also convert the unregister case.
+
+-       ret = misc_register(&s3c2410wdt_miscdev);
++       ret = watchdog_register_device(&s3c2410_wdd);
+
+...
+
+-       misc_deregister(&s3c2410wdt_miscdev);
++       watchdog_unregister_device(&s3c2410_wdd);
+
+
+Update the Kconfig-entry
+------------------------
+
+The entry for the driver now needs to select WATCHDOG_CORE:
+
++       select WATCHDOG_CORE
+
+
+Create a patch and send it to upstream
+--------------------------------------
+
+Make sure you understood Documentation/SubmittingPatches and send your patch to
+linux-watchdog@vger.kernel.org. We are looking forward to it :)
+
index a6afe34..6388a96 100644 (file)
@@ -2387,7 +2387,7 @@ F:        include/linux/netfilter_bridge/ebt_*.h
 F:     net/bridge/netfilter/ebt*.c
 
 ECRYPT FILE SYSTEM
-M:     Tyler Hicks <tyhicks@linux.vnet.ibm.com>
+M:     Tyler Hicks <tyhicks@canonical.com>
 M:     Dustin Kirkland <kirkland@canonical.com>
 L:     ecryptfs@vger.kernel.org
 W:     https://launchpad.net/ecryptfs
index fe6b052..44789ef 100644 (file)
@@ -595,6 +595,7 @@ config ARCH_MMP
        select TICK_ONESHOT
        select PLAT_PXA
        select SPARSE_IRQ
+       select GENERIC_ALLOCATOR
        help
          Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 
@@ -769,6 +770,7 @@ config ARCH_S3C64XX
        select CPU_V6
        select ARM_VIC
        select HAVE_CLK
+       select HAVE_TCM
        select CLKDEV_LOOKUP
        select NO_IOPORT
        select ARCH_USES_GETTIMEOFFSET
@@ -777,9 +779,6 @@ config ARCH_S3C64XX
        select SAMSUNG_CLKSRC
        select SAMSUNG_IRQ_VIC_TIMER
        select S3C_GPIO_TRACK
-       select S3C_GPIO_PULL_UPDOWN
-       select S3C_GPIO_CFG_S3C24XX
-       select S3C_GPIO_CFG_S3C64XX
        select S3C_DEV_NAND
        select USB_ARCH_HAS_OHCI
        select SAMSUNG_GPIOLIB_4BIT
@@ -838,8 +837,8 @@ config ARCH_S5PV210
        help
          Samsung S5PV210/S5PC110 series based systems
 
-config ARCH_EXYNOS4
-       bool "Samsung EXYNOS4"
+config ARCH_EXYNOS
+       bool "SAMSUNG EXYNOS"
        select CPU_V7
        select ARCH_SPARSEMEM_ENABLE
        select ARCH_HAS_HOLES_MEMORYMODEL
@@ -853,7 +852,7 @@ config ARCH_EXYNOS4
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
        select NEED_MACH_MEMORY_H
        help
-         Samsung EXYNOS4 series based systems
+         Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 
 config ARCH_SHARK
        bool "Shark"
@@ -1080,7 +1079,7 @@ source "arch/arm/mach-s5pc100/Kconfig"
 
 source "arch/arm/mach-s5pv210/Kconfig"
 
-source "arch/arm/mach-exynos4/Kconfig"
+source "arch/arm/mach-exynos/Kconfig"
 
 source "arch/arm/mach-shmobile/Kconfig"
 
@@ -2212,7 +2211,7 @@ menu "Power management options"
 source "kernel/power/Kconfig"
 
 config ARCH_SUSPEND_POSSIBLE
-       depends on !ARCH_S5P64X0 && !ARCH_S5PC100
+       depends on !ARCH_S5PC100
        depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
                CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
        def_bool y
index b7c2d37..dfcf3b0 100644 (file)
@@ -180,7 +180,7 @@ machine-$(CONFIG_ARCH_S3C64XX)              := s3c64xx
 machine-$(CONFIG_ARCH_S5P64X0)         := s5p64x0
 machine-$(CONFIG_ARCH_S5PC100)         := s5pc100
 machine-$(CONFIG_ARCH_S5PV210)         := s5pv210
-machine-$(CONFIG_ARCH_EXYNOS4)         := exynos4
+machine-$(CONFIG_ARCH_EXYNOS4)         := exynos
 machine-$(CONFIG_ARCH_SA1100)          := sa1100
 machine-$(CONFIG_ARCH_SHARK)           := shark
 machine-$(CONFIG_ARCH_SHMOBILE)        := shmobile
index cd40bb5..bffe68e 100644 (file)
@@ -4,19 +4,18 @@ CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_EXYNOS4=y
+CONFIG_ARCH_EXYNOS=y
 CONFIG_S3C_LOWLEVEL_UART_PORT=1
 CONFIG_MACH_SMDKC210=y
-CONFIG_MACH_SMDKV310=y
 CONFIG_MACH_ARMLEX4210=y
 CONFIG_MACH_UNIVERSAL_C210=y
 CONFIG_MACH_NURI=y
 CONFIG_MACH_ORIGEN=y
+CONFIG_MACH_SMDK4412=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
-CONFIG_HOTPLUG_CPU=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
@@ -61,13 +60,9 @@ CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_RT_MUTEXES=y
 CONFIG_DEBUG_SPINLOCK=y
 CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
-CONFIG_DEBUG_S3C_UART=1
 CONFIG_CRC_CCITT=y
similarity index 76%
rename from arch/arm/mach-exynos4/Kconfig
rename to arch/arm/mach-exynos/Kconfig
index 44013e0..724ec0f 100644 (file)
@@ -1,4 +1,4 @@
-# arch/arm/mach-exynos4/Kconfig
+# arch/arm/mach-exynos/Kconfig
 #
 # Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 #              http://www.samsung.com/
@@ -7,22 +7,47 @@
 
 # Configuration options for the EXYNOS4
 
-if ARCH_EXYNOS4
+if ARCH_EXYNOS
+
+menu "SAMSUNG EXYNOS SoCs Support"
+
+choice
+       prompt "EXYNOS System Type"
+       default ARCH_EXYNOS4
+
+config ARCH_EXYNOS4
+       bool "SAMSUNG EXYNOS4"
+       help
+         Samsung EXYNOS4 SoCs based systems
+
+endchoice
+
+comment "EXYNOS SoCs"
 
 config CPU_EXYNOS4210
-       bool
+       bool "SAMSUNG EXYNOS4210"
+       default y
+       depends on ARCH_EXYNOS4
        select SAMSUNG_DMADEV
        select ARM_CPU_SUSPEND if PM
+       select S5P_PM if PM
+       select S5P_SLEEP if PM
        help
          Enable EXYNOS4210 CPU support
 
 config SOC_EXYNOS4212
-       bool
+       bool "SAMSUNG EXYNOS4212"
+       default y
+       depends on ARCH_EXYNOS4
+       select S5P_PM if PM
+       select S5P_SLEEP if PM
        help
          Enable EXYNOS4212 SoC support
 
 config SOC_EXYNOS4412
-       bool
+       bool "SAMSUNG EXYNOS4412"
+       default y
+       depends on ARCH_EXYNOS4
        help
          Enable EXYNOS4412 SoC support
 
@@ -120,7 +145,7 @@ config EXYNOS4_SETUP_USB_PHY
 
 # machine support
 
-menu "EXYNOS4 Machines"
+if ARCH_EXYNOS4
 
 comment "EXYNOS4210 Boards"
 
@@ -137,6 +162,14 @@ config MACH_SMDKV310
        select S3C_DEV_RTC
        select S3C_DEV_WDT
        select S3C_DEV_I2C1
+       select S5P_DEV_FIMC0
+       select S5P_DEV_FIMC1
+       select S5P_DEV_FIMC2
+       select S5P_DEV_FIMC3
+       select S5P_DEV_I2C_HDMIPHY
+       select S5P_DEV_MFC
+       select S5P_DEV_TV
+       select S5P_DEV_USB_EHCI
        select S3C_DEV_HSMMC
        select S3C_DEV_HSMMC1
        select S3C_DEV_HSMMC2
@@ -151,6 +184,7 @@ config MACH_SMDKV310
        select EXYNOS4_SETUP_I2C1
        select EXYNOS4_SETUP_KEYPAD
        select EXYNOS4_SETUP_SDHCI
+       select EXYNOS4_SETUP_USB_PHY
        help
          Machine support for Samsung SMDKV310
 
@@ -176,19 +210,26 @@ config MACH_UNIVERSAL_C210
        select S5P_DEV_FIMC1
        select S5P_DEV_FIMC2
        select S5P_DEV_FIMC3
+       select S5P_DEV_CSIS0
+       select S5P_DEV_FIMD0
        select S3C_DEV_HSMMC
        select S3C_DEV_HSMMC2
        select S3C_DEV_HSMMC3
        select S3C_DEV_I2C1
        select S3C_DEV_I2C3
        select S3C_DEV_I2C5
+       select S5P_DEV_I2C_HDMIPHY
        select S5P_DEV_MFC
        select S5P_DEV_ONENAND
+       select S5P_DEV_TV
        select EXYNOS4_DEV_PD
+       select EXYNOS4_SETUP_FIMD0
        select EXYNOS4_SETUP_I2C1
        select EXYNOS4_SETUP_I2C3
        select EXYNOS4_SETUP_I2C5
        select EXYNOS4_SETUP_SDHCI
+       select EXYNOS4_SETUP_FIMC
+       select S5P_SETUP_MIPIPHY
        help
          Machine support for Samsung Mobile Universal S5PC210 Reference
          Board.
@@ -196,21 +237,33 @@ config MACH_UNIVERSAL_C210
 config MACH_NURI
        bool "Mobile NURI Board"
        select CPU_EXYNOS4210
+       select S5P_GPIO_INT
        select S3C_DEV_WDT
+       select S3C_DEV_RTC
+       select S5P_DEV_FIMD0
        select S3C_DEV_HSMMC
        select S3C_DEV_HSMMC2
        select S3C_DEV_HSMMC3
        select S3C_DEV_I2C1
        select S3C_DEV_I2C3
        select S3C_DEV_I2C5
+       select S5P_DEV_CSIS0
+       select S5P_DEV_FIMC0
+       select S5P_DEV_FIMC1
+       select S5P_DEV_FIMC2
+       select S5P_DEV_FIMC3
        select S5P_DEV_MFC
        select S5P_DEV_USB_EHCI
+       select S5P_SETUP_MIPIPHY
        select EXYNOS4_DEV_PD
+       select EXYNOS4_SETUP_FIMC
+       select EXYNOS4_SETUP_FIMD0
        select EXYNOS4_SETUP_I2C1
        select EXYNOS4_SETUP_I2C3
        select EXYNOS4_SETUP_I2C5
        select EXYNOS4_SETUP_SDHCI
        select EXYNOS4_SETUP_USB_PHY
+       select S5P_SETUP_MIPIPHY
        select SAMSUNG_DEV_PWM
        select SAMSUNG_DEV_ADC
        help
@@ -221,8 +274,23 @@ config MACH_ORIGEN
        select CPU_EXYNOS4210
        select S3C_DEV_RTC
        select S3C_DEV_WDT
+       select S3C_DEV_HSMMC
        select S3C_DEV_HSMMC2
+       select S5P_DEV_FIMC0
+       select S5P_DEV_FIMC1
+       select S5P_DEV_FIMC2
+       select S5P_DEV_FIMC3
+       select S5P_DEV_FIMD0
+       select S5P_DEV_I2C_HDMIPHY
+       select S5P_DEV_MFC
+       select S5P_DEV_TV
+       select S5P_DEV_USB_EHCI
+       select SAMSUNG_DEV_BACKLIGHT
+       select SAMSUNG_DEV_PWM
+       select EXYNOS4_DEV_PD
+       select EXYNOS4_SETUP_FIMD0
        select EXYNOS4_SETUP_SDHCI
+       select EXYNOS4_SETUP_USB_PHY
        help
          Machine support for ORIGEN based on Samsung EXYNOS4210
 
@@ -257,12 +325,11 @@ config MACH_SMDK4412
        select MACH_SMDK4212
        help
          Machine support for Samsung SMDK4412
+endif
 
-endmenu
-
-comment "Configuration for HSMMC bus width"
+if ARCH_EXYNOS4
 
-menu "Use 8-bit bus width"
+comment "Configuration for HSMMC 8-bit bus width"
 
 config EXYNOS4_SDHCI_CH0_8BIT
        bool "Channel 0 with 8-bit bus"
@@ -275,6 +342,7 @@ config EXYNOS4_SDHCI_CH2_8BIT
        help
          Support HSMMC Channel 2 8-bit bus.
          If selected, Channel 3 is disabled.
+endif
 
 endmenu
 
similarity index 88%
rename from arch/arm/mach-exynos4/Makefile
rename to arch/arm/mach-exynos/Makefile
index c9b2e1f..59069a3 100644 (file)
@@ -1,4 +1,4 @@
-# arch/arm/mach-exynos4/Makefile
+# arch/arm/mach-exynos/Makefile
 #
 # Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 #              http://www.samsung.com/
@@ -12,11 +12,11 @@ obj-                                :=
 
 # Core support for EXYNOS4 system
 
-obj-$(CONFIG_ARCH_EXYNOS4)     += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_ARCH_EXYNOS4)     += setup-i2c0.o irq-eint.o dma.o pmu.o
+obj-$(CONFIG_ARCH_EXYNOS4)     += cpu.o init.o clock.o irq-combiner.o setup-i2c0.o
+obj-$(CONFIG_ARCH_EXYNOS4)     += irq-eint.o dma.o pmu.o
 obj-$(CONFIG_CPU_EXYNOS4210)   += clock-exynos4210.o
 obj-$(CONFIG_SOC_EXYNOS4212)   += clock-exynos4212.o
-obj-$(CONFIG_PM)               += pm.o sleep.o
+obj-$(CONFIG_PM)               += pm.o
 obj-$(CONFIG_CPU_IDLE)         += cpuidle.o
 
 obj-$(CONFIG_SMP)              += platsmp.o headsmp.o
@@ -39,11 +39,11 @@ obj-$(CONFIG_MACH_SMDK4412)         += mach-smdk4x12.o
 
 # device support
 
-obj-y                                  += dev-audio.o
+obj-$(CONFIG_ARCH_EXYNOS4)             += dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)         += dev-ahci.o
 obj-$(CONFIG_EXYNOS4_DEV_PD)           += dev-pd.o
 obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)       += dev-sysmmu.o
-obj-$(CONFIG_EXYNOS4_DEV_DWMCI)        += dev-dwmci.o
+obj-$(CONFIG_EXYNOS4_DEV_DWMCI)                += dev-dwmci.o
 
 obj-$(CONFIG_EXYNOS4_SETUP_FIMC)       += setup-fimc.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMD0)      += setup-fimd0.o
@@ -57,5 +57,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7)      += setup-i2c7.o
 obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)     += setup-keypad.o
 obj-$(CONFIG_EXYNOS4_SETUP_SDHCI)      += setup-sdhci.o
 obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
-
 obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY)    += setup-usb-phy.o
similarity index 86%
rename from arch/arm/mach-exynos4/clock.c
rename to arch/arm/mach-exynos/clock.c
index e21952d..2894f0a 100644 (file)
@@ -151,6 +151,11 @@ static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
        return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
 }
 
+static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
+}
+
 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
 {
        return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
@@ -191,6 +196,16 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
        return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
 }
 
+static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
+static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
+}
+
 /* Core list of CMU_CPU side */
 
 static struct clksrc_clk clk_mout_apll = {
@@ -508,13 +523,43 @@ static struct clk init_clocks_off[] = {
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 9),
        }, {
+               .name           = "dac",
+               .devname        = "s5p-sdo",
+               .enable         = exynos4_clk_ip_tv_ctrl,
+               .ctrlbit        = (1 << 2),
+       }, {
+               .name           = "mixer",
+               .devname        = "s5p-mixer",
+               .enable         = exynos4_clk_ip_tv_ctrl,
+               .ctrlbit        = (1 << 1),
+       }, {
+               .name           = "vp",
+               .devname        = "s5p-mixer",
+               .enable         = exynos4_clk_ip_tv_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "hdmi",
+               .devname        = "exynos4-hdmi",
+               .enable         = exynos4_clk_ip_tv_ctrl,
+               .ctrlbit        = (1 << 3),
+       }, {
+               .name           = "hdmiphy",
+               .devname        = "exynos4-hdmi",
+               .enable         = exynos4_clk_hdmiphy_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "dacphy",
+               .devname        = "s5p-sdo",
+               .enable         = exynos4_clk_dac_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
                .name           = "dma",
-               .devname        = "s3c-pl330.0",
+               .devname        = "dma-pl330.0",
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 0),
        }, {
                .name           = "dma",
-               .devname        = "s3c-pl330.1",
+               .devname        = "dma-pl330.1",
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 1),
        }, {
@@ -635,6 +680,12 @@ static struct clk init_clocks_off[] = {
                .enable         = exynos4_clk_ip_peril_ctrl,
                .ctrlbit        = (1 << 13),
        }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-hdmiphy-i2c",
+               .parent         = &clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 14),
+       }, {
                .name           = "SYSMMU_MDMA",
                .enable         = exynos4_clk_ip_image_ctrl,
                .ctrlbit        = (1 << 5),
@@ -836,6 +887,81 @@ static struct clksrc_sources clkset_mout_mfc = {
        .nr_sources     = ARRAY_SIZE(clkset_mout_mfc_list),
 };
 
+static struct clk *clkset_sclk_dac_list[] = {
+       [0] = &clk_sclk_vpll.clk,
+       [1] = &clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources clkset_sclk_dac = {
+       .sources        = clkset_sclk_dac_list,
+       .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
+};
+
+static struct clksrc_clk clk_sclk_dac = {
+       .clk            = {
+               .name           = "sclk_dac",
+               .enable         = exynos4_clksrc_mask_tv_ctrl,
+               .ctrlbit        = (1 << 8),
+       },
+       .sources = &clkset_sclk_dac,
+       .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk clk_sclk_pixel = {
+       .clk            = {
+               .name           = "sclk_pixel",
+               .parent = &clk_sclk_vpll.clk,
+       },
+       .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
+};
+
+static struct clk *clkset_sclk_hdmi_list[] = {
+       [0] = &clk_sclk_pixel.clk,
+       [1] = &clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources clkset_sclk_hdmi = {
+       .sources        = clkset_sclk_hdmi_list,
+       .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk clk_sclk_hdmi = {
+       .clk            = {
+               .name           = "sclk_hdmi",
+               .enable         = exynos4_clksrc_mask_tv_ctrl,
+               .ctrlbit        = (1 << 0),
+       },
+       .sources = &clkset_sclk_hdmi,
+       .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
+};
+
+static struct clk *clkset_sclk_mixer_list[] = {
+       [0] = &clk_sclk_dac.clk,
+       [1] = &clk_sclk_hdmi.clk,
+};
+
+static struct clksrc_sources clkset_sclk_mixer = {
+       .sources        = clkset_sclk_mixer_list,
+       .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
+};
+
+static struct clksrc_clk clk_sclk_mixer = {
+       .clk            = {
+               .name           = "sclk_mixer",
+               .enable         = exynos4_clksrc_mask_tv_ctrl,
+               .ctrlbit        = (1 << 4),
+       },
+       .sources = &clkset_sclk_mixer,
+       .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk *sclk_tv[] = {
+       &clk_sclk_dac,
+       &clk_sclk_pixel,
+       &clk_sclk_hdmi,
+       &clk_sclk_mixer,
+};
+
 static struct clksrc_clk clk_dout_mmc0 = {
        .clk            = {
                .name           = "dout_mmc0",
@@ -1162,6 +1288,71 @@ static struct clk_ops exynos4_fout_apll_ops = {
        .get_rate = exynos4_fout_apll_get_rate,
 };
 
+static u32 vpll_div[][8] = {
+       {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
+       { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
+};
+
+static unsigned long exynos4_vpll_get_rate(struct clk *clk)
+{
+       return clk->rate;
+}
+
+static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
+{
+       unsigned int vpll_con0, vpll_con1 = 0;
+       unsigned int i;
+
+       /* Return if nothing changed */
+       if (clk->rate == rate)
+               return 0;
+
+       vpll_con0 = __raw_readl(S5P_VPLL_CON0);
+       vpll_con0 &= ~(0x1 << 27 |                                      \
+                       PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
+                       PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
+                       PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+       vpll_con1 = __raw_readl(S5P_VPLL_CON1);
+       vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
+                       PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
+                       PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
+
+       for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
+               if (vpll_div[i][0] == rate) {
+                       vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
+                       vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
+                       vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
+                       vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
+                       vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
+                       vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
+                       vpll_con0 |= vpll_div[i][7] << 27;
+                       break;
+               }
+       }
+
+       if (i == ARRAY_SIZE(vpll_div)) {
+               printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
+                               __func__);
+               return -EINVAL;
+       }
+
+       __raw_writel(vpll_con0, S5P_VPLL_CON0);
+       __raw_writel(vpll_con1, S5P_VPLL_CON1);
+
+       /* Wait for VPLL lock */
+       while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
+               continue;
+
+       clk->rate = rate;
+       return 0;
+}
+
+static struct clk_ops exynos4_vpll_ops = {
+       .get_rate = exynos4_vpll_get_rate,
+       .set_rate = exynos4_vpll_set_rate,
+};
+
 void __init_or_cpufreq exynos4_setup_clocks(void)
 {
        struct clk *xtal_clk;
@@ -1219,6 +1410,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
        clk_fout_apll.ops = &exynos4_fout_apll_ops;
        clk_fout_mpll.rate = mpll;
        clk_fout_epll.rate = epll;
+       clk_fout_vpll.ops = &exynos4_vpll_ops;
        clk_fout_vpll.rate = vpll;
 
        printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
@@ -1246,7 +1438,10 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
 }
 
 static struct clk *clks[] __initdata = {
-       /* Nothing here yet */
+       &clk_sclk_hdmi27m,
+       &clk_sclk_hdmiphy,
+       &clk_sclk_usbphy0,
+       &clk_sclk_usbphy1,
 };
 
 #ifdef CONFIG_PM_SLEEP
@@ -1280,17 +1475,17 @@ void __init exynos4_register_clocks(void)
        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
                s3c_register_clksrc(sysclks[ptr], 1);
 
+       for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
+               s3c_register_clksrc(sclk_tv[ptr], 1);
+
        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
-<<<<<<< HEAD
        register_syscore_ops(&exynos4_clock_syscore_ops);
-=======
        s3c24xx_register_clock(&dummy_apb_pclk);
 
->>>>>>> 4598fc2c94b68740e0269db03c98a1e7ad5af773
        s3c_pwmclk_init();
 }
similarity index 90%
rename from arch/arm/mach-exynos4/cpu.c
rename to arch/arm/mach-exynos/cpu.c
index a348434..90ec247 100644 (file)
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-exynos4/cpu.c
+/* linux/arch/arm/mach-exynos/cpu.c
  *
  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *             http://www.samsung.com
@@ -28,6 +28,7 @@
 #include <plat/fimc-core.h>
 #include <plat/iic-core.h>
 #include <plat/reset.h>
+#include <plat/tv-core.h>
 
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
@@ -39,28 +40,47 @@ extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
 
 /* Initial IO mappings */
-static struct map_desc exynos4_iodesc[] __initdata = {
+static struct map_desc exynos_iodesc[] __initdata = {
        {
                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
+               .pfn            = __phys_to_pfn(EXYNOS_PA_SYSTIMER),
                .length         = SZ_4K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_CMU,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
-               .length         = SZ_128K,
                .type           = MT_DEVICE,
        }, {
                .virtual        = (unsigned long)S5P_VA_PMU,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
+               .pfn            = __phys_to_pfn(EXYNOS_PA_PMU),
                .length         = SZ_64K,
                .type           = MT_DEVICE,
        }, {
                .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
+               .pfn            = __phys_to_pfn(EXYNOS_PA_COMBINER),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
        }, {
+               .virtual        = (unsigned long)S5P_VA_GIC_CPU,
+               .pfn            = __phys_to_pfn(EXYNOS_PA_GIC_CPU),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GIC_DIST,
+               .pfn            = __phys_to_pfn(EXYNOS_PA_GIC_DIST),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_UART,
+               .pfn            = __phys_to_pfn(S3C_PA_UART),
+               .length         = SZ_512K,
+               .type           = MT_DEVICE,
+       },
+};
+
+static struct map_desc exynos4_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S5P_VA_CMU,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
+               .length         = SZ_128K,
+               .type           = MT_DEVICE,
+       }, {
                .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
                .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
                .length         = SZ_8K,
@@ -91,11 +111,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
                .length         = SZ_4K,
                .type           = MT_DEVICE,
        }, {
-               .virtual        = (unsigned long)S3C_VA_UART,
-               .pfn            = __phys_to_pfn(S3C_PA_UART),
-               .length         = SZ_512K,
-               .type           = MT_DEVICE,
-       }, {
                .virtual        = (unsigned long)S5P_VA_SROMC,
                .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
                .length         = SZ_4K,
@@ -105,16 +120,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
                .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_GIC_CPU,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
-               .length         = SZ_64K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_GIC_DIST,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
-               .length         = SZ_64K,
-               .type           = MT_DEVICE,
        },
 };
 
@@ -136,7 +141,7 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
        },
 };
 
-static void exynos4_idle(void)
+static void exynos_idle(void)
 {
        if (!need_resched())
                cpu_do_idle();
@@ -150,12 +155,13 @@ static void exynos4_sw_reset(void)
 }
 
 /*
- * exynos4_map_io
+ * exynos_map_io
  *
  * register the standard cpu IO areas
  */
 void __init exynos4_map_io(void)
 {
+       iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
        iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 
        if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
@@ -182,6 +188,7 @@ void __init exynos4_map_io(void)
        s3c_i2c2_setname("s3c2440-i2c");
 
        s5p_fb_setname(0, "exynos4-fb");
+       s5p_hdmi_setname("exynos4-hdmi");
 }
 
 void __init exynos4_init_clocks(int xtal)
@@ -248,7 +255,6 @@ static int __init exynos4_core_init(void)
 {
        return sysdev_class_register(&exynos4_sysclass);
 }
-
 core_initcall(exynos4_core_init);
 
 #ifdef CONFIG_CACHE_L2X0
@@ -277,15 +283,16 @@ static int __init exynos4_l2x0_cache_init(void)
 early_initcall(exynos4_l2x0_cache_init);
 #endif
 
-int __init exynos4_init(void)
+int __init exynos_init(void)
 {
-       printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
+       printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 
        /* set idle function */
-       pm_idle = exynos4_idle;
+       pm_idle = exynos_idle;
 
        /* set sw_reset function */
-       s5p_reset_hook = exynos4_sw_reset;
+       if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
+               s5p_reset_hook = exynos4_sw_reset;
 
        return sysdev_register(&exynos4_sysdev);
 }
similarity index 98%
rename from arch/arm/mach-exynos4/dma.c
rename to arch/arm/mach-exynos/dma.c
index d57d662..9667c61 100644 (file)
@@ -243,6 +243,7 @@ struct amba_device exynos4_device_pdma1 = {
 static int __init exynos4_dma_init(void)
 {
        amba_device_register(&exynos4_device_pdma0, &iomem_resource);
+       amba_device_register(&exynos4_device_pdma1, &iomem_resource);
 
        return 0;
 }
similarity index 97%
rename from arch/arm/mach-exynos4/include/mach/irqs.h
rename to arch/arm/mach-exynos/include/mach/irqs.h
index 2d3f6bc..dfd4b7e 100644 (file)
 #define IRQ_2D                 IRQ_SPI(89)
 #define IRQ_PCIE               IRQ_SPI(90)
 
+#define IRQ_MIXER              IRQ_SPI(91)
+#define IRQ_HDMI               IRQ_SPI(92)
+#define IRQ_IIC_HDMIPHY                IRQ_SPI(93)
 #define IRQ_MFC                        IRQ_SPI(94)
+#define IRQ_SDO                        IRQ_SPI(95)
 
 #define IRQ_AUDIO_SS           IRQ_SPI(96)
 #define IRQ_I2S0               IRQ_SPI(97)
similarity index 87%
rename from arch/arm/mach-exynos4/include/mach/map.h
rename to arch/arm/mach-exynos/include/mach/map.h
index 9f97eb8..058541d 100644 (file)
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-exynos4/include/mach/map.h
+/* linux/arch/arm/mach-exynos/include/mach/map.h
  *
  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *             http://www.samsung.com/
 
 #define EXYNOS4_PA_UART                        0x13800000
 
+#define EXYNOS4_PA_VP                  0x12C00000
+#define EXYNOS4_PA_MIXER               0x12C10000
+#define EXYNOS4_PA_SDO                 0x12C20000
+#define EXYNOS4_PA_HDMI                        0x12D00000
+#define EXYNOS4_PA_IIC_HDMIPHY         0x138E0000
+
 #define EXYNOS4_PA_IIC(x)              (0x13860000 + ((x) * 0x10000))
 
 #define EXYNOS4_PA_ADC                 0x13910000
 #define S3C_PA_IIC5                    EXYNOS4_PA_IIC(5)
 #define S3C_PA_IIC6                    EXYNOS4_PA_IIC(6)
 #define S3C_PA_IIC7                    EXYNOS4_PA_IIC(7)
-#define SAMSUNG_PA_ADC                 EXYNOS4_PA_ADC
-#define SAMSUNG_PA_ADC1                        EXYNOS4_PA_ADC1
 #define S3C_PA_RTC                     EXYNOS4_PA_RTC
 #define S3C_PA_WDT                     EXYNOS4_PA_WATCHDOG
+#define S3C_PA_UART                    EXYNOS4_PA_UART
 
 #define S5P_PA_CHIPID                  EXYNOS4_PA_CHIPID
+#define S5P_PA_EHCI                    EXYNOS4_PA_EHCI
 #define S5P_PA_FIMC0                   EXYNOS4_PA_FIMC0
 #define S5P_PA_FIMC1                   EXYNOS4_PA_FIMC1
 #define S5P_PA_FIMC2                   EXYNOS4_PA_FIMC2
 #define S5P_PA_FIMC3                   EXYNOS4_PA_FIMC3
+#define S5P_PA_FIMD0                   EXYNOS4_PA_FIMD0
+#define S5P_PA_HDMI                    EXYNOS4_PA_HDMI
+#define S5P_PA_IIC_HDMIPHY             EXYNOS4_PA_IIC_HDMIPHY
+#define S5P_PA_MFC                     EXYNOS4_PA_MFC
 #define S5P_PA_MIPI_CSIS0              EXYNOS4_PA_MIPI_CSIS0
 #define S5P_PA_MIPI_CSIS1              EXYNOS4_PA_MIPI_CSIS1
-#define S5P_PA_FIMD0                   EXYNOS4_PA_FIMD0
+#define S5P_PA_MIXER                   EXYNOS4_PA_MIXER
 #define S5P_PA_ONENAND                 EXYNOS4_PA_ONENAND
 #define S5P_PA_ONENAND_DMA             EXYNOS4_PA_ONENAND_DMA
+#define S5P_PA_SDO                     EXYNOS4_PA_SDO
 #define S5P_PA_SDRAM                   EXYNOS4_PA_SDRAM
 #define S5P_PA_SROMC                   EXYNOS4_PA_SROMC
-#define S5P_PA_MFC                     EXYNOS4_PA_MFC
 #define S5P_PA_SYSCON                  EXYNOS4_PA_SYSCON
 #define S5P_PA_TIMER                   EXYNOS4_PA_TIMER
-#define S5P_PA_EHCI                    EXYNOS4_PA_EHCI
+#define S5P_PA_VP                      EXYNOS4_PA_VP
 
+#define SAMSUNG_PA_ADC                 EXYNOS4_PA_ADC
+#define SAMSUNG_PA_ADC1                        EXYNOS4_PA_ADC1
 #define SAMSUNG_PA_KEYPAD              EXYNOS4_PA_KEYPAD
 
-/* UART */
+#define EXYNOS_PA_COMBINER             EXYNOS4_PA_COMBINER
+#define EXYNOS_PA_GIC_CPU              EXYNOS4_PA_GIC_CPU
+#define EXYNOS_PA_GIC_DIST             EXYNOS4_PA_GIC_DIST
+#define EXYNOS_PA_PMU                  EXYNOS4_PA_PMU
+#define EXYNOS_PA_SYSTIMER             EXYNOS4_PA_SYSTIMER
 
-#define S3C_PA_UART                    EXYNOS4_PA_UART
+/* Compatibility UART */
+
+#define S3C_VA_UARTx(x)                        (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
 #define S5P_PA_UART(x)                 (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
 #define S5P_PA_UART0                   S5P_PA_UART(0)
similarity index 89%
rename from arch/arm/mach-exynos4/include/mach/pm-core.h
rename to arch/arm/mach-exynos/include/mach/pm-core.h
index 1df3b81..9d8da51 100644 (file)
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
+
+#ifndef __ASM_ARCH_PM_CORE_H
+#define __ASM_ARCH_PM_CORE_H __FILE__
+
 #include <mach/regs-pmu.h>
 
 static inline void s3c_pm_debug_init_uart(void)
@@ -53,7 +57,9 @@ static inline void s3c_pm_restored_gpios(void)
        /* nothing here yet */
 }
 
-static inline void s3c_pm_saved_gpios(void)
+static inline void samsung_pm_saved_gpios(void)
 {
        /* nothing here yet */
 }
+
+#endif /* __ASM_ARCH_PM_CORE_H */
similarity index 84%
rename from arch/arm/mach-exynos4/include/mach/pmu.h
rename to arch/arm/mach-exynos/include/mach/pmu.h
index a952904..632dd56 100644 (file)
@@ -13,6 +13,8 @@
 #ifndef __ASM_ARCH_PMU_H
 #define __ASM_ARCH_PMU_H __FILE__
 
+#define PMU_TABLE_END  NULL
+
 enum sys_powerdown {
        SYS_AFTR,
        SYS_LPA,
@@ -20,6 +22,11 @@ enum sys_powerdown {
        NUM_SYS_POWERDOWN,
 };
 
+struct exynos4_pmu_conf {
+       void __iomem *reg;
+       unsigned int val[NUM_SYS_POWERDOWN];
+};
+
 extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
 
 #endif /* __ASM_ARCH_PMU_H */
similarity index 69%
rename from arch/arm/mach-exynos4/include/mach/regs-pmu.h
rename to arch/arm/mach-exynos/include/mach/regs-pmu.h
index cdf9b47..4fff8e9 100644 (file)
 
 #define S5P_USE_STANDBY_WFI0                   (1 << 16)
 #define S5P_USE_STANDBY_WFI1                   (1 << 17)
+#define S5P_USE_STANDBYWFI_ISP_ARM             (1 << 18)
 #define S5P_USE_STANDBY_WFE0                   (1 << 24)
 #define S5P_USE_STANDBY_WFE1                   (1 << 25)
-#define S5P_USE_MASK                           ((0x3 << 16) | (0x3 << 24))
+#define S5P_USE_STANDBYWFE_ISP_ARM             (1 << 26)
 
 #define S5P_SWRESET                            S5P_PMUREG(0x0400)
 
 #define S5P_EINT_WAKEUP_MASK                   S5P_PMUREG(0x0604)
 #define S5P_WAKEUP_MASK                                S5P_PMUREG(0x0608)
 
-#define S5P_USBHOST_PHY_CONTROL                        S5P_PMUREG(0x0708)
-#define S5P_USBHOST_PHY_ENABLE                 (1 << 0)
+#define S5P_HDMI_PHY_CONTROL                   S5P_PMUREG(0x0700)
+#define S5P_HDMI_PHY_ENABLE                    (1 << 0)
+
+#define S5P_DAC_PHY_CONTROL                    S5P_PMUREG(0x070C)
+#define S5P_DAC_PHY_ENABLE                     (1 << 0)
 
 #define S5P_MIPI_DPHY_CONTROL(n)               S5P_PMUREG(0x0710 + (n) * 4)
 #define S5P_MIPI_DPHY_ENABLE                   (1 << 0)
 #define S5P_MIPI_DPHY_SRESETN                  (1 << 1)
 #define S5P_MIPI_DPHY_MRESETN                  (1 << 2)
 
-#define S5P_PMU_SATA_PHY_CONTROL               S5P_PMUREG(0x0720)
 #define S5P_INFORM0                            S5P_PMUREG(0x0800)
 #define S5P_INFORM1                            S5P_PMUREG(0x0804)
 #define S5P_INFORM2                            S5P_PMUREG(0x0808)
@@ -76,7 +79,6 @@
 #define S5P_CMU_CLKSTOP_MFC_LOWPWR             S5P_PMUREG(0x1148)
 #define S5P_CMU_CLKSTOP_G3D_LOWPWR             S5P_PMUREG(0x114C)
 #define S5P_CMU_CLKSTOP_LCD0_LOWPWR            S5P_PMUREG(0x1150)
-#define S5P_CMU_CLKSTOP_LCD1_LOWPWR            S5P_PMUREG(0x1154)
 #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR          S5P_PMUREG(0x1158)
 #define S5P_CMU_CLKSTOP_GPS_LOWPWR             S5P_PMUREG(0x115C)
 #define S5P_CMU_RESET_CAM_LOWPWR               S5P_PMUREG(0x1160)
@@ -84,7 +86,6 @@
 #define S5P_CMU_RESET_MFC_LOWPWR               S5P_PMUREG(0x1168)
 #define S5P_CMU_RESET_G3D_LOWPWR               S5P_PMUREG(0x116C)
 #define S5P_CMU_RESET_LCD0_LOWPWR              S5P_PMUREG(0x1170)
-#define S5P_CMU_RESET_LCD1_LOWPWR              S5P_PMUREG(0x1174)
 #define S5P_CMU_RESET_MAUDIO_LOWPWR            S5P_PMUREG(0x1178)
 #define S5P_CMU_RESET_GPS_LOWPWR               S5P_PMUREG(0x117C)
 #define S5P_TOP_BUS_LOWPWR                     S5P_PMUREG(0x1180)
 #define S5P_TOP_PWR_LOWPWR                     S5P_PMUREG(0x1188)
 #define S5P_LOGIC_RESET_LOWPWR                 S5P_PMUREG(0x11A0)
 #define S5P_ONENAND_MEM_LOWPWR                 S5P_PMUREG(0x11C0)
-#define S5P_MODIMIF_MEM_LOWPWR                 S5P_PMUREG(0x11C4)
 #define S5P_G2D_ACP_MEM_LOWPWR                 S5P_PMUREG(0x11C8)
 #define S5P_USBOTG_MEM_LOWPWR                  S5P_PMUREG(0x11CC)
 #define S5P_HSMMC_MEM_LOWPWR                   S5P_PMUREG(0x11D0)
 #define S5P_CSSYS_MEM_LOWPWR                   S5P_PMUREG(0x11D4)
 #define S5P_SECSS_MEM_LOWPWR                   S5P_PMUREG(0x11D8)
-#define S5P_PCIE_MEM_LOWPWR                    S5P_PMUREG(0x11E0)
-#define S5P_SATA_MEM_LOWPWR                    S5P_PMUREG(0x11E4)
 #define S5P_PAD_RETENTION_DRAM_LOWPWR          S5P_PMUREG(0x1200)
 #define S5P_PAD_RETENTION_MAUDIO_LOWPWR                S5P_PMUREG(0x1204)
 #define S5P_PAD_RETENTION_GPIO_LOWPWR          S5P_PMUREG(0x1220)
 #define S5P_MFC_LOWPWR                         S5P_PMUREG(0x1388)
 #define S5P_G3D_LOWPWR                         S5P_PMUREG(0x138C)
 #define S5P_LCD0_LOWPWR                                S5P_PMUREG(0x1390)
-#define S5P_LCD1_LOWPWR                                S5P_PMUREG(0x1394)
 #define S5P_MAUDIO_LOWPWR                      S5P_PMUREG(0x1398)
 #define S5P_GPS_LOWPWR                         S5P_PMUREG(0x139C)
 #define S5P_GPS_ALIVE_LOWPWR                   S5P_PMUREG(0x13A0)
 #define S5P_PMU_MFC_CONF                       S5P_PMUREG(0x3C40)
 #define S5P_PMU_G3D_CONF                       S5P_PMUREG(0x3C60)
 #define S5P_PMU_LCD0_CONF                      S5P_PMUREG(0x3C80)
-#define S5P_PMU_LCD1_CONF                      S5P_PMUREG(0x3CA0)
 #define S5P_PMU_GPS_CONF                       S5P_PMUREG(0x3CE0)
 
 #define S5P_PMU_SATA_PHY_CONTROL_EN            0x1
 
 #define S5P_CHECK_SLEEP                                0x00000BAD
 
+/* Only for EXYNOS4210 */
+#define S5P_USBHOST_PHY_CONTROL                S5P_PMUREG(0x0708)
+#define S5P_USBHOST_PHY_ENABLE         (1 << 0)
+
+#define S5P_PMU_SATA_PHY_CONTROL       S5P_PMUREG(0x0720)
+
+#define S5P_CMU_CLKSTOP_LCD1_LOWPWR    S5P_PMUREG(0x1154)
+#define S5P_CMU_RESET_LCD1_LOWPWR      S5P_PMUREG(0x1174)
+#define S5P_MODIMIF_MEM_LOWPWR         S5P_PMUREG(0x11C4)
+#define S5P_PCIE_MEM_LOWPWR            S5P_PMUREG(0x11E0)
+#define S5P_SATA_MEM_LOWPWR            S5P_PMUREG(0x11E4)
+#define S5P_LCD1_LOWPWR                        S5P_PMUREG(0x1394)
+
+#define S5P_PMU_LCD1_CONF              S5P_PMUREG(0x3CA0)
+
+/* Only for EXYNOS4212 */
+#define S5P_ISP_ARM_LOWPWR                     S5P_PMUREG(0x1050)
+#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR       S5P_PMUREG(0x1054)
+#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR     S5P_PMUREG(0x1058)
+#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR                S5P_PMUREG(0x1110)
+#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR                S5P_PMUREG(0x1114)
+#define S5P_CMU_RESET_COREBLK_LOWPWR           S5P_PMUREG(0x111C)
+#define S5P_MPLLUSER_SYSCLK_LOWPWR             S5P_PMUREG(0x1130)
+#define S5P_CMU_CLKSTOP_ISP_LOWPWR             S5P_PMUREG(0x1154)
+#define S5P_CMU_RESET_ISP_LOWPWR               S5P_PMUREG(0x1174)
+#define S5P_TOP_BUS_COREBLK_LOWPWR             S5P_PMUREG(0x1190)
+#define S5P_TOP_RETENTION_COREBLK_LOWPWR       S5P_PMUREG(0x1194)
+#define S5P_TOP_PWR_COREBLK_LOWPWR             S5P_PMUREG(0x1198)
+#define S5P_OSCCLK_GATE_LOWPWR                 S5P_PMUREG(0x11A4)
+#define S5P_LOGIC_RESET_COREBLK_LOWPWR         S5P_PMUREG(0x11B0)
+#define S5P_OSCCLK_GATE_COREBLK_LOWPWR         S5P_PMUREG(0x11B4)
+#define S5P_HSI_MEM_LOWPWR                     S5P_PMUREG(0x11C4)
+#define S5P_ROTATOR_MEM_LOWPWR                 S5P_PMUREG(0x11DC)
+#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR  S5P_PMUREG(0x123C)
+#define S5P_PAD_ISOLATION_COREBLK_LOWPWR       S5P_PMUREG(0x1250)
+#define S5P_GPIO_MODE_COREBLK_LOWPWR           S5P_PMUREG(0x1320)
+#define S5P_TOP_ASB_RESET_LOWPWR               S5P_PMUREG(0x1344)
+#define S5P_TOP_ASB_ISOLATION_LOWPWR           S5P_PMUREG(0x1348)
+#define S5P_ISP_LOWPWR                         S5P_PMUREG(0x1394)
+#define S5P_DRAM_FREQ_DOWN_LOWPWR              S5P_PMUREG(0x13B0)
+#define S5P_DDRPHY_DLLOFF_LOWPWR               S5P_PMUREG(0x13B4)
+#define S5P_CMU_SYSCLK_ISP_LOWPWR              S5P_PMUREG(0x13B8)
+#define S5P_CMU_SYSCLK_GPS_LOWPWR              S5P_PMUREG(0x13BC)
+#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR          S5P_PMUREG(0x13C0)
+
+#define S5P_ARM_L2_0_OPTION                    S5P_PMUREG(0x2608)
+#define S5P_ARM_L2_1_OPTION                    S5P_PMUREG(0x2628)
+#define S5P_ONENAND_MEM_OPTION                 S5P_PMUREG(0x2E08)
+#define S5P_HSI_MEM_OPTION                     S5P_PMUREG(0x2E28)
+#define S5P_G2D_ACP_MEM_OPTION                 S5P_PMUREG(0x2E48)
+#define S5P_USBOTG_MEM_OPTION                  S5P_PMUREG(0x2E68)
+#define S5P_HSMMC_MEM_OPTION                   S5P_PMUREG(0x2E88)
+#define S5P_CSSYS_MEM_OPTION                   S5P_PMUREG(0x2EA8)
+#define S5P_SECSS_MEM_OPTION                   S5P_PMUREG(0x2EC8)
+#define S5P_ROTATOR_MEM_OPTION                 S5P_PMUREG(0x2F48)
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
similarity index 85%
rename from arch/arm/mach-exynos4/mach-nuri.c
rename to arch/arm/mach-exynos/mach-nuri.c
index 6e05368..236bbe1 100644 (file)
 #include <linux/pwm_backlight.h>
 
 #include <video/platform_lcd.h>
+#include <media/m5mols.h>
+#include <media/s5p_fimc.h>
+#include <media/v4l2-mediabus.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
 #include <plat/adc.h>
+#include <plat/regs-fb-v4.h>
 #include <plat/regs-serial.h>
 #include <plat/exynos4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
+#include <plat/fb.h>
 #include <plat/sdhci.h>
 #include <plat/ehci.h>
 #include <plat/clock.h>
@@ -43,6 +48,9 @@
 #include <plat/iic.h>
 #include <plat/mfc.h>
 #include <plat/pd.h>
+#include <plat/fimc-core.h>
+#include <plat/camport.h>
+#include <plat/mipi_csis.h>
 
 #include <mach/map.h>
 
@@ -63,6 +71,8 @@
 enum fixed_regulator_id {
        FIXED_REG_ID_MMC = 0,
        FIXED_REG_ID_MAX8903,
+       FIXED_REG_ID_CAM_A28V,
+       FIXED_REG_ID_CAM_12V,
 };
 
 static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
@@ -199,6 +209,33 @@ static struct platform_device nuri_gpio_keys = {
        },
 };
 
+/* Frame Buffer */
+static struct s3c_fb_pd_win nuri_fb_win0 = {
+       .win_mode = {
+               .left_margin    = 64,
+               .right_margin   = 16,
+               .upper_margin   = 64,
+               .lower_margin   = 1,
+               .hsync_len      = 48,
+               .vsync_len      = 3,
+               .xres           = 1280,
+               .yres           = 800,
+               .refresh        = 60,
+       },
+       .max_bpp        = 24,
+       .default_bpp    = 16,
+       .virtual_x      = 1280,
+       .virtual_y      = 800,
+};
+
+static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
+       .win[0]         = &nuri_fb_win0,
+       .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
+                         VIDCON0_CLKSEL_LCD,
+       .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+       .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
+};
+
 static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
 {
        int gpio = EXYNOS4_GPE1(5);
@@ -1037,13 +1074,6 @@ static struct platform_device nuri_max8903_device = {
        },
 };
 
-static struct device *nuri_cm_devices[] = {
-       &s3c_device_i2c5.dev,
-       &s3c_device_adc.dev,
-       NULL, /* Reserved for UART */
-       NULL,
-};
-
 static void __init nuri_power_init(void)
 {
        int gpio;
@@ -1088,10 +1118,141 @@ static void __init nuri_ehci_init(void)
        s5p_ehci_set_platdata(pdata);
 }
 
+/* CAMERA */
+static struct regulator_consumer_supply cam_vdda_supply[] = {
+       REGULATOR_SUPPLY("a_sensor", "0-001f"),
+};
+
+static struct regulator_init_data cam_vdda_reg_init_data = {
+       .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+       .num_consumer_supplies = ARRAY_SIZE(cam_vdda_supply),
+       .consumer_supplies = cam_vdda_supply,
+};
+
+static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = {
+       .supply_name    = "CAM_IO_EN",
+       .microvolts     = 2800000,
+       .gpio           = EXYNOS4_GPE2(1), /* CAM_IO_EN */
+       .enable_high    = 1,
+       .init_data      = &cam_vdda_reg_init_data,
+};
+
+static struct platform_device cam_vdda_fixed_rdev = {
+       .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_A28V,
+       .dev = { .platform_data = &cam_vdda_fixed_voltage_cfg },
+};
+
+static struct regulator_consumer_supply camera_8m_12v_supply =
+       REGULATOR_SUPPLY("dig_12", "0-001f");
+
+static struct regulator_init_data cam_8m_12v_reg_init_data = {
+       .num_consumer_supplies  = 1,
+       .consumer_supplies      = &camera_8m_12v_supply,
+       .constraints = {
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS
+       },
+};
+
+static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = {
+       .supply_name    = "8M_1.2V",
+       .microvolts     = 1200000,
+       .gpio           = EXYNOS4_GPE2(5), /* 8M_1.2V_EN */
+       .enable_high    = 1,
+       .init_data      = &cam_8m_12v_reg_init_data,
+};
+
+static struct platform_device cam_8m_12v_fixed_rdev = {
+       .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_12V,
+       .dev = { .platform_data = &cam_8m_12v_fixed_voltage_cfg },
+};
+
+static struct s5p_platform_mipi_csis mipi_csis_platdata = {
+       .clk_rate       = 166000000UL,
+       .lanes          = 2,
+       .alignment      = 32,
+       .hs_settle      = 12,
+       .phy_enable     = s5p_csis_phy_enable,
+};
+
+#define GPIO_CAM_MEGA_RST      EXYNOS4_GPY3(7) /* ISP_RESET */
+#define GPIO_CAM_8M_ISP_INT    EXYNOS4_GPL2(5)
+
+static struct m5mols_platform_data m5mols_platdata = {
+       .gpio_reset = GPIO_CAM_MEGA_RST,
+};
+
+static struct i2c_board_info m5mols_board_info = {
+       I2C_BOARD_INFO("M5MOLS", 0x1F),
+       .platform_data  = &m5mols_platdata,
+};
+
+static struct s5p_fimc_isp_info nuri_camera_sensors[] = {
+       {
+               .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
+                                 V4L2_MBUS_VSYNC_ACTIVE_LOW,
+               .bus_type       = FIMC_MIPI_CSI2,
+               .board_info     = &m5mols_board_info,
+               .clk_frequency  = 24000000UL,
+               .csi_data_align = 32,
+       },
+};
+
+static struct s5p_platform_fimc fimc_md_platdata = {
+       .isp_info       = nuri_camera_sensors,
+       .num_clients    = ARRAY_SIZE(nuri_camera_sensors),
+};
+
+static struct gpio nuri_camera_gpios[] = {
+       { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,           "8M_ISP_INT"  },
+       { GPIO_CAM_MEGA_RST,    GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
+};
+
+static void nuri_camera_init(void)
+{
+       s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
+                        &s5p_device_mipi_csis0);
+       s3c_set_platdata(&fimc_md_platdata,  sizeof(fimc_md_platdata),
+                        &s5p_device_fimc_md);
+
+       if (gpio_request_array(nuri_camera_gpios,
+                              ARRAY_SIZE(nuri_camera_gpios))) {
+               pr_err("%s: GPIO request failed\n", __func__);
+               return;
+       }
+
+       m5mols_board_info.irq = s5p_register_gpio_interrupt(GPIO_CAM_8M_ISP_INT);
+       if (!IS_ERR_VALUE(m5mols_board_info.irq))
+               s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xF));
+       else
+               pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__);
+
+       /* Free GPIOs controlled directly by the sensor drivers. */
+       gpio_free(GPIO_CAM_MEGA_RST);
+
+       if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) {
+               pr_err("%s: Camera port A setup failed\n", __func__);
+               return;
+       }
+       /* Increase drive strength of the sensor clock output */
+       s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4);
+}
+
+static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = {
+       .frequency      = 400000U,
+       .sda_delay      = 200,
+};
+
 static struct platform_device *nuri_devices[] __initdata = {
        /* Samsung Platform Devices */
        &s3c_device_i2c5, /* PMIC should initialize first */
+       &s3c_device_i2c0,
        &emmc_fixed_voltage,
+       &s5p_device_mipi_csis0,
+       &s5p_device_fimc0,
+       &s5p_device_fimc1,
+       &s5p_device_fimc2,
+       &s5p_device_fimc3,
+       &s5p_device_fimd0,
        &s3c_device_hsmmc0,
        &s3c_device_hsmmc2,
        &s3c_device_hsmmc3,
@@ -1106,6 +1267,9 @@ static struct platform_device *nuri_devices[] __initdata = {
        &s5p_device_mfc_l,
        &s5p_device_mfc_r,
        &exynos4_device_pd[PD_MFC],
+       &exynos4_device_pd[PD_LCD0],
+       &exynos4_device_pd[PD_CAM],
+       &s5p_device_fimc_md,
 
        /* NURI Devices */
        &nuri_gpio_keys,
@@ -1113,6 +1277,8 @@ static struct platform_device *nuri_devices[] __initdata = {
        &nuri_backlight_device,
        &max8903_fixed_reg_dev,
        &nuri_max8903_device,
+       &cam_vdda_fixed_rdev,
+       &cam_8m_12v_fixed_rdev,
 };
 
 static void __init nuri_map_io(void)
@@ -1133,6 +1299,7 @@ static void __init nuri_machine_init(void)
        nuri_tsp_init();
        nuri_power_init();
 
+       s3c_i2c0_set_platdata(&nuri_i2c0_platdata);
        i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
        s3c_i2c3_set_platdata(&i2c3_data);
        i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
@@ -1142,12 +1309,23 @@ static void __init nuri_machine_init(void)
        i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
        i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
 
+       s5p_fimd0_set_platdata(&nuri_fb_pdata);
+
+       nuri_camera_init();
+
        nuri_ehci_init();
        clk_xusbxti.rate = 24000000;
 
        /* Last */
        platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
        s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+       s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+
+       s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+       s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+       s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+       s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+       s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
 }
 
 MACHINE_START(NURI, "NURI")
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
new file mode 100644 (file)
index 0000000..f80b563
--- /dev/null
@@ -0,0 +1,700 @@
+/* linux/arch/arm/mach-exynos4/mach-origen.c
+ *
+ * Copyright (c) 2011 Insignal Co., Ltd.
+ *             http://www.insignal.co.kr/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/serial_core.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/input.h>
+#include <linux/pwm_backlight.h>
+#include <linux/gpio_keys.h>
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+#include <linux/mfd/max8997.h>
+#include <linux/lcd.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <video/platform_lcd.h>
+
+#include <plat/regs-serial.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/exynos4.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/sdhci.h>
+#include <plat/iic.h>
+#include <plat/ehci.h>
+#include <plat/clock.h>
+#include <plat/gpio-cfg.h>
+#include <plat/backlight.h>
+#include <plat/pd.h>
+#include <plat/fb.h>
+#include <plat/mfc.h>
+
+#include <mach/map.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define ORIGEN_UCON_DEFAULT    (S3C2410_UCON_TXILEVEL |        \
+                                S3C2410_UCON_RXILEVEL |        \
+                                S3C2410_UCON_TXIRQMODE |       \
+                                S3C2410_UCON_RXIRQMODE |       \
+                                S3C2410_UCON_RXFIFO_TOI |      \
+                                S3C2443_UCON_RXERR_IRQEN)
+
+#define ORIGEN_ULCON_DEFAULT   S3C2410_LCON_CS8
+
+#define ORIGEN_UFCON_DEFAULT   (S3C2410_UFCON_FIFOMODE |       \
+                                S5PV210_UFCON_TXTRIG4 |        \
+                                S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
+       [0] = {
+               .hwport         = 0,
+               .flags          = 0,
+               .ucon           = ORIGEN_UCON_DEFAULT,
+               .ulcon          = ORIGEN_ULCON_DEFAULT,
+               .ufcon          = ORIGEN_UFCON_DEFAULT,
+       },
+       [1] = {
+               .hwport         = 1,
+               .flags          = 0,
+               .ucon           = ORIGEN_UCON_DEFAULT,
+               .ulcon          = ORIGEN_ULCON_DEFAULT,
+               .ufcon          = ORIGEN_UFCON_DEFAULT,
+       },
+       [2] = {
+               .hwport         = 2,
+               .flags          = 0,
+               .ucon           = ORIGEN_UCON_DEFAULT,
+               .ulcon          = ORIGEN_ULCON_DEFAULT,
+               .ufcon          = ORIGEN_UFCON_DEFAULT,
+       },
+       [3] = {
+               .hwport         = 3,
+               .flags          = 0,
+               .ucon           = ORIGEN_UCON_DEFAULT,
+               .ulcon          = ORIGEN_ULCON_DEFAULT,
+               .ufcon          = ORIGEN_UFCON_DEFAULT,
+       },
+};
+
+static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
+       REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
+       REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */
+       REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */
+};
+static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
+       REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
+};
+static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
+       REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
+};
+static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
+       REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
+       REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), /* HDMI */
+};
+static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
+       REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
+};
+static struct regulator_consumer_supply __initdata ldo11_consumer[] = {
+       REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */
+};
+static struct regulator_consumer_supply __initdata ldo14_consumer[] = {
+       REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
+};
+static struct regulator_consumer_supply __initdata ldo17_consumer[] = {
+       REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
+};
+static struct regulator_consumer_supply __initdata buck1_consumer[] = {
+       REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply __initdata buck2_consumer[] = {
+       REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply __initdata buck3_consumer[] = {
+       REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */
+};
+static struct regulator_consumer_supply __initdata buck7_consumer[] = {
+       REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */
+};
+
+static struct regulator_init_data __initdata max8997_ldo1_data = {
+       .constraints    = {
+               .name           = "VDD_ABB_3.3V",
+               .min_uV         = 3300000,
+               .max_uV         = 3300000,
+               .apply_uV       = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_ldo2_data = {
+       .constraints    = {
+               .name           = "VDD_ALIVE_1.1V",
+               .min_uV         = 1100000,
+               .max_uV         = 1100000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .enabled        = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_ldo3_data = {
+       .constraints    = {
+               .name           = "VMIPI_1.1V",
+               .min_uV         = 1100000,
+               .max_uV         = 1100000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(ldo3_consumer),
+       .consumer_supplies      = ldo3_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo4_data = {
+       .constraints    = {
+               .name           = "VDD_RTC_1.8V",
+               .min_uV         = 1800000,
+               .max_uV         = 1800000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_ldo6_data = {
+       .constraints    = {
+               .name           = "VMIPI_1.8V",
+               .min_uV         = 1800000,
+               .max_uV         = 1800000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(ldo6_consumer),
+       .consumer_supplies      = ldo6_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo7_data = {
+       .constraints    = {
+               .name           = "VDD_AUD_1.8V",
+               .min_uV         = 1800000,
+               .max_uV         = 1800000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(ldo7_consumer),
+       .consumer_supplies      = ldo7_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo8_data = {
+       .constraints    = {
+               .name           = "VADC_3.3V",
+               .min_uV         = 3300000,
+               .max_uV         = 3300000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(ldo8_consumer),
+       .consumer_supplies      = ldo8_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo9_data = {
+       .constraints    = {
+               .name           = "DVDD_SWB_2.8V",
+               .min_uV         = 2800000,
+               .max_uV         = 2800000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(ldo9_consumer),
+       .consumer_supplies      = ldo9_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo10_data = {
+       .constraints    = {
+               .name           = "VDD_PLL_1.1V",
+               .min_uV         = 1100000,
+               .max_uV         = 1100000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_ldo11_data = {
+       .constraints    = {
+               .name           = "VDD_AUD_3V",
+               .min_uV         = 3000000,
+               .max_uV         = 3000000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(ldo11_consumer),
+       .consumer_supplies      = ldo11_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo14_data = {
+       .constraints    = {
+               .name           = "AVDD18_SWB_1.8V",
+               .min_uV         = 1800000,
+               .max_uV         = 1800000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(ldo14_consumer),
+       .consumer_supplies      = ldo14_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo17_data = {
+       .constraints    = {
+               .name           = "VDD_SWB_3.3V",
+               .min_uV         = 3300000,
+               .max_uV         = 3300000,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(ldo17_consumer),
+       .consumer_supplies      = ldo17_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo21_data = {
+       .constraints    = {
+               .name           = "VDD_MIF_1.2V",
+               .min_uV         = 1200000,
+               .max_uV         = 1200000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_buck1_data = {
+       .constraints    = {
+               .name           = "VDD_ARM_1.2V",
+               .min_uV         = 950000,
+               .max_uV         = 1350000,
+               .always_on      = 1,
+               .boot_on        = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(buck1_consumer),
+       .consumer_supplies      = buck1_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_buck2_data = {
+       .constraints    = {
+               .name           = "VDD_INT_1.1V",
+               .min_uV         = 900000,
+               .max_uV         = 1100000,
+               .always_on      = 1,
+               .boot_on        = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(buck2_consumer),
+       .consumer_supplies      = buck2_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_buck3_data = {
+       .constraints    = {
+               .name           = "VDD_G3D_1.1V",
+               .min_uV         = 900000,
+               .max_uV         = 1100000,
+               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                       REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(buck3_consumer),
+       .consumer_supplies      = buck3_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_buck5_data = {
+       .constraints    = {
+               .name           = "VDDQ_M1M2_1.2V",
+               .min_uV         = 1200000,
+               .max_uV         = 1200000,
+               .apply_uV       = 1,
+               .always_on      = 1,
+               .state_mem      = {
+                       .disabled       = 1,
+               },
+       },
+};
+
+static struct regulator_init_data __initdata max8997_buck7_data = {
+       .constraints    = {
+               .name           = "VDD_LCD_3.3V",
+               .min_uV         = 3300000,
+               .max_uV         = 3300000,
+               .boot_on        = 1,
+               .apply_uV       = 1,
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+               .state_mem      = {
+                       .disabled       = 1
+               },
+       },
+       .num_consumer_supplies  = ARRAY_SIZE(buck7_consumer),
+       .consumer_supplies      = buck7_consumer,
+};
+
+static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
+       { MAX8997_LDO1,         &max8997_ldo1_data },
+       { MAX8997_LDO2,         &max8997_ldo2_data },
+       { MAX8997_LDO3,         &max8997_ldo3_data },
+       { MAX8997_LDO4,         &max8997_ldo4_data },
+       { MAX8997_LDO6,         &max8997_ldo6_data },
+       { MAX8997_LDO7,         &max8997_ldo7_data },
+       { MAX8997_LDO8,         &max8997_ldo8_data },
+       { MAX8997_LDO9,         &max8997_ldo9_data },
+       { MAX8997_LDO10,        &max8997_ldo10_data },
+       { MAX8997_LDO11,        &max8997_ldo11_data },
+       { MAX8997_LDO14,        &max8997_ldo14_data },
+       { MAX8997_LDO17,        &max8997_ldo17_data },
+       { MAX8997_LDO21,        &max8997_ldo21_data },
+       { MAX8997_BUCK1,        &max8997_buck1_data },
+       { MAX8997_BUCK2,        &max8997_buck2_data },
+       { MAX8997_BUCK3,        &max8997_buck3_data },
+       { MAX8997_BUCK5,        &max8997_buck5_data },
+       { MAX8997_BUCK7,        &max8997_buck7_data },
+};
+
+struct max8997_platform_data __initdata origen_max8997_pdata = {
+       .num_regulators = ARRAY_SIZE(origen_max8997_regulators),
+       .regulators     = origen_max8997_regulators,
+
+       .wakeup = true,
+       .buck1_gpiodvs  = false,
+       .buck2_gpiodvs  = false,
+       .buck5_gpiodvs  = false,
+       .irq_base       = IRQ_GPIO_END + 1,
+
+       .ignore_gpiodvs_side_effect = true,
+       .buck125_default_idx = 0x0,
+
+       .buck125_gpios[0]       = EXYNOS4_GPX0(0),
+       .buck125_gpios[1]       = EXYNOS4_GPX0(1),
+       .buck125_gpios[2]       = EXYNOS4_GPX0(2),
+
+       .buck1_voltage[0]       = 1350000,
+       .buck1_voltage[1]       = 1300000,
+       .buck1_voltage[2]       = 1250000,
+       .buck1_voltage[3]       = 1200000,
+       .buck1_voltage[4]       = 1150000,
+       .buck1_voltage[5]       = 1100000,
+       .buck1_voltage[6]       = 1000000,
+       .buck1_voltage[7]       = 950000,
+
+       .buck2_voltage[0]       = 1100000,
+       .buck2_voltage[1]       = 1100000,
+       .buck2_voltage[2]       = 1100000,
+       .buck2_voltage[3]       = 1100000,
+       .buck2_voltage[4]       = 1000000,
+       .buck2_voltage[5]       = 1000000,
+       .buck2_voltage[6]       = 1000000,
+       .buck2_voltage[7]       = 1000000,
+
+       .buck5_voltage[0]       = 1200000,
+       .buck5_voltage[1]       = 1200000,
+       .buck5_voltage[2]       = 1200000,
+       .buck5_voltage[3]       = 1200000,
+       .buck5_voltage[4]       = 1200000,
+       .buck5_voltage[5]       = 1200000,
+       .buck5_voltage[6]       = 1200000,
+       .buck5_voltage[7]       = 1200000,
+};
+
+/* I2C0 */
+static struct i2c_board_info i2c0_devs[] __initdata = {
+       {
+               I2C_BOARD_INFO("max8997", (0xCC >> 1)),
+               .platform_data  = &origen_max8997_pdata,
+               .irq            = IRQ_EINT(4),
+       },
+};
+
+static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
+       .cd_type                = S3C_SDHCI_CD_INTERNAL,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
+       .cd_type                = S3C_SDHCI_CD_INTERNAL,
+       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+/* USB EHCI */
+static struct s5p_ehci_platdata origen_ehci_pdata;
+
+static void __init origen_ehci_init(void)
+{
+       struct s5p_ehci_platdata *pdata = &origen_ehci_pdata;
+
+       s5p_ehci_set_platdata(pdata);
+}
+
+static struct gpio_keys_button origen_gpio_keys_table[] = {
+       {
+               .code                   = KEY_MENU,
+               .gpio                   = EXYNOS4_GPX1(5),
+               .desc                   = "gpio-keys: KEY_MENU",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .wakeup                 = 1,
+               .debounce_interval      = 1,
+       }, {
+               .code                   = KEY_HOME,
+               .gpio                   = EXYNOS4_GPX1(6),
+               .desc                   = "gpio-keys: KEY_HOME",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .wakeup                 = 1,
+               .debounce_interval      = 1,
+       }, {
+               .code                   = KEY_BACK,
+               .gpio                   = EXYNOS4_GPX1(7),
+               .desc                   = "gpio-keys: KEY_BACK",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .wakeup                 = 1,
+               .debounce_interval      = 1,
+       }, {
+               .code                   = KEY_UP,
+               .gpio                   = EXYNOS4_GPX2(0),
+               .desc                   = "gpio-keys: KEY_UP",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .wakeup                 = 1,
+               .debounce_interval      = 1,
+       }, {
+               .code                   = KEY_DOWN,
+               .gpio                   = EXYNOS4_GPX2(1),
+               .desc                   = "gpio-keys: KEY_DOWN",
+               .type                   = EV_KEY,
+               .active_low             = 1,
+               .wakeup                 = 1,
+               .debounce_interval      = 1,
+       },
+};
+
+static struct gpio_keys_platform_data origen_gpio_keys_data = {
+       .buttons        = origen_gpio_keys_table,
+       .nbuttons       = ARRAY_SIZE(origen_gpio_keys_table),
+};
+
+static struct platform_device origen_device_gpiokeys = {
+       .name           = "gpio-keys",
+       .dev            = {
+               .platform_data  = &origen_gpio_keys_data,
+       },
+};
+
+static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
+{
+       int ret;
+
+       if (power)
+               ret = gpio_request_one(EXYNOS4_GPE3(4),
+                                       GPIOF_OUT_INIT_HIGH, "GPE3_4");
+       else
+               ret = gpio_request_one(EXYNOS4_GPE3(4),
+                                       GPIOF_OUT_INIT_LOW, "GPE3_4");
+
+       gpio_free(EXYNOS4_GPE3(4));
+
+       if (ret)
+               pr_err("failed to request gpio for LCD power: %d\n", ret);
+}
+
+static struct plat_lcd_data origen_lcd_hv070wsa_data = {
+       .set_power = lcd_hv070wsa_set_power,
+};
+
+static struct platform_device origen_lcd_hv070wsa = {
+       .name                   = "platform-lcd",
+       .dev.parent             = &s5p_device_fimd0.dev,
+       .dev.platform_data      = &origen_lcd_hv070wsa_data,
+};
+
+static struct s3c_fb_pd_win origen_fb_win0 = {
+       .win_mode = {
+               .left_margin    = 64,
+               .right_margin   = 16,
+               .upper_margin   = 64,
+               .lower_margin   = 16,
+               .hsync_len      = 48,
+               .vsync_len      = 3,
+               .xres           = 1024,
+               .yres           = 600,
+       },
+       .max_bpp                = 32,
+       .default_bpp            = 24,
+};
+
+static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
+       .win[0]         = &origen_fb_win0,
+       .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+       .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+       .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
+};
+
+static struct platform_device *origen_devices[] __initdata = {
+       &s3c_device_hsmmc2,
+       &s3c_device_hsmmc0,
+       &s3c_device_i2c0,
+       &s3c_device_rtc,
+       &s3c_device_wdt,
+       &s5p_device_ehci,
+       &s5p_device_fimc0,
+       &s5p_device_fimc1,
+       &s5p_device_fimc2,
+       &s5p_device_fimc3,
+       &s5p_device_fimd0,
+       &s5p_device_hdmi,
+       &s5p_device_i2c_hdmiphy,
+       &s5p_device_mfc,
+       &s5p_device_mfc_l,
+       &s5p_device_mfc_r,
+       &s5p_device_mixer,
+       &exynos4_device_pd[PD_LCD0],
+       &exynos4_device_pd[PD_TV],
+       &exynos4_device_pd[PD_G3D],
+       &exynos4_device_pd[PD_LCD1],
+       &exynos4_device_pd[PD_CAM],
+       &exynos4_device_pd[PD_GPS],
+       &exynos4_device_pd[PD_MFC],
+       &origen_device_gpiokeys,
+       &origen_lcd_hv070wsa,
+};
+
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info origen_bl_gpio_info = {
+       .no             = EXYNOS4_GPD0(0),
+       .func           = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data origen_bl_data = {
+       .pwm_id         = 0,
+       .pwm_period_ns  = 1000,
+};
+
+static void s5p_tv_setup(void)
+{
+       /* Direct HPD to HDMI chip */
+       gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
+       s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
+       s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
+}
+
+static void __init origen_map_io(void)
+{
+       s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+       s3c24xx_init_clocks(24000000);
+       s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
+}
+
+static void __init origen_power_init(void)
+{
+       gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ");
+       s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf));
+       s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE);
+}
+
+static void __init origen_reserve(void)
+{
+       s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
+static void __init origen_machine_init(void)
+{
+       origen_power_init();
+
+       s3c_i2c0_set_platdata(NULL);
+       i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
+
+       /*
+        * Since sdhci instance 2 can contain a bootable media,
+        * sdhci instance 0 is registered after instance 2.
+        */
+       s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
+       s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
+
+       origen_ehci_init();
+       clk_xusbxti.rate = 24000000;
+
+       s5p_tv_setup();
+       s5p_i2c_hdmiphy_set_platdata(NULL);
+
+       s5p_fimd0_set_platdata(&origen_lcd_pdata);
+
+       platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
+
+       s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+
+       s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
+       s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
+
+       s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+
+       samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
+}
+
+MACHINE_START(ORIGEN, "ORIGEN")
+       /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
+       .atag_offset    = 0x100,
+       .init_irq       = exynos4_init_irq,
+       .map_io         = origen_map_io,
+       .init_machine   = origen_machine_init,
+       .timer          = &exynos4_timer,
+       .reserve        = &origen_reserve,
+MACHINE_END
similarity index 88%
rename from arch/arm/mach-exynos4/mach-smdkv310.c
rename to arch/arm/mach-exynos/mach-smdkv310.c
index 2c1a076..cec2afa 100644 (file)
@@ -37,6 +37,9 @@
 #include <plat/pd.h>
 #include <plat/gpio-cfg.h>
 #include <plat/backlight.h>
+#include <plat/mfc.h>
+#include <plat/ehci.h>
+#include <plat/clock.h>
 
 #include <mach/map.h>
 
@@ -232,17 +235,36 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
        {I2C_BOARD_INFO("wm8994", 0x1a),},
 };
 
+/* USB EHCI */
+static struct s5p_ehci_platdata smdkv310_ehci_pdata;
+
+static void __init smdkv310_ehci_init(void)
+{
+       struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
+
+       s5p_ehci_set_platdata(pdata);
+}
+
 static struct platform_device *smdkv310_devices[] __initdata = {
        &s3c_device_hsmmc0,
        &s3c_device_hsmmc1,
        &s3c_device_hsmmc2,
        &s3c_device_hsmmc3,
        &s3c_device_i2c1,
+       &s5p_device_i2c_hdmiphy,
        &s3c_device_rtc,
        &s3c_device_wdt,
+       &s5p_device_ehci,
+       &s5p_device_fimc0,
+       &s5p_device_fimc1,
+       &s5p_device_fimc2,
+       &s5p_device_fimc3,
        &exynos4_device_ac97,
        &exynos4_device_i2s0,
        &samsung_device_keypad,
+       &s5p_device_mfc,
+       &s5p_device_mfc_l,
+       &s5p_device_mfc_r,
        &exynos4_device_pd[PD_MFC],
        &exynos4_device_pd[PD_G3D],
        &exynos4_device_pd[PD_LCD0],
@@ -258,6 +280,8 @@ static struct platform_device *smdkv310_devices[] __initdata = {
        &smdkv310_lcd_lte480wv,
        &smdkv310_smsc911x,
        &exynos4_device_ahci,
+       &s5p_device_hdmi,
+       &s5p_device_mixer,
 };
 
 static void __init smdkv310_smsc911x_init(void)
@@ -294,6 +318,18 @@ static struct platform_pwm_backlight_data smdkv310_bl_data = {
        .pwm_period_ns  = 1000,
 };
 
+static void s5p_tv_setup(void)
+{
+       /* direct HPD to HDMI chip */
+       WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
+       s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
+       s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
+
+       /* setup dependencies between TV devices */
+       s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
+       s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
+}
+
 static void __init smdkv310_map_io(void)
 {
        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -301,6 +337,11 @@ static void __init smdkv310_map_io(void)
        s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
 }
 
+static void __init smdkv310_reserve(void)
+{
+       s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
 static void __init smdkv310_machine_init(void)
 {
        s3c_i2c1_set_platdata(NULL);
@@ -313,12 +354,19 @@ static void __init smdkv310_machine_init(void)
        s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
        s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
 
+       s5p_tv_setup();
+       s5p_i2c_hdmiphy_set_platdata(NULL);
+
        samsung_keypad_set_platdata(&smdkv310_keypad_data);
 
        samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
        s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
 
+       smdkv310_ehci_init();
+       clk_xusbxti.rate = 24000000;
+
        platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
+       s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
 }
 
 MACHINE_START(SMDKV310, "SMDKV310")
@@ -329,6 +377,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
        .map_io         = smdkv310_map_io,
        .init_machine   = smdkv310_machine_init,
        .timer          = &exynos4_timer,
+       .reserve        = &smdkv310_reserve,
 MACHINE_END
 
 MACHINE_START(SMDKC210, "SMDKC210")
similarity index 67%
rename from arch/arm/mach-exynos4/mach-universal_c210.c
rename to arch/arm/mach-exynos/mach-universal_c210.c
index 2aac6f7..a2a177f 100644 (file)
@@ -13,6 +13,7 @@
 #include <linux/i2c.h>
 #include <linux/gpio_keys.h>
 #include <linux/gpio.h>
+#include <linux/fb.h>
 #include <linux/mfd/max8998.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
 #include <plat/devs.h>
 #include <plat/iic.h>
 #include <plat/gpio-cfg.h>
+#include <plat/fb.h>
 #include <plat/mfc.h>
 #include <plat/sdhci.h>
 #include <plat/pd.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/fimc-core.h>
+#include <plat/camport.h>
+#include <plat/mipi_csis.h>
 
 #include <mach/map.h>
 
+#include <media/v4l2-mediabus.h>
+#include <media/s5p_fimc.h>
+#include <media/m5mols.h>
+
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |        \
@@ -110,6 +120,9 @@ static struct regulator_consumer_supply lp3974_buck1_consumer =
 static struct regulator_consumer_supply lp3974_buck2_consumer =
        REGULATOR_SUPPLY("vddg3d", NULL);
 
+static struct regulator_consumer_supply lp3974_buck3_consumer =
+       REGULATOR_SUPPLY("vdet", "s5p-sdo");
+
 static struct regulator_init_data lp3974_buck1_data = {
        .constraints    = {
                .name           = "VINT_1.1V",
@@ -153,6 +166,8 @@ static struct regulator_init_data lp3974_buck3_data = {
                        .enabled        = 1,
                },
        },
+       .num_consumer_supplies = 1,
+       .consumer_supplies = &lp3974_buck3_consumer,
 };
 
 static struct regulator_init_data lp3974_buck4_data = {
@@ -181,6 +196,12 @@ static struct regulator_init_data lp3974_ldo2_data = {
        },
 };
 
+static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
+       REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
+       REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
+       REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"),
+};
+
 static struct regulator_init_data lp3974_ldo3_data = {
        .constraints    = {
                .name           = "VUSB+MIPI_1.1V",
@@ -192,6 +213,12 @@ static struct regulator_init_data lp3974_ldo3_data = {
                        .disabled       = 1,
                },
        },
+       .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer),
+       .consumer_supplies = lp3974_ldo3_consumer,
+};
+
+static struct regulator_consumer_supply lp3974_ldo4_consumer[] = {
+       REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
 };
 
 static struct regulator_init_data lp3974_ldo4_data = {
@@ -205,6 +232,8 @@ static struct regulator_init_data lp3974_ldo4_data = {
                        .disabled       = 1,
                },
        },
+       .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer),
+       .consumer_supplies = lp3974_ldo4_consumer,
 };
 
 static struct regulator_init_data lp3974_ldo5_data = {
@@ -233,6 +262,10 @@ static struct regulator_init_data lp3974_ldo6_data = {
        },
 };
 
+static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
+       REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"),
+};
+
 static struct regulator_init_data lp3974_ldo7_data = {
        .constraints    = {
                .name           = "VLCD+VMIPI_1.8V",
@@ -244,6 +277,12 @@ static struct regulator_init_data lp3974_ldo7_data = {
                        .disabled       = 1,
                },
        },
+       .num_consumer_supplies  = ARRAY_SIZE(lp3974_ldo7_consumer),
+       .consumer_supplies      = lp3974_ldo7_consumer,
+};
+
+static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
+       REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
 };
 
 static struct regulator_init_data lp3974_ldo8_data = {
@@ -257,6 +296,8 @@ static struct regulator_init_data lp3974_ldo8_data = {
                        .disabled       = 1,
                },
        },
+       .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer),
+       .consumer_supplies = lp3974_ldo8_consumer,
 };
 
 static struct regulator_init_data lp3974_ldo9_data = {
@@ -286,6 +327,9 @@ static struct regulator_init_data lp3974_ldo10_data = {
        },
 };
 
+static struct regulator_consumer_supply lp3974_ldo11_consumer =
+       REGULATOR_SUPPLY("dig_28", "0-001f");
+
 static struct regulator_init_data lp3974_ldo11_data = {
        .constraints    = {
                .name           = "CAM_AF_3.3V",
@@ -297,6 +341,8 @@ static struct regulator_init_data lp3974_ldo11_data = {
                        .disabled       = 1,
                },
        },
+       .num_consumer_supplies  = 1,
+       .consumer_supplies      = &lp3974_ldo11_consumer,
 };
 
 static struct regulator_init_data lp3974_ldo12_data = {
@@ -325,6 +371,9 @@ static struct regulator_init_data lp3974_ldo13_data = {
        },
 };
 
+static struct regulator_consumer_supply lp3974_ldo14_consumer =
+       REGULATOR_SUPPLY("dig_18", "0-001f");
+
 static struct regulator_init_data lp3974_ldo14_data = {
        .constraints    = {
                .name           = "CAM_I_HOST_1.8V",
@@ -336,8 +385,14 @@ static struct regulator_init_data lp3974_ldo14_data = {
                        .disabled       = 1,
                },
        },
+       .num_consumer_supplies  = 1,
+       .consumer_supplies      = &lp3974_ldo14_consumer,
 };
 
+
+static struct regulator_consumer_supply lp3974_ldo15_consumer =
+       REGULATOR_SUPPLY("dig_12", "0-001f");
+
 static struct regulator_init_data lp3974_ldo15_data = {
        .constraints    = {
                .name           = "CAM_S_DIG+FM33_CORE_1.2V",
@@ -349,6 +404,12 @@ static struct regulator_init_data lp3974_ldo15_data = {
                        .disabled       = 1,
                },
        },
+       .num_consumer_supplies  = 1,
+       .consumer_supplies      = &lp3974_ldo15_consumer,
+};
+
+static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
+       REGULATOR_SUPPLY("a_sensor", "0-001f"),
 };
 
 static struct regulator_init_data lp3974_ldo16_data = {
@@ -362,6 +423,8 @@ static struct regulator_init_data lp3974_ldo16_data = {
                        .disabled       = 1,
                },
        },
+       .num_consumer_supplies  = ARRAY_SIZE(lp3974_ldo16_consumer),
+       .consumer_supplies      = lp3974_ldo16_consumer,
 };
 
 static struct regulator_init_data lp3974_ldo17_data = {
@@ -472,6 +535,43 @@ static struct max8998_platform_data universal_lp3974_pdata = {
        .wakeup                 = true,
 };
 
+
+enum fixed_regulator_id {
+       FIXED_REG_ID_MMC0,
+       FIXED_REG_ID_HDMI_5V,
+       FIXED_REG_ID_CAM_S_IF,
+       FIXED_REG_ID_CAM_I_CORE,
+       FIXED_REG_ID_CAM_VT_DIO,
+};
+
+static struct regulator_consumer_supply hdmi_fixed_consumer =
+       REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi");
+
+static struct regulator_init_data hdmi_fixed_voltage_init_data = {
+       .constraints            = {
+               .name           = "HDMI_5V",
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+       },
+       .num_consumer_supplies  = 1,
+       .consumer_supplies      = &hdmi_fixed_consumer,
+};
+
+static struct fixed_voltage_config hdmi_fixed_voltage_config = {
+       .supply_name            = "HDMI_EN1",
+       .microvolts             = 5000000,
+       .gpio                   = EXYNOS4_GPE0(1),
+       .enable_high            = true,
+       .init_data              = &hdmi_fixed_voltage_init_data,
+};
+
+static struct platform_device hdmi_fixed_voltage = {
+       .name                   = "reg-fixed-voltage",
+       .id                     = FIXED_REG_ID_HDMI_5V,
+       .dev                    = {
+               .platform_data  = &hdmi_fixed_voltage_config,
+       },
+};
+
 /* GPIO I2C 5 (PMIC) */
 static struct i2c_board_info i2c5_devs[] __initdata = {
        {
@@ -573,6 +673,11 @@ static void __init universal_touchkey_init(void)
        gpio_direction_output(gpio, 1);
 }
 
+static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
+       .frequency      = 300 * 1000,
+       .sda_delay      = 200,
+};
+
 /* GPIO KEYS */
 static struct gpio_keys_button universal_gpio_keys_tables[] = {
        {
@@ -658,7 +763,7 @@ static struct fixed_voltage_config mmc0_fixed_voltage_config = {
 
 static struct platform_device mmc0_fixed_voltage = {
        .name                   = "reg-fixed-voltage",
-       .id                     = 0,
+       .id                     = FIXED_REG_ID_MMC0,
        .dev                    = {
                .platform_data  = &mmc0_fixed_voltage_config,
        },
@@ -692,18 +797,165 @@ static void __init universal_sdhci_init(void)
        s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
 }
 
-/* I2C0 */
-static struct i2c_board_info i2c0_devs[] __initdata = {
-       /* Camera, To be updated */
-};
-
 /* I2C1 */
 static struct i2c_board_info i2c1_devs[] __initdata = {
        /* Gyro, To be updated */
 };
 
+/* Frame Buffer */
+static struct s3c_fb_pd_win universal_fb_win0 = {
+       .win_mode = {
+               .left_margin    = 16,
+               .right_margin   = 16,
+               .upper_margin   = 2,
+               .lower_margin   = 28,
+               .hsync_len      = 2,
+               .vsync_len      = 1,
+               .xres           = 480,
+               .yres           = 800,
+               .refresh        = 55,
+       },
+       .max_bpp        = 32,
+       .default_bpp    = 16,
+};
+
+static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
+       .win[0]         = &universal_fb_win0,
+       .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
+                         VIDCON0_CLKSEL_LCD,
+       .vidcon1        = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
+                         | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+       .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
+};
+
+static struct regulator_consumer_supply cam_i_core_supply =
+       REGULATOR_SUPPLY("core", "0-001f");
+
+static struct regulator_init_data cam_i_core_reg_init_data = {
+       .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+       .num_consumer_supplies = 1,
+       .consumer_supplies = &cam_i_core_supply,
+};
+
+static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
+       .supply_name    = "CAM_I_CORE_1.2V",
+       .microvolts     = 1200000,
+       .gpio           = EXYNOS4_GPE2(2),      /* CAM_8M_CORE_EN */
+       .enable_high    = 1,
+       .init_data      = &cam_i_core_reg_init_data,
+};
+
+static struct platform_device cam_i_core_fixed_reg_dev = {
+       .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE,
+       .dev = { .platform_data = &cam_i_core_fixed_voltage_cfg },
+};
+
+static struct regulator_consumer_supply cam_s_if_supply =
+       REGULATOR_SUPPLY("d_sensor", "0-001f");
+
+static struct regulator_init_data cam_s_if_reg_init_data = {
+       .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+       .num_consumer_supplies = 1,
+       .consumer_supplies = &cam_s_if_supply,
+};
+
+static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
+       .supply_name    = "CAM_S_IF_1.8V",
+       .microvolts     = 1800000,
+       .gpio           = EXYNOS4_GPE3(0),      /* CAM_PWR_EN1 */
+       .enable_high    = 1,
+       .init_data      = &cam_s_if_reg_init_data,
+};
+
+static struct platform_device cam_s_if_fixed_reg_dev = {
+       .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF,
+       .dev = { .platform_data = &cam_s_if_fixed_voltage_cfg },
+};
+
+static struct s5p_platform_mipi_csis mipi_csis_platdata = {
+       .clk_rate       = 166000000UL,
+       .lanes          = 2,
+       .alignment      = 32,
+       .hs_settle      = 12,
+       .phy_enable     = s5p_csis_phy_enable,
+};
+
+#define GPIO_CAM_LEVEL_EN(n)   EXYNOS4_GPE4(n + 3)
+#define GPIO_CAM_8M_ISP_INT    EXYNOS4_GPX1(5) /* XEINT_13 */
+#define GPIO_CAM_MEGA_nRST     EXYNOS4_GPE2(5)
+
+static int m5mols_set_power(struct device *dev, int on)
+{
+       gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on);
+       gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
+       return 0;
+}
+
+static struct m5mols_platform_data m5mols_platdata = {
+       .gpio_reset     = GPIO_CAM_MEGA_nRST,
+       .reset_polarity = 0,
+       .set_power      = m5mols_set_power,
+};
+
+static struct i2c_board_info m5mols_board_info = {
+       I2C_BOARD_INFO("M5MOLS", 0x1F),
+       .platform_data = &m5mols_platdata,
+};
+
+static struct s5p_fimc_isp_info universal_camera_sensors[] = {
+       {
+               .mux_id         = 0,
+               .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
+                                 V4L2_MBUS_VSYNC_ACTIVE_LOW,
+               .bus_type       = FIMC_MIPI_CSI2,
+               .board_info     = &m5mols_board_info,
+               .i2c_bus_num    = 0,
+               .clk_frequency  = 21600000UL,
+               .csi_data_align = 32,
+       },
+};
+
+static struct s5p_platform_fimc fimc_md_platdata = {
+       .isp_info       = universal_camera_sensors,
+       .num_clients    = ARRAY_SIZE(universal_camera_sensors),
+};
+
+static struct gpio universal_camera_gpios[] = {
+       { GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" },
+       { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW,  "CAM_LVL_EN2" },
+       { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,            "8M_ISP_INT"  },
+       { GPIO_CAM_MEGA_nRST,   GPIOF_OUT_INIT_LOW,  "CAM_8M_NRST" },
+};
+
+static void universal_camera_init(void)
+{
+       s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
+                        &s5p_device_mipi_csis0);
+       s3c_set_platdata(&fimc_md_platdata,  sizeof(fimc_md_platdata),
+                        &s5p_device_fimc_md);
+
+       if (gpio_request_array(universal_camera_gpios,
+                              ARRAY_SIZE(universal_camera_gpios))) {
+               pr_err("%s: GPIO request failed\n", __func__);
+               return;
+       }
+
+       if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf)))
+               m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT);
+       else
+               pr_err("Failed to configure 8M_ISP_INT GPIO\n");
+
+       /* Free GPIOs controlled directly by the sensor drivers. */
+       gpio_free(GPIO_CAM_MEGA_nRST);
+       gpio_free(GPIO_CAM_8M_ISP_INT);
+
+       if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
+               pr_err("Camera port A setup failed\n");
+}
+
 static struct platform_device *universal_devices[] __initdata = {
        /* Samsung Platform Devices */
+       &s5p_device_mipi_csis0,
        &s5p_device_fimc0,
        &s5p_device_fimc1,
        &s5p_device_fimc2,
@@ -712,17 +964,30 @@ static struct platform_device *universal_devices[] __initdata = {
        &s3c_device_hsmmc0,
        &s3c_device_hsmmc2,
        &s3c_device_hsmmc3,
+       &s3c_device_i2c0,
        &s3c_device_i2c3,
        &s3c_device_i2c5,
+       &s5p_device_i2c_hdmiphy,
+       &hdmi_fixed_voltage,
+       &exynos4_device_pd[PD_TV],
+       &s5p_device_hdmi,
+       &s5p_device_sdo,
+       &s5p_device_mixer,
 
        /* Universal Devices */
        &i2c_gpio12,
        &universal_gpio_keys,
        &s5p_device_onenand,
+       &s5p_device_fimd0,
        &s5p_device_mfc,
        &s5p_device_mfc_l,
        &s5p_device_mfc_r,
        &exynos4_device_pd[PD_MFC],
+       &exynos4_device_pd[PD_LCD0],
+       &exynos4_device_pd[PD_CAM],
+       &cam_i_core_fixed_reg_dev,
+       &cam_s_if_fixed_reg_dev,
+       &s5p_device_fimc_md,
 };
 
 static void __init universal_map_io(void)
@@ -732,6 +997,20 @@ static void __init universal_map_io(void)
        s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
 }
 
+void s5p_tv_setup(void)
+{
+       /* direct HPD to HDMI chip */
+       gpio_request(EXYNOS4_GPX3(7), "hpd-plug");
+
+       gpio_direction_input(EXYNOS4_GPX3(7));
+       s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
+       s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
+
+       /* setup dependencies between TV devices */
+       s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
+       s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
+}
+
 static void __init universal_reserve(void)
 {
        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
@@ -740,8 +1019,9 @@ static void __init universal_reserve(void)
 static void __init universal_machine_init(void)
 {
        universal_sdhci_init();
+       s5p_tv_setup();
 
-       i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
+       s3c_i2c0_set_platdata(&universal_i2c0_platdata);
        i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
 
        universal_tsp_init();
@@ -749,15 +1029,28 @@ static void __init universal_machine_init(void)
        i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
 
        s3c_i2c5_set_platdata(NULL);
+       s5p_i2c_hdmiphy_set_platdata(NULL);
        i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
 
+       s5p_fimd0_set_platdata(&universal_lcd_pdata);
+
        universal_touchkey_init();
        i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
                        ARRAY_SIZE(i2c_gpio12_devs));
 
+       universal_camera_init();
+
        /* Last */
        platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
+
        s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+       s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+
+       s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+       s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+       s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+       s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+       s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
 }
 
 MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
similarity index 91%
rename from arch/arm/mach-exynos4/mct.c
rename to arch/arm/mach-exynos/mct.c
index f191608..97343df 100644 (file)
@@ -44,7 +44,7 @@ struct mct_clock_event_device {
        char name[10];
 };
 
-struct mct_clock_event_device mct_tick[NR_CPUS];
+static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
 
 static void exynos4_mct_write(unsigned int value, void *addr)
 {
@@ -302,7 +302,7 @@ static void exynos4_mct_tick_start(unsigned long cycles,
 static int exynos4_tick_set_next_event(unsigned long cycles,
                                       struct clock_event_device *evt)
 {
-       struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
+       struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
 
        exynos4_mct_tick_start(cycles, mevt);
 
@@ -312,7 +312,7 @@ static int exynos4_tick_set_next_event(unsigned long cycles,
 static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
                                         struct clock_event_device *evt)
 {
-       struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
+       struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
 
        exynos4_mct_tick_stop(mevt);
 
@@ -376,14 +376,16 @@ static struct irqaction mct_tick1_event_irq = {
 
 static void exynos4_mct_tick_init(struct clock_event_device *evt)
 {
+       struct mct_clock_event_device *mevt;
        unsigned int cpu = smp_processor_id();
 
-       mct_tick[cpu].evt = evt;
+       mevt = this_cpu_ptr(&percpu_mct_tick);
+       mevt->evt = evt;
 
-       mct_tick[cpu].base = EXYNOS4_MCT_L_BASE(cpu);
-       sprintf(mct_tick[cpu].name, "mct_tick%d", cpu);
+       mevt->base = EXYNOS4_MCT_L_BASE(cpu);
+       sprintf(mevt->name, "mct_tick%d", cpu);
 
-       evt->name = mct_tick[cpu].name;
+       evt->name = mevt->name;
        evt->cpumask = cpumask_of(cpu);
        evt->set_next_event = exynos4_tick_set_next_event;
        evt->set_mode = exynos4_tick_set_mode;
@@ -398,21 +400,21 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
 
        clockevents_register_device(evt);
 
-       exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
+       exynos4_mct_write(0x1, mevt->base + MCT_L_TCNTB_OFFSET);
 
        if (mct_int_type == MCT_INT_SPI) {
                if (cpu == 0) {
-                       mct_tick0_event_irq.dev_id = &mct_tick[cpu];
+                       mct_tick0_event_irq.dev_id = mevt;
                        evt->irq = IRQ_MCT_L0;
                        setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
                } else {
-                       mct_tick1_event_irq.dev_id = &mct_tick[cpu];
+                       mct_tick1_event_irq.dev_id = mevt;
                        evt->irq = IRQ_MCT_L1;
                        setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
                        irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
                }
        } else {
-               gic_enable_ppi(IRQ_MCT_LOCALTIMER);
+               enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0);
        }
 }
 
@@ -427,9 +429,11 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)
 void local_timer_stop(struct clock_event_device *evt)
 {
        evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
-       disable_irq(evt->irq);
+       if (mct_int_type == MCT_INT_SPI)
+               disable_irq(evt->irq);
+       else
+               disable_percpu_irq(IRQ_MCT_LOCALTIMER);
 }
-
 #endif /* CONFIG_LOCAL_TIMERS */
 
 static void __init exynos4_timer_resources(void)
@@ -438,6 +442,16 @@ static void __init exynos4_timer_resources(void)
        mct_clk = clk_get(NULL, "xtal");
 
        clk_rate = clk_get_rate(mct_clk);
+
+       if (mct_int_type == MCT_INT_PPI) {
+               int err;
+
+               err = request_percpu_irq(IRQ_MCT_LOCALTIMER,
+                                        exynos4_mct_tick_isr, "MCT",
+                                        &percpu_mct_tick);
+               WARN(err, "MCT: can't request IRQ %d (%d)\n",
+                    IRQ_MCT_LOCALTIMER, err);
+       }
 }
 
 static void __init exynos4_timer_init(void)
similarity index 98%
rename from arch/arm/mach-exynos4/pm.c
rename to arch/arm/mach-exynos/pm.c
index 62e4f43..509a435 100644 (file)
@@ -339,6 +339,13 @@ static int exynos4_pm_suspend(void)
        tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
        __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 
+       if (soc_is_exynos4212()) {
+               tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
+               tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
+                        S5P_USE_STANDBYWFE_ISP_ARM);
+               __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+       }
+
        /* Save Power control register */
        asm ("mrc p15, 0, %0, c15, c0, 0"
             : "=r" (tmp) : : "cc");
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
new file mode 100644 (file)
index 0000000..bba48f5
--- /dev/null
@@ -0,0 +1,230 @@
+/* linux/arch/arm/mach-exynos4/pmu.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com/
+ *
+ * EXYNOS4210 - CPU PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include <mach/regs-clock.h>
+#include <mach/pmu.h>
+
+static struct exynos4_pmu_conf *exynos4_pmu_config;
+
+static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
+       /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+       { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
+       { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
+       { S5P_DIS_IRQ_CENTRAL0,                 { 0x0, 0x0, 0x0 } },
+       { S5P_ARM_CORE1_LOWPWR,                 { 0x0, 0x0, 0x2 } },
+       { S5P_DIS_IRQ_CORE1,                    { 0x0, 0x0, 0x0 } },
+       { S5P_DIS_IRQ_CENTRAL1,                 { 0x0, 0x0, 0x0 } },
+       { S5P_ARM_COMMON_LOWPWR,                { 0x0, 0x0, 0x2 } },
+       { S5P_L2_0_LOWPWR,                      { 0x2, 0x2, 0x3 } },
+       { S5P_L2_1_LOWPWR,                      { 0x2, 0x2, 0x3 } },
+       { S5P_CMU_ACLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_SCLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_LOWPWR,                 { 0x1, 0x1, 0x0 } },
+       { S5P_APLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+       { S5P_MPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+       { S5P_VPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+       { S5P_EPLL_SYSCLK_LOWPWR,               { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,     { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_GPSALIVE_LOWPWR,        { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_CAM_LOWPWR,           { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_TV_LOWPWR,            { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_MFC_LOWPWR,           { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_G3D_LOWPWR,           { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_LCD0_LOWPWR,          { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_LCD1_LOWPWR,          { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,        { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_CLKSTOP_GPS_LOWPWR,           { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_CAM_LOWPWR,             { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_TV_LOWPWR,              { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_MFC_LOWPWR,             { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_G3D_LOWPWR,             { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_LCD0_LOWPWR,            { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_LCD1_LOWPWR,            { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_GPS_LOWPWR,             { 0x1, 0x1, 0x0 } },
+       { S5P_TOP_BUS_LOWPWR,                   { 0x3, 0x0, 0x0 } },
+       { S5P_TOP_RETENTION_LOWPWR,             { 0x1, 0x0, 0x1 } },
+       { S5P_TOP_PWR_LOWPWR,                   { 0x3, 0x0, 0x3 } },
+       { S5P_LOGIC_RESET_LOWPWR,               { 0x1, 0x1, 0x0 } },
+       { S5P_ONENAND_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+       { S5P_MODIMIF_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+       { S5P_G2D_ACP_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+       { S5P_USBOTG_MEM_LOWPWR,                { 0x3, 0x0, 0x0 } },
+       { S5P_HSMMC_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+       { S5P_CSSYS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+       { S5P_SECSS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+       { S5P_PCIE_MEM_LOWPWR,                  { 0x3, 0x0, 0x0 } },
+       { S5P_SATA_MEM_LOWPWR,                  { 0x3, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_DRAM_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_MAUDIO_LOWPWR,      { 0x1, 0x1, 0x0 } },
+       { S5P_PAD_RETENTION_GPIO_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_UART_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_MMCA_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_MMCB_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_EBIA_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_EBIB_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_ISOLATION_LOWPWR,   { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_ALV_SEL_LOWPWR,     { 0x1, 0x0, 0x0 } },
+       { S5P_XUSBXTI_LOWPWR,                   { 0x1, 0x1, 0x0 } },
+       { S5P_XXTI_LOWPWR,                      { 0x1, 0x1, 0x0 } },
+       { S5P_EXT_REGULATOR_LOWPWR,             { 0x1, 0x1, 0x0 } },
+       { S5P_GPIO_MODE_LOWPWR,                 { 0x1, 0x0, 0x0 } },
+       { S5P_GPIO_MODE_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
+       { S5P_CAM_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_TV_LOWPWR,                        { 0x7, 0x0, 0x0 } },
+       { S5P_MFC_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_G3D_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_LCD0_LOWPWR,                      { 0x7, 0x0, 0x0 } },
+       { S5P_LCD1_LOWPWR,                      { 0x7, 0x0, 0x0 } },
+       { S5P_MAUDIO_LOWPWR,                    { 0x7, 0x7, 0x0 } },
+       { S5P_GPS_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_GPS_ALIVE_LOWPWR,                 { 0x7, 0x0, 0x0 } },
+       { PMU_TABLE_END,},
+};
+
+static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
+       { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
+       { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
+       { S5P_DIS_IRQ_CENTRAL0,                 { 0x0, 0x0, 0x0 } },
+       { S5P_ARM_CORE1_LOWPWR,                 { 0x0, 0x0, 0x2 } },
+       { S5P_DIS_IRQ_CORE1,                    { 0x0, 0x0, 0x0 } },
+       { S5P_DIS_IRQ_CENTRAL1,                 { 0x0, 0x0, 0x0 } },
+       { S5P_ISP_ARM_LOWPWR,                   { 0x1, 0x0, 0x0 } },
+       { S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR,     { 0x0, 0x0, 0x0 } },
+       { S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR,   { 0x0, 0x0, 0x0 } },
+       { S5P_ARM_COMMON_LOWPWR,                { 0x0, 0x0, 0x2 } },
+       { S5P_L2_0_LOWPWR,                      { 0x0, 0x0, 0x3 } },
+       /* XXX_OPTION register should be set other field */
+       { S5P_ARM_L2_0_OPTION,                  { 0x10, 0x10, 0x0 } },
+       { S5P_L2_1_LOWPWR,                      { 0x0, 0x0, 0x3 } },
+       { S5P_ARM_L2_1_OPTION,                  { 0x10, 0x10, 0x0 } },
+       { S5P_CMU_ACLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_SCLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_LOWPWR,                 { 0x1, 0x1, 0x0 } },
+       { S5P_DRAM_FREQ_DOWN_LOWPWR,            { 0x1, 0x1, 0x1 } },
+       { S5P_DDRPHY_DLLOFF_LOWPWR,             { 0x1, 0x1, 0x1 } },
+       { S5P_LPDDR_PHY_DLL_LOCK_LOWPWR,        { 0x1, 0x1, 0x1 } },
+       { S5P_CMU_ACLKSTOP_COREBLK_LOWPWR,      { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_SCLKSTOP_COREBLK_LOWPWR,      { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_COREBLK_LOWPWR,         { 0x1, 0x1, 0x0 } },
+       { S5P_APLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+       { S5P_MPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+       { S5P_VPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+       { S5P_EPLL_SYSCLK_LOWPWR,               { 0x1, 0x1, 0x0 } },
+       { S5P_MPLLUSER_SYSCLK_LOWPWR,           { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,     { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_GPSALIVE_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_CAM_LOWPWR,           { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_TV_LOWPWR,            { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_MFC_LOWPWR,           { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_G3D_LOWPWR,           { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_LCD0_LOWPWR,          { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_ISP_LOWPWR,           { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_CLKSTOP_GPS_LOWPWR,           { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_CAM_LOWPWR,             { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_TV_LOWPWR,              { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_MFC_LOWPWR,             { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_G3D_LOWPWR,             { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_LCD0_LOWPWR,            { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_ISP_LOWPWR,             { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_RESET_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
+       { S5P_CMU_RESET_GPS_LOWPWR,             { 0x1, 0x0, 0x0 } },
+       { S5P_TOP_BUS_LOWPWR,                   { 0x3, 0x0, 0x0 } },
+       { S5P_TOP_RETENTION_LOWPWR,             { 0x1, 0x0, 0x1 } },
+       { S5P_TOP_PWR_LOWPWR,                   { 0x3, 0x0, 0x3 } },
+       { S5P_TOP_BUS_COREBLK_LOWPWR,           { 0x3, 0x0, 0x0 } },
+       { S5P_TOP_RETENTION_COREBLK_LOWPWR,     { 0x1, 0x0, 0x1 } },
+       { S5P_TOP_PWR_COREBLK_LOWPWR,           { 0x3, 0x0, 0x3 } },
+       { S5P_LOGIC_RESET_LOWPWR,               { 0x1, 0x1, 0x0 } },
+       { S5P_OSCCLK_GATE_LOWPWR,               { 0x1, 0x0, 0x1 } },
+       { S5P_LOGIC_RESET_COREBLK_LOWPWR,       { 0x1, 0x1, 0x0 } },
+       { S5P_OSCCLK_GATE_COREBLK_LOWPWR,       { 0x1, 0x0, 0x1 } },
+       { S5P_ONENAND_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+       { S5P_ONENAND_MEM_OPTION,               { 0x10, 0x10, 0x0 } },
+       { S5P_HSI_MEM_LOWPWR,                   { 0x3, 0x0, 0x0 } },
+       { S5P_HSI_MEM_OPTION,                   { 0x10, 0x10, 0x0 } },
+       { S5P_G2D_ACP_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+       { S5P_G2D_ACP_MEM_OPTION,               { 0x10, 0x10, 0x0 } },
+       { S5P_USBOTG_MEM_LOWPWR,                { 0x3, 0x0, 0x0 } },
+       { S5P_USBOTG_MEM_OPTION,                { 0x10, 0x10, 0x0 } },
+       { S5P_HSMMC_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+       { S5P_HSMMC_MEM_OPTION,                 { 0x10, 0x10, 0x0 } },
+       { S5P_CSSYS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+       { S5P_CSSYS_MEM_OPTION,                 { 0x10, 0x10, 0x0 } },
+       { S5P_SECSS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+       { S5P_SECSS_MEM_OPTION,                 { 0x10, 0x10, 0x0 } },
+       { S5P_ROTATOR_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+       { S5P_ROTATOR_MEM_OPTION,               { 0x10, 0x10, 0x0 } },
+       { S5P_PAD_RETENTION_DRAM_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_MAUDIO_LOWPWR,      { 0x1, 0x1, 0x0 } },
+       { S5P_PAD_RETENTION_GPIO_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_UART_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_MMCA_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_MMCB_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_EBIA_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_EBIB_LOWPWR,        { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR,{ 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_ISOLATION_LOWPWR,   { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_ISOLATION_COREBLK_LOWPWR,     { 0x1, 0x0, 0x0 } },
+       { S5P_PAD_RETENTION_ALV_SEL_LOWPWR,     { 0x1, 0x0, 0x0 } },
+       { S5P_XUSBXTI_LOWPWR,                   { 0x1, 0x1, 0x0 } },
+       { S5P_XXTI_LOWPWR,                      { 0x1, 0x1, 0x0 } },
+       { S5P_EXT_REGULATOR_LOWPWR,             { 0x1, 0x1, 0x0 } },
+       { S5P_GPIO_MODE_LOWPWR,                 { 0x1, 0x0, 0x0 } },
+       { S5P_GPIO_MODE_COREBLK_LOWPWR,         { 0x1, 0x0, 0x0 } },
+       { S5P_GPIO_MODE_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
+       { S5P_TOP_ASB_RESET_LOWPWR,             { 0x1, 0x1, 0x1 } },
+       { S5P_TOP_ASB_ISOLATION_LOWPWR,         { 0x1, 0x0, 0x1 } },
+       { S5P_CAM_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_TV_LOWPWR,                        { 0x7, 0x0, 0x0 } },
+       { S5P_MFC_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_G3D_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_LCD0_LOWPWR,                      { 0x7, 0x0, 0x0 } },
+       { S5P_ISP_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_MAUDIO_LOWPWR,                    { 0x7, 0x7, 0x0 } },
+       { S5P_GPS_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+       { S5P_GPS_ALIVE_LOWPWR,                 { 0x7, 0x0, 0x0 } },
+       { S5P_CMU_SYSCLK_ISP_LOWPWR,            { 0x1, 0x0, 0x0 } },
+       { S5P_CMU_SYSCLK_GPS_LOWPWR,            { 0x1, 0x0, 0x0 } },
+       { PMU_TABLE_END,},
+};
+
+void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
+{
+       unsigned int i;
+
+       for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
+               __raw_writel(exynos4_pmu_config[i].val[mode],
+                               exynos4_pmu_config[i].reg);
+}
+
+static int __init exynos4_pmu_init(void)
+{
+       exynos4_pmu_config = exynos4210_pmu_config;
+
+       if (soc_is_exynos4210()) {
+               exynos4_pmu_config = exynos4210_pmu_config;
+               pr_info("EXYNOS4210 PMU Initialize\n");
+       } else if (soc_is_exynos4212()) {
+               exynos4_pmu_config = exynos4212_pmu_config;
+               pr_info("EXYNOS4212 PMU Initialize\n");
+       } else {
+               pr_info("EXYNOS4: PMU not supported\n");
+       }
+
+       return 0;
+}
+arch_initcall(exynos4_pmu_init);
diff --git a/arch/arm/mach-exynos/setup-sdhci.c b/arch/arm/mach-exynos/setup-sdhci.c
new file mode 100644 (file)
index 0000000..92937b4
--- /dev/null
@@ -0,0 +1,22 @@
+/* linux/arch/arm/mach-exynos4/setup-sdhci.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/types.h>
+
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+
+char *exynos4_hsmmc_clksrcs[4] = {
+       [0] = NULL,
+       [1] = NULL,
+       [2] = "sclk_mmc",       /* mmc_bus */
+       [3] = NULL,
+};
diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h b/arch/arm/mach-exynos4/include/mach/clkdev.h
deleted file mode 100644 (file)
index 7dffa83..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H__
-#define __MACH_CLKDEV_H__
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do {} while (0)
-
-#endif
diff --git a/arch/arm/mach-exynos4/mach-origen.c b/arch/arm/mach-exynos4/mach-origen.c
deleted file mode 100644 (file)
index b5f6f38..0000000
+++ /dev/null
@@ -1,108 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-origen.c
- *
- * Copyright (c) 2011 Insignal Co., Ltd.
- *             http://www.insignal.co.kr/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/serial_core.h>
-#include <linux/gpio.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/input.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <plat/regs-serial.h>
-#include <plat/exynos4.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/sdhci.h>
-#include <plat/iic.h>
-
-#include <mach/map.h>
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define ORIGEN_UCON_DEFAULT    (S3C2410_UCON_TXILEVEL |        \
-                                S3C2410_UCON_RXILEVEL |        \
-                                S3C2410_UCON_TXIRQMODE |       \
-                                S3C2410_UCON_RXIRQMODE |       \
-                                S3C2410_UCON_RXFIFO_TOI |      \
-                                S3C2443_UCON_RXERR_IRQEN)
-
-#define ORIGEN_ULCON_DEFAULT   S3C2410_LCON_CS8
-
-#define ORIGEN_UFCON_DEFAULT   (S3C2410_UFCON_FIFOMODE |       \
-                                S5PV210_UFCON_TXTRIG4 |        \
-                                S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
-       [0] = {
-               .hwport         = 0,
-               .flags          = 0,
-               .ucon           = ORIGEN_UCON_DEFAULT,
-               .ulcon          = ORIGEN_ULCON_DEFAULT,
-               .ufcon          = ORIGEN_UFCON_DEFAULT,
-       },
-       [1] = {
-               .hwport         = 1,
-               .flags          = 0,
-               .ucon           = ORIGEN_UCON_DEFAULT,
-               .ulcon          = ORIGEN_ULCON_DEFAULT,
-               .ufcon          = ORIGEN_UFCON_DEFAULT,
-       },
-       [2] = {
-               .hwport         = 2,
-               .flags          = 0,
-               .ucon           = ORIGEN_UCON_DEFAULT,
-               .ulcon          = ORIGEN_ULCON_DEFAULT,
-               .ufcon          = ORIGEN_UFCON_DEFAULT,
-       },
-       [3] = {
-               .hwport         = 3,
-               .flags          = 0,
-               .ucon           = ORIGEN_UCON_DEFAULT,
-               .ulcon          = ORIGEN_ULCON_DEFAULT,
-               .ufcon          = ORIGEN_UFCON_DEFAULT,
-       },
-};
-
-static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
-       .cd_type                = S3C_SDHCI_CD_GPIO,
-       .ext_cd_gpio            = EXYNOS4_GPK2(2),
-       .ext_cd_gpio_invert     = 1,
-       .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-static struct platform_device *origen_devices[] __initdata = {
-       &s3c_device_hsmmc2,
-       &s3c_device_rtc,
-       &s3c_device_wdt,
-};
-
-static void __init origen_map_io(void)
-{
-       s5p_init_io(NULL, 0, S5P_VA_CHIPID);
-       s3c24xx_init_clocks(24000000);
-       s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
-}
-
-static void __init origen_machine_init(void)
-{
-       s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
-       platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
-}
-
-MACHINE_START(ORIGEN, "ORIGEN")
-       /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
-       .atag_offset    = 0x100,
-       .init_irq       = exynos4_init_irq,
-       .map_io         = origen_map_io,
-       .init_machine   = origen_machine_init,
-       .timer          = &exynos4_timer,
-MACHINE_END
diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos4/pmu.c
deleted file mode 100644 (file)
index 7ea9eb2..0000000
+++ /dev/null
@@ -1,175 +0,0 @@
-/* linux/arch/arm/mach-exynos4/pmu.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com/
- *
- * EXYNOS4210 - CPU PMU(Power Management Unit) support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/io.h>
-#include <linux/kernel.h>
-
-#include <mach/regs-clock.h>
-#include <mach/pmu.h>
-
-static void __iomem *sys_powerdown_reg[] = {
-       S5P_ARM_CORE0_LOWPWR,
-       S5P_DIS_IRQ_CORE0,
-       S5P_DIS_IRQ_CENTRAL0,
-       S5P_ARM_CORE1_LOWPWR,
-       S5P_DIS_IRQ_CORE1,
-       S5P_DIS_IRQ_CENTRAL1,
-       S5P_ARM_COMMON_LOWPWR,
-       S5P_L2_0_LOWPWR,
-       S5P_L2_1_LOWPWR,
-       S5P_CMU_ACLKSTOP_LOWPWR,
-       S5P_CMU_SCLKSTOP_LOWPWR,
-       S5P_CMU_RESET_LOWPWR,
-       S5P_APLL_SYSCLK_LOWPWR,
-       S5P_MPLL_SYSCLK_LOWPWR,
-       S5P_VPLL_SYSCLK_LOWPWR,
-       S5P_EPLL_SYSCLK_LOWPWR,
-       S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
-       S5P_CMU_RESET_GPSALIVE_LOWPWR,
-       S5P_CMU_CLKSTOP_CAM_LOWPWR,
-       S5P_CMU_CLKSTOP_TV_LOWPWR,
-       S5P_CMU_CLKSTOP_MFC_LOWPWR,
-       S5P_CMU_CLKSTOP_G3D_LOWPWR,
-       S5P_CMU_CLKSTOP_LCD0_LOWPWR,
-       S5P_CMU_CLKSTOP_LCD1_LOWPWR,
-       S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
-       S5P_CMU_CLKSTOP_GPS_LOWPWR,
-       S5P_CMU_RESET_CAM_LOWPWR,
-       S5P_CMU_RESET_TV_LOWPWR,
-       S5P_CMU_RESET_MFC_LOWPWR,
-       S5P_CMU_RESET_G3D_LOWPWR,
-       S5P_CMU_RESET_LCD0_LOWPWR,
-       S5P_CMU_RESET_LCD1_LOWPWR,
-       S5P_CMU_RESET_MAUDIO_LOWPWR,
-       S5P_CMU_RESET_GPS_LOWPWR,
-       S5P_TOP_BUS_LOWPWR,
-       S5P_TOP_RETENTION_LOWPWR,
-       S5P_TOP_PWR_LOWPWR,
-       S5P_LOGIC_RESET_LOWPWR,
-       S5P_ONENAND_MEM_LOWPWR,
-       S5P_MODIMIF_MEM_LOWPWR,
-       S5P_G2D_ACP_MEM_LOWPWR,
-       S5P_USBOTG_MEM_LOWPWR,
-       S5P_HSMMC_MEM_LOWPWR,
-       S5P_CSSYS_MEM_LOWPWR,
-       S5P_SECSS_MEM_LOWPWR,
-       S5P_PCIE_MEM_LOWPWR,
-       S5P_SATA_MEM_LOWPWR,
-       S5P_PAD_RETENTION_DRAM_LOWPWR,
-       S5P_PAD_RETENTION_MAUDIO_LOWPWR,
-       S5P_PAD_RETENTION_GPIO_LOWPWR,
-       S5P_PAD_RETENTION_UART_LOWPWR,
-       S5P_PAD_RETENTION_MMCA_LOWPWR,
-       S5P_PAD_RETENTION_MMCB_LOWPWR,
-       S5P_PAD_RETENTION_EBIA_LOWPWR,
-       S5P_PAD_RETENTION_EBIB_LOWPWR,
-       S5P_PAD_RETENTION_ISOLATION_LOWPWR,
-       S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
-       S5P_XUSBXTI_LOWPWR,
-       S5P_XXTI_LOWPWR,
-       S5P_EXT_REGULATOR_LOWPWR,
-       S5P_GPIO_MODE_LOWPWR,
-       S5P_GPIO_MODE_MAUDIO_LOWPWR,
-       S5P_CAM_LOWPWR,
-       S5P_TV_LOWPWR,
-       S5P_MFC_LOWPWR,
-       S5P_G3D_LOWPWR,
-       S5P_LCD0_LOWPWR,
-       S5P_LCD1_LOWPWR,
-       S5P_MAUDIO_LOWPWR,
-       S5P_GPS_LOWPWR,
-       S5P_GPS_ALIVE_LOWPWR,
-};
-
-static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
-       /* { AFTR, LPA, SLEEP }*/
-       { 0, 0, 2 },    /* ARM_CORE0 */
-       { 0, 0, 0 },    /* ARM_DIS_IRQ_CORE0 */
-       { 0, 0, 0 },    /* ARM_DIS_IRQ_CENTRAL0 */
-       { 0, 0, 2 },    /* ARM_CORE1 */
-       { 0, 0, 0 },    /* ARM_DIS_IRQ_CORE1 */
-       { 0, 0, 0 },    /* ARM_DIS_IRQ_CENTRAL1 */
-       { 0, 0, 2 },    /* ARM_COMMON */
-       { 2, 2, 3 },    /* ARM_CPU_L2_0 */
-       { 2, 2, 3 },    /* ARM_CPU_L2_1 */
-       { 1, 0, 0 },    /* CMU_ACLKSTOP */
-       { 1, 0, 0 },    /* CMU_SCLKSTOP */
-       { 1, 1, 0 },    /* CMU_RESET */
-       { 1, 0, 0 },    /* APLL_SYSCLK */
-       { 1, 0, 0 },    /* MPLL_SYSCLK */
-       { 1, 0, 0 },    /* VPLL_SYSCLK */
-       { 1, 1, 0 },    /* EPLL_SYSCLK */
-       { 1, 1, 0 },    /* CMU_CLKSTOP_GPS_ALIVE */
-       { 1, 1, 0 },    /* CMU_RESET_GPS_ALIVE */
-       { 1, 1, 0 },    /* CMU_CLKSTOP_CAM */
-       { 1, 1, 0 },    /* CMU_CLKSTOP_TV */
-       { 1, 1, 0 },    /* CMU_CLKSTOP_MFC */
-       { 1, 1, 0 },    /* CMU_CLKSTOP_G3D */
-       { 1, 1, 0 },    /* CMU_CLKSTOP_LCD0 */
-       { 1, 1, 0 },    /* CMU_CLKSTOP_LCD1 */
-       { 1, 1, 0 },    /* CMU_CLKSTOP_MAUDIO */
-       { 1, 1, 0 },    /* CMU_CLKSTOP_GPS */
-       { 1, 1, 0 },    /* CMU_RESET_CAM */
-       { 1, 1, 0 },    /* CMU_RESET_TV */
-       { 1, 1, 0 },    /* CMU_RESET_MFC */
-       { 1, 1, 0 },    /* CMU_RESET_G3D */
-       { 1, 1, 0 },    /* CMU_RESET_LCD0 */
-       { 1, 1, 0 },    /* CMU_RESET_LCD1 */
-       { 1, 1, 0 },    /* CMU_RESET_MAUDIO */
-       { 1, 1, 0 },    /* CMU_RESET_GPS */
-       { 3, 0, 0 },    /* TOP_BUS */
-       { 1, 0, 1 },    /* TOP_RETENTION */
-       { 3, 0, 3 },    /* TOP_PWR */
-       { 1, 1, 0 },    /* LOGIC_RESET */
-       { 3, 0, 0 },    /* ONENAND_MEM */
-       { 3, 0, 0 },    /* MODIMIF_MEM */
-       { 3, 0, 0 },    /* G2D_ACP_MEM */
-       { 3, 0, 0 },    /* USBOTG_MEM */
-       { 3, 0, 0 },    /* HSMMC_MEM */
-       { 3, 0, 0 },    /* CSSYS_MEM */
-       { 3, 0, 0 },    /* SECSS_MEM */
-       { 3, 0, 0 },    /* PCIE_MEM */
-       { 3, 0, 0 },    /* SATA_MEM */
-       { 1, 0, 0 },    /* PAD_RETENTION_DRAM */
-       { 1, 1, 0 },    /* PAD_RETENTION_MAUDIO */
-       { 1, 0, 0 },    /* PAD_RETENTION_GPIO */
-       { 1, 0, 0 },    /* PAD_RETENTION_UART */
-       { 1, 0, 0 },    /* PAD_RETENTION_MMCA */
-       { 1, 0, 0 },    /* PAD_RETENTION_MMCB */
-       { 1, 0, 0 },    /* PAD_RETENTION_EBIA */
-       { 1, 0, 0 },    /* PAD_RETENTION_EBIB */
-       { 1, 0, 0 },    /* PAD_RETENTION_ISOLATION */
-       { 1, 0, 0 },    /* PAD_RETENTION_ALV_SEL */
-       { 1, 1, 0 },    /* XUSBXTI */
-       { 1, 1, 0 },    /* XXTI */
-       { 1, 1, 0 },    /* EXT_REGULATOR */
-       { 1, 0, 0 },    /* GPIO_MODE */
-       { 1, 1, 0 },    /* GPIO_MODE_MAUDIO */
-       { 7, 0, 0 },    /* CAM */
-       { 7, 0, 0 },    /* TV */
-       { 7, 0, 0 },    /* MFC */
-       { 7, 0, 0 },    /* G3D */
-       { 7, 0, 0 },    /* LCD0 */
-       { 7, 0, 0 },    /* LCD1 */
-       { 7, 7, 0 },    /* MAUDIO */
-       { 7, 0, 0 },    /* GPS */
-       { 7, 0, 0 },    /* GPS_ALIVE */
-};
-
-void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
-{
-       unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
-
-       for (; count > 0; count--)
-               __raw_writel(sys_powerdown_val[count - 1][mode],
-                               sys_powerdown_reg[count - 1]);
-}
diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c
deleted file mode 100644 (file)
index 1e83f8c..0000000
+++ /dev/null
@@ -1,69 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-sdhci.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <linux/mmc/card.h>
-#include <linux/mmc/host.h>
-
-#include <plat/regs-sdhci.h>
-
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-
-char *exynos4_hsmmc_clksrcs[4] = {
-       [0] = NULL,
-       [1] = NULL,
-       [2] = "sclk_mmc",       /* mmc_bus */
-       [3] = NULL,
-};
-
-void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
-                                 struct mmc_ios *ios, struct mmc_card *card)
-{
-       u32 ctrl2, ctrl3;
-
-       /* don't need to alter anything according to card-type */
-
-       ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
-
-       /* select base clock source to HCLK */
-
-       ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
-
-       /*
-        * clear async mode, enable conflict mask, rx feedback ctrl, SD
-        * clk hold and no use debounce count
-        */
-
-       ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
-                 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
-                 S3C_SDHCI_CTRL2_ENFBCLKRX |
-                 S3C_SDHCI_CTRL2_DFCNT_NONE |
-                 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
-
-       /* Tx and Rx feedback clock delay control */
-
-       if (ios->clock < 25 * 1000000)
-               ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
-                        S3C_SDHCI_CTRL3_FCSEL2 |
-                        S3C_SDHCI_CTRL3_FCSEL1 |
-                        S3C_SDHCI_CTRL3_FCSEL0);
-       else
-               ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
-
-       writel(ctrl2, r + S3C_SDHCI_CONTROL2);
-       writel(ctrl3, r + S3C_SDHCI_CONTROL3);
-}
index 8f948f9..ba254a7 100644 (file)
@@ -7,7 +7,7 @@ obj-y                           += common.o clock.o devices.o time.o
 # SoC support
 obj-$(CONFIG_CPU_PXA168)       += pxa168.o irq-pxa168.o
 obj-$(CONFIG_CPU_PXA910)       += pxa910.o irq-pxa168.o
-obj-$(CONFIG_CPU_MMP2)         += mmp2.o irq-mmp2.o
+obj-$(CONFIG_CPU_MMP2)         += mmp2.o irq-mmp2.o sram.o
 
 # board support
 obj-$(CONFIG_MACH_ASPENITE)    += aspenite.o
index e411252..983cfb1 100644 (file)
@@ -185,6 +185,15 @@ static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc2 = {
                | PXA_FLAG_SD_8_BIT_CAPABLE_SLOT,
 };
 
+static struct sram_platdata mmp2_asram_platdata = {
+       .pool_name      = "asram",
+       .granularity    = SRAM_GRANULARITY,
+};
+
+static struct sram_platdata mmp2_isram_platdata = {
+       .pool_name      = "isram",
+       .granularity    = SRAM_GRANULARITY,
+};
 
 static void __init brownstone_init(void)
 {
@@ -196,6 +205,8 @@ static void __init brownstone_init(void)
        mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
        mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
        mmp2_add_sdhost(2, &mmp2_sdh_platdata_mmc2); /* eMMC */
+       mmp2_add_asram(&mmp2_asram_platdata);
+       mmp2_add_isram(&mmp2_isram_platdata);
 
        /* enable 5v regulator */
        platform_device_register(&brownstone_v_5vp_device);
index de7b888..2f7b2d3 100644 (file)
@@ -13,6 +13,7 @@ extern void mmp2_clear_pmic_int(void);
 #include <linux/i2c.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <mach/devices.h>
+#include <mach/sram.h>
 
 extern struct pxa_device_desc mmp2_device_uart1;
 extern struct pxa_device_desc mmp2_device_uart2;
@@ -28,6 +29,8 @@ extern struct pxa_device_desc mmp2_device_sdh0;
 extern struct pxa_device_desc mmp2_device_sdh1;
 extern struct pxa_device_desc mmp2_device_sdh2;
 extern struct pxa_device_desc mmp2_device_sdh3;
+extern struct pxa_device_desc mmp2_device_asram;
+extern struct pxa_device_desc mmp2_device_isram;
 
 static inline int mmp2_add_uart(int id)
 {
@@ -85,5 +88,15 @@ static inline int mmp2_add_sdhost(int id, struct sdhci_pxa_platdata *data)
        return pxa_register_device(d, data, sizeof(*data));
 }
 
+static inline int mmp2_add_asram(struct sram_platdata *data)
+{
+       return pxa_register_device(&mmp2_device_asram, data, sizeof(*data));
+}
+
+static inline int mmp2_add_isram(struct sram_platdata *data)
+{
+       return pxa_register_device(&mmp2_device_isram, data, sizeof(*data));
+}
+
 #endif /* __ASM_MACH_MMP2_H */
 
diff --git a/arch/arm/mach-mmp/include/mach/sram.h b/arch/arm/mach-mmp/include/mach/sram.h
new file mode 100644 (file)
index 0000000..239e0fc
--- /dev/null
@@ -0,0 +1,35 @@
+/*
+ *  linux/arch/arm/mach-mmp/include/mach/sram.h
+ *
+ *  SRAM Memory Management
+ *
+ *  Copyright (c) 2011 Marvell Semiconductors Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_SRAM_H
+#define __ASM_ARCH_SRAM_H
+
+#include <linux/genalloc.h>
+
+/* ARBITRARY:  SRAM allocations are multiples of this 2^N size */
+#define SRAM_GRANULARITY       512
+
+enum sram_type {
+       MMP_SRAM_UNDEFINED = 0,
+       MMP_ASRAM,
+       MMP_ISRAM,
+};
+
+struct sram_platdata {
+       char *pool_name;
+       int granularity;
+};
+
+extern struct gen_pool *sram_get_gpool(char *pool_name);
+
+#endif /* __ASM_ARCH_SRAM_H */
index 7a7e8e4..5dd1d4a 100644 (file)
@@ -226,4 +226,7 @@ MMP2_DEVICE(sdh0, "sdhci-pxav3", 0, MMC, 0xd4280000, 0x120);
 MMP2_DEVICE(sdh1, "sdhci-pxav3", 1, MMC2, 0xd4280800, 0x120);
 MMP2_DEVICE(sdh2, "sdhci-pxav3", 2, MMC3, 0xd4281000, 0x120);
 MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120);
+MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000);
+/* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */
+MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000);
 
diff --git a/arch/arm/mach-mmp/sram.c b/arch/arm/mach-mmp/sram.c
new file mode 100644 (file)
index 0000000..4304f95
--- /dev/null
@@ -0,0 +1,168 @@
+/*
+ *  linux/arch/arm/mach-mmp/sram.c
+ *
+ *  based on mach-davinci/sram.c - DaVinci simple SRAM allocator
+ *
+ *  Copyright (c) 2011 Marvell Semiconductors Inc.
+ *  All Rights Reserved
+ *
+ *  Add for mmp sram support - Leo Yan <leoy@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/genalloc.h>
+
+#include <mach/sram.h>
+
+struct sram_bank_info {
+       char *pool_name;
+       struct gen_pool *gpool;
+       int granularity;
+
+       phys_addr_t sram_phys;
+       void __iomem *sram_virt;
+       u32 sram_size;
+
+       struct list_head node;
+};
+
+static DEFINE_MUTEX(sram_lock);
+static LIST_HEAD(sram_bank_list);
+
+struct gen_pool *sram_get_gpool(char *pool_name)
+{
+       struct sram_bank_info *info = NULL;
+
+       if (!pool_name)
+               return NULL;
+
+       mutex_lock(&sram_lock);
+
+       list_for_each_entry(info, &sram_bank_list, node)
+               if (!strcmp(pool_name, info->pool_name))
+                       break;
+
+       mutex_unlock(&sram_lock);
+
+       if (&info->node == &sram_bank_list)
+               return NULL;
+
+       return info->gpool;
+}
+EXPORT_SYMBOL(sram_get_gpool);
+
+static int __devinit sram_probe(struct platform_device *pdev)
+{
+       struct sram_platdata *pdata = pdev->dev.platform_data;
+       struct sram_bank_info *info;
+       struct resource *res;
+       int ret = 0;
+
+       if (!pdata && !pdata->pool_name)
+               return -ENODEV;
+
+       info = kzalloc(sizeof(*info), GFP_KERNEL);
+       if (!info)
+               return -ENOMEM;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       if (res == NULL) {
+               dev_err(&pdev->dev, "no memory resource defined\n");
+               ret = -ENODEV;
+               goto out;
+       }
+
+       if (!resource_size(res))
+               return 0;
+
+       info->sram_phys   = (phys_addr_t)res->start;
+       info->sram_size   = resource_size(res);
+       info->sram_virt   = ioremap(info->sram_phys, info->sram_size);
+       info->pool_name   = kstrdup(pdata->pool_name, GFP_KERNEL);
+       info->granularity = pdata->granularity;
+
+       info->gpool = gen_pool_create(ilog2(info->granularity), -1);
+       if (!info->gpool) {
+               dev_err(&pdev->dev, "create pool failed\n");
+               ret = -ENOMEM;
+               goto create_pool_err;
+       }
+
+       ret = gen_pool_add_virt(info->gpool, (unsigned long)info->sram_virt,
+                               info->sram_phys, info->sram_size, -1);
+       if (ret < 0) {
+               dev_err(&pdev->dev, "add new chunk failed\n");
+               ret = -ENOMEM;
+               goto add_chunk_err;
+       }
+
+       mutex_lock(&sram_lock);
+       list_add(&info->node, &sram_bank_list);
+       mutex_unlock(&sram_lock);
+
+       platform_set_drvdata(pdev, info);
+
+       dev_info(&pdev->dev, "initialized\n");
+       return 0;
+
+add_chunk_err:
+       gen_pool_destroy(info->gpool);
+create_pool_err:
+       iounmap(info->sram_virt);
+       kfree(info->pool_name);
+out:
+       kfree(info);
+       return ret;
+}
+
+static int __devexit sram_remove(struct platform_device *pdev)
+{
+       struct sram_bank_info *info;
+
+       info = platform_get_drvdata(pdev);
+       if (info == NULL)
+               return -ENODEV;
+
+       mutex_lock(&sram_lock);
+       list_del(&info->node);
+       mutex_unlock(&sram_lock);
+
+       gen_pool_destroy(info->gpool);
+       iounmap(info->sram_virt);
+       kfree(info->pool_name);
+       kfree(info);
+       return 0;
+}
+
+static const struct platform_device_id sram_id_table[] = {
+       { "asram", MMP_ASRAM },
+       { "isram", MMP_ISRAM },
+       { }
+};
+
+static struct platform_driver sram_driver = {
+       .probe          = sram_probe,
+       .remove         = sram_remove,
+       .driver         = {
+               .name   = "mmp-sram",
+       },
+       .id_table       = sram_id_table,
+};
+
+static int __init sram_init(void)
+{
+       return platform_driver_register(&sram_driver);
+}
+core_initcall(sram_init);
+
+MODULE_LICENSE("GPL");
index 3700cf3..5261a7e 100644 (file)
@@ -6,7 +6,6 @@ config CPU_S3C2410
        bool
        depends on ARCH_S3C2410
        select CPU_ARM920T
-       select S3C_GPIO_PULL_UP
        select S3C2410_CLOCK
        select CPU_LLSERIAL_S3C2410
        select S3C2410_PM if PM
index eee0654..a957bc8 100644 (file)
@@ -1,74 +1 @@
-/* arch/arm/mach-s3c2410/include/mach/fb.h
- *
- * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
- *
- * Inspired by pxafb.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARM_FB_H
-#define __ASM_ARM_FB_H
-
-#include <mach/regs-lcd.h>
-
-struct s3c2410fb_hw {
-       unsigned long   lcdcon1;
-       unsigned long   lcdcon2;
-       unsigned long   lcdcon3;
-       unsigned long   lcdcon4;
-       unsigned long   lcdcon5;
-};
-
-/* LCD description */
-struct s3c2410fb_display {
-       /* LCD type */
-       unsigned type;
-
-       /* Screen size */
-       unsigned short width;
-       unsigned short height;
-
-       /* Screen info */
-       unsigned short xres;
-       unsigned short yres;
-       unsigned short bpp;
-
-       unsigned pixclock;              /* pixclock in picoseconds */
-       unsigned short left_margin;  /* value in pixels (TFT) or HCLKs (STN) */
-       unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */
-       unsigned short hsync_len;    /* value in pixels (TFT) or HCLKs (STN) */
-       unsigned short upper_margin;    /* value in lines (TFT) or 0 (STN) */
-       unsigned short lower_margin;    /* value in lines (TFT) or 0 (STN) */
-       unsigned short vsync_len;       /* value in lines (TFT) or 0 (STN) */
-
-       /* lcd configuration registers */
-       unsigned long   lcdcon5;
-};
-
-struct s3c2410fb_mach_info {
-
-       struct s3c2410fb_display *displays;     /* attached diplays info */
-       unsigned num_displays;                  /* number of defined displays */
-       unsigned default_display;
-
-       /* GPIOs */
-
-       unsigned long   gpcup;
-       unsigned long   gpcup_mask;
-       unsigned long   gpccon;
-       unsigned long   gpccon_mask;
-       unsigned long   gpdup;
-       unsigned long   gpdup_mask;
-       unsigned long   gpdcon;
-       unsigned long   gpdcon_mask;
-
-       /* lpc3600 control register */
-       unsigned long   lpcsel;
-};
-
-extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
-
-#endif /* __ASM_ARM_FB_H */
+#include <plat/fb-s3c2410.h>
index bab1392..c53ad34 100644 (file)
@@ -1,98 +1 @@
-/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
- *
- * Copyright (c) 2003-2009 Simtec Electronics
- *     Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - hardware
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __MACH_GPIO_FNS_H
-#define __MACH_GPIO_FNS_H __FILE__
-
-/* These functions are in the to-be-removed category and it is strongly
- * encouraged not to use these in new code. They will be marked deprecated
- * very soon.
- *
- * Most of the functionality can be either replaced by the gpiocfg calls
- * for the s3c platform or by the generic GPIOlib API.
- *
- * As of 2.6.35-rc, these will be removed, with the few drivers using them
- * either replaced or given a wrapper until the calls can be removed.
-*/
-
-#include <plat/gpio-cfg.h>
-
-static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg)
-{
-       /* 1:1 mapping between cfgpin and setcfg calls at the moment */
-       s3c_gpio_cfgpin(pin, cfg);
-}
-
-/* external functions for GPIO support
- *
- * These allow various different clients to access the same GPIO
- * registers without conflicting. If your driver only owns the entire
- * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
-*/
-
-extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
-
-/* s3c2410_gpio_getirq
- *
- * turn the given pin number into the corresponding IRQ number
- *
- * returns:
- *     < 0 = no interrupt for this pin
- *     >=0 = interrupt number for the pin
-*/
-
-extern int s3c2410_gpio_getirq(unsigned int pin);
-
-/* s3c2410_gpio_irqfilter
- *
- * set the irq filtering on the given pin
- *
- * on = 0 => disable filtering
- *      1 => enable filtering
- *
- * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
- *          width of filter (0 through 63)
- *
- *
-*/
-
-extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
-                                 unsigned int config);
-
-/* s3c2410_gpio_pullup
- *
- * This call should be replaced with s3c_gpio_setpull().
- *
- * As a note, there is currently no distinction between pull-up and pull-down
- * in the s3c24xx series devices with only an on/off configuration.
- */
-
-/* s3c2410_gpio_pullup
- *
- * configure the pull-up control on the given pin
- *
- * to = 1 => disable the pull-up
- *      0 => enable the pull-up
- *
- * eg;
- *
- *   s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
- *   s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
-*/
-
-extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
-
-extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
-
-extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
-
-#endif /* __MACH_GPIO_FNS_H */
+#include <plat/gpio-fns.h>
index 4f7bf32..019ea86 100644 (file)
@@ -53,7 +53,7 @@
 #define S3C2410_GPIO_M_NR      (32)    /* technically 2. */
 
 #if CONFIG_S3C_GPIO_SPACE != 0
-#error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment
+#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment
 #endif
 
 #define S3C2410_GPIO_NEXT(__gpio) \
index d67819d..c410a07 100644 (file)
 
 #include <mach/regs-gpio.h>
 
-extern struct s3c_gpio_chip s3c24xx_gpios[];
+extern struct samsung_gpio_chip s3c24xx_gpios[];
 
-static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
+static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin)
 {
-       struct s3c_gpio_chip *chip;
+       struct samsung_gpio_chip *chip;
 
        if (pin > S3C_GPIO_END)
                return NULL;
index e5a68ea..e53b217 100644 (file)
 #define IRQ_LCD_SYSTEM         IRQ_S3C2443_LCD2
 
 #ifdef CONFIG_CPU_S3C2440
-#define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97
+#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97
 #else
-#define IRQ_S3C244x_AC97 IRQ_S3C2443_AC97
+#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97
 #endif
 
 /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
index 4cf495f..78ae807 100644 (file)
 #define S3C24XX_PA_RTC      S3C2410_PA_RTC
 #define S3C24XX_PA_ADC      S3C2410_PA_ADC
 #define S3C24XX_PA_SPI      S3C2410_PA_SPI
+#define S3C24XX_PA_SPI1                (S3C2410_PA_SPI + S3C2410_SPI1)
 #define S3C24XX_PA_SDI      S3C2410_PA_SDI
 #define S3C24XX_PA_NAND            S3C2410_PA_NAND
 
index 45eea52..2eef7e6 100644 (file)
@@ -64,4 +64,4 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
 }
 
 static inline void s3c_pm_restored_gpios(void) { }
-static inline void s3c_pm_saved_gpios(void) { }
+static inline void samsung_pm_saved_gpios(void) { }
index 5e06c72..c3feff3 100644 (file)
@@ -65,6 +65,7 @@
 #define S3C2443_CLKDIV0_PREDIV_MASK    (3<<4)
 #define S3C2443_CLKDIV0_PREDIV_SHIFT   (4)
 
+#define S3C2416_CLKDIV0_ARMDIV_MASK    (7 << 9)
 #define S3C2443_CLKDIV0_ARMDIV_MASK    (15<<9)
 #define S3C2443_CLKDIV0_ARMDIV_SHIFT   (9)
 #define S3C2443_CLKDIV0_ARMDIV_1       (0<<9)
 #define S3C2443_PCLKCON_UART3          (1<<3)
 #define S3C2443_PCLKCON_IIC            (1<<4)
 #define S3C2443_PCLKCON_SDI            (1<<5)
+#define S3C2443_PCLKCON_HSSPI          (1<<6)
 #define S3C2443_PCLKCON_ADC            (1<<7)
 #define S3C2443_PCLKCON_AC97           (1<<8)
 #define S3C2443_PCLKCON_IIS            (1<<9)
index 556c535..caa4ae2 100644 (file)
@@ -696,9 +696,9 @@ static void __init h1940_init(void)
                              S3C2410_MISCCR_USBSUSPND0 |
                              S3C2410_MISCCR_USBSUSPND1, 0x0);
 
-       tmp =   (0x78 << S3C24XX_PLLCON_MDIVSHIFT)
-             | (0x02 << S3C24XX_PLLCON_PDIVSHIFT)
-             | (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
+       tmp =   (0x78 << S3C24XX_PLL_MDIV_SHIFT)
+             | (0x02 << S3C24XX_PLL_PDIV_SHIFT)
+             | (0x03 << S3C24XX_PLL_SDIV_SHIFT);
        writel(tmp, S3C2410_UPLLCON);
 
        gpio_request(S3C2410_GPC(0), "LCD power");
index 367d376..4518521 100644 (file)
@@ -49,6 +49,7 @@
 
 #include <mach/regs-gpio.h>
 #include <mach/leds-gpio.h>
+#include <mach/regs-lcd.h>
 #include <plat/regs-serial.h>
 #include <mach/fb.h>
 #include <plat/nand.h>
index 343a540..3d7ebc5 100644 (file)
@@ -72,8 +72,8 @@ void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 
 void __init s3c2410_map_io(void)
 {
-       s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
-       s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
+       s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up;
+       s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up;
 
        iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
 }
diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c
new file mode 100644 (file)
index 0000000..4526f6b
--- /dev/null
@@ -0,0 +1,62 @@
+/* linux/arch/arm/mach-s3c2412/gpio.c
+ *
+ * Copyright (c) 2007 Simtec Electronics
+ *     Ben Dooks <ben@simtec.co.uk>
+ *
+ * http://armlinux.simtec.co.uk/.
+ *
+ * S3C2412/S3C2413 specific GPIO support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/regs-gpio.h>
+#include <mach/hardware.h>
+
+#include <plat/gpio-core.h>
+
+int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
+{
+       struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
+       unsigned long offs = pin - chip->chip.base;
+       unsigned long flags;
+       unsigned long slpcon;
+
+       offs *= 2;
+
+       if (pin < S3C2410_GPB(0))
+               return -EINVAL;
+
+       if (pin >= S3C2410_GPF(0) &&
+           pin <= S3C2410_GPG(16))
+               return -EINVAL;
+
+       if (pin > S3C2410_GPH(16))
+               return -EINVAL;
+
+       local_irq_save(flags);
+
+       slpcon = __raw_readl(chip->base + 0x0C);
+
+       slpcon &= ~(3 << offs);
+       slpcon |= state << offs;
+
+       __raw_writel(slpcon, chip->base + 0x0C);
+
+       local_irq_restore(flags);
+
+       return 0;
+}
+
+EXPORT_SYMBOL(s3c2412_gpio_set_sleepcfg);
index 69b48a7..84c7b03 100644 (file)
@@ -13,7 +13,6 @@ config CPU_S3C2416
        select CPU_ARM926T
        select S3C2416_DMA if S3C2410_DMA
        select CPU_LLSERIAL_S3C2440
-       select S3C_GPIO_PULL_UPDOWN
        select SAMSUNG_CLKSRC
        select S3C2443_CLOCK
        help
index 21a5e81..afbbe8b 100644 (file)
@@ -21,7 +21,6 @@
 #include <plat/cpu.h>
 
 #include <plat/cpu-freq.h>
-#include <plat/pll6553x.h>
 #include <plat/pll.h>
 
 #include <asm/mach/map.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-s3c2443-clock.h>
 
+/* armdiv
+ *
+ * this clock is sourced from msysclk and can have a number of
+ * divider values applied to it to then be fed into armclk.
+ * The real clock definition is done in s3c2443-clock.c,
+ * only the armdiv divisor table must be defined here.
+*/
+
 static unsigned int armdiv[8] = {
        [0] = 1,
        [1] = 2,
@@ -38,6 +45,32 @@ static unsigned int armdiv[8] = {
        [7] = 8,
 };
 
+static struct clksrc_clk hsspi_eplldiv = {
+       .clk = {
+               .name   = "hsspi-eplldiv",
+               .parent = &clk_esysclk.clk,
+               .ctrlbit = (1 << 14),
+               .enable = s3c2443_clkcon_enable_s,
+       },
+       .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
+};
+
+static struct clk *hsspi_sources[] = {
+       [0] = &hsspi_eplldiv.clk,
+       [1] = NULL, /* to fix */
+};
+
+static struct clksrc_clk hsspi_mux = {
+       .clk    = {
+               .name   = "hsspi-if",
+       },
+       .sources = &(struct clksrc_sources) {
+               .sources = hsspi_sources,
+               .nr_sources = ARRAY_SIZE(hsspi_sources),
+       },
+       .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
+};
+
 static struct clksrc_clk hsmmc_div[] = {
        [0] = {
                .clk = {
@@ -100,20 +133,15 @@ static struct clk hsmmc0_clk = {
        .ctrlbit        = S3C2416_HCLKCON_HSMMC0,
 };
 
-static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
-{
-       clkcon0 &= 7 << S3C2443_CLKDIV0_ARMDIV_SHIFT;
-
-       return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
-}
-
 void __init_or_cpufreq s3c2416_setup_clocks(void)
 {
-       s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div);
+       s3c2443_common_setup_clocks(s3c2416_get_pll);
 }
 
 
 static struct clksrc_clk *clksrcs[] __initdata = {
+       &hsspi_eplldiv,
+       &hsspi_mux,
        &hsmmc_div[0],
        &hsmmc_div[1],
        &hsmmc_mux[0],
@@ -131,7 +159,9 @@ void __init s3c2416_init_clocks(int xtal)
 
        clk_epll.parent = &clk_epllref.clk;
 
-       s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div);
+       s3c2443_common_init_clocks(xtal, s3c2416_get_pll,
+                                  armdiv, ARRAY_SIZE(armdiv),
+                                  S3C2416_CLKDIV0_ARMDIV_MASK);
 
        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
                s3c_register_clksrc(clksrcs[ptr], 1);
index 20b3fdf..ee214bc 100644 (file)
@@ -60,6 +60,7 @@
 #include <plat/iic-core.h>
 #include <plat/fb-core.h>
 #include <plat/nand-core.h>
+#include <plat/adc-core.h>
 
 static struct map_desc s3c2416_iodesc[] __initdata = {
        IODESC_ENT(WATCHDOG),
@@ -97,6 +98,8 @@ int __init s3c2416_init(void)
 
        s3c_fb_setname("s3c2443-fb");
 
+       s3c_adc_setname("s3c2416-adc");
+
 #ifdef CONFIG_PM
        register_syscore_ops(&s3c2416_pm_syscore_ops);
 #endif
@@ -120,8 +123,8 @@ void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 
 void __init s3c2416_map_io(void)
 {
-       s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown;
-       s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown;
+       s3c24xx_gpiocfg_default.set_pull = samsung_gpio_setpull_updown;
+       s3c24xx_gpiocfg_default.get_pull = samsung_gpio_getpull_updown;
 
        /* initialize device information early */
        s3c2416_default_sdhci0();
index ed34fad..cee5395 100644 (file)
  * published by the Free Software Foundation.
 */
 
-#include <linux/kernel.h>
 #include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <linux/mmc/card.h>
-#include <linux/mmc/host.h>
-
-#include <plat/regs-sdhci.h>
-#include <plat/sdhci.h>
 
 /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
 
@@ -32,30 +22,3 @@ char *s3c2416_hsmmc_clksrcs[4] = {
        [2] = "hsmmc-if",
        /* [3] = "48m", - note not successfully used yet */
 };
-
-void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
-                                 void __iomem *r,
-                                 struct mmc_ios *ios,
-                                 struct mmc_card *card)
-{
-       u32 ctrl2, ctrl3;
-
-       ctrl2 = __raw_readl(r + S3C_SDHCI_CONTROL2);
-       ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
-       ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
-                 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
-                 S3C_SDHCI_CTRL2_ENFBCLKRX |
-                 S3C_SDHCI_CTRL2_DFCNT_NONE |
-                 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
-
-       if (ios->clock < 25 * 1000000)
-               ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
-                        S3C_SDHCI_CTRL3_FCSEL2 |
-                        S3C_SDHCI_CTRL3_FCSEL1 |
-                        S3C_SDHCI_CTRL3_FCSEL0);
-       else
-               ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
-
-       __raw_writel(ctrl2, r + S3C_SDHCI_CONTROL2);
-       __raw_writel(ctrl3, r + S3C_SDHCI_CONTROL3);
-}
index c461fb8..914e620 100644 (file)
@@ -5,7 +5,6 @@
 config CPU_S3C2440
        bool
        select CPU_ARM920T
-       select S3C_GPIO_PULL_UP
        select S3C2410_CLOCK
        select S3C2410_PM if PM
        select S3C2440_DMA if S3C2410_DMA
@@ -17,7 +16,6 @@ config CPU_S3C2440
 config CPU_S3C2442
        bool
        select CPU_ARM920T
-       select S3C_GPIO_PULL_DOWN
        select S3C2410_CLOCK
        select S3C2410_PM if PM
        select CPU_S3C244X
index 684dbb3..0d3453b 100644 (file)
@@ -43,6 +43,7 @@
 
 #include <mach/regs-gpio.h>
 #include <mach/regs-gpioj.h>
+#include <mach/regs-lcd.h>
 #include <mach/h1940.h>
 #include <mach/fb.h>
 
index 2270d33..37f8cc6 100644 (file)
@@ -70,6 +70,6 @@ void __init s3c2440_map_io(void)
 {
        s3c244x_map_io();
 
-       s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
-       s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
+       s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up;
+       s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up;
 }
index 6f2b65e..2c822e0 100644 (file)
@@ -182,6 +182,6 @@ void __init s3c2442_map_io(void)
 {
        s3c244x_map_io();
 
-       s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1down;
-       s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1down;
+       s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1down;
+       s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1down;
 }
index d8eb868..8814031 100644 (file)
@@ -10,7 +10,6 @@ config CPU_S3C2443
        select CPU_LLSERIAL_S3C2440
        select SAMSUNG_CLKSRC
        select S3C2443_CLOCK
-       select S3C_GPIO_PULL_S3C2443
        help
          Support for the S3C2443 SoC from the S3C24XX line
 
index 38058af..1c2c088 100644 (file)
 
 /* clock selections */
 
-static struct clk clk_i2s_ext = {
-       .name           = "i2s-ext",
-};
-
 /* armdiv
  *
  * this clock is sourced from msysclk and can have a number of
  * divider values applied to it to then be fed into armclk.
+ * The real clock definition is done in s3c2443-clock.c,
+ * only the armdiv divisor table must be defined here.
 */
 
-/* armdiv divisor table */
-
 static unsigned int armdiv[16] = {
        [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 1,
        [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 2,
@@ -80,92 +76,6 @@ static unsigned int armdiv[16] = {
        [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]     = 16,
 };
 
-static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
-{
-       clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
-
-       return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
-}
-
-static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
-                                             unsigned long rate)
-{
-       unsigned long parent = clk_get_rate(clk->parent);
-       unsigned long calc;
-       unsigned best = 256; /* bigger than any value */
-       unsigned div;
-       int ptr;
-
-       for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
-               div = armdiv[ptr];
-               calc = parent / div;
-               if (calc <= rate && div < best)
-                       best = div;
-       }
-
-       return parent / best;
-}
-
-static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
-{
-       unsigned long parent = clk_get_rate(clk->parent);
-       unsigned long calc;
-       unsigned div;
-       unsigned best = 256; /* bigger than any value */
-       int ptr;
-       int val = -1;
-
-       for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
-               div = armdiv[ptr];
-               calc = parent / div;
-               if (calc <= rate && div < best) {
-                       best = div;
-                       val = ptr;
-               }
-       }
-
-       if (val >= 0) {
-               unsigned long clkcon0;
-
-               clkcon0 = __raw_readl(S3C2443_CLKDIV0);
-               clkcon0 &= ~S3C2443_CLKDIV0_ARMDIV_MASK;
-               clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
-               __raw_writel(clkcon0, S3C2443_CLKDIV0);
-       }
-
-       return (val == -1) ? -EINVAL : 0;
-}
-
-static struct clk clk_armdiv = {
-       .name           = "armdiv",
-       .parent         = &clk_msysclk.clk,
-       .ops            = &(struct clk_ops) {
-               .round_rate = s3c2443_armclk_roundrate,
-               .set_rate = s3c2443_armclk_setrate,
-       },
-};
-
-/* armclk
- *
- * this is the clock fed into the ARM core itself, from armdiv or from hclk.
- */
-
-static struct clk *clk_arm_sources[] = {
-       [0] = &clk_armdiv,
-       [1] = &clk_h,
-};
-
-static struct clksrc_clk clk_arm = {
-       .clk    = {
-               .name           = "armclk",
-       },
-       .sources = &(struct clksrc_sources) {
-               .sources = clk_arm_sources,
-               .nr_sources = ARRAY_SIZE(clk_arm_sources),
-       },
-       .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
-};
-
 /* hsspi
  *
  * high-speed spi clock, sourced from esysclk
@@ -173,7 +83,7 @@ static struct clksrc_clk clk_arm = {
 
 static struct clksrc_clk clk_hsspi = {
        .clk    = {
-               .name           = "hsspi",
+               .name           = "hsspi-if",
                .parent         = &clk_esysclk.clk,
                .ctrlbit        = S3C2443_SCLKCON_HSSPICLK,
                .enable         = s3c2443_clkcon_enable_s,
@@ -235,48 +145,6 @@ static struct clk clk_hsmmc = {
        },
 };
 
-/* i2s_eplldiv
- *
- * This clock is the output from the I2S divisor of ESYSCLK, and is separate
- * from the mux that comes after it (cannot merge into one single clock)
-*/
-
-static struct clksrc_clk clk_i2s_eplldiv = {
-       .clk    = {
-               .name           = "i2s-eplldiv",
-               .parent         = &clk_esysclk.clk,
-       },
-       .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
-};
-
-/* i2s-ref
- *
- * i2s bus reference clock, selectable from external, esysclk or epllref
- *
- * Note, this used to be two clocks, but was compressed into one.
-*/
-
-struct clk *clk_i2s_srclist[] = {
-       [0] = &clk_i2s_eplldiv.clk,
-       [1] = &clk_i2s_ext,
-       [2] = &clk_epllref.clk,
-       [3] = &clk_epllref.clk,
-};
-
-static struct clksrc_clk clk_i2s = {
-       .clk    = {
-               .name           = "i2s-if",
-               .ctrlbit        = S3C2443_SCLKCON_I2SCLK,
-               .enable         = s3c2443_clkcon_enable_s,
-
-       },
-       .sources = &(struct clksrc_sources) {
-               .sources = clk_i2s_srclist,
-               .nr_sources = ARRAY_SIZE(clk_i2s_srclist),
-       },
-       .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
-};
-
 /* standard clock definitions */
 
 static struct clk init_clocks_off[] = {
@@ -286,11 +154,6 @@ static struct clk init_clocks_off[] = {
                .enable         = s3c2443_clkcon_enable_p,
                .ctrlbit        = S3C2443_PCLKCON_SDI,
        }, {
-               .name           = "iis",
-               .parent         = &clk_p,
-               .enable         = s3c2443_clkcon_enable_p,
-               .ctrlbit        = S3C2443_PCLKCON_IIS,
-       }, {
                .name           = "spi",
                .devname        = "s3c2410-spi.0",
                .parent         = &clk_p,
@@ -305,27 +168,20 @@ static struct clk init_clocks_off[] = {
        }
 };
 
-static struct clk init_clocks[] = {
-};
-
 /* clocks to add straight away */
 
 static struct clksrc_clk *clksrcs[] __initdata = {
-       &clk_arm,
-       &clk_i2s_eplldiv,
-       &clk_i2s,
        &clk_hsspi,
        &clk_hsmmc_div,
 };
 
 static struct clk *clks[] __initdata = {
        &clk_hsmmc,
-       &clk_armdiv,
 };
 
 void __init_or_cpufreq s3c2443_setup_clocks(void)
 {
-       s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div);
+       s3c2443_common_setup_clocks(s3c2443_get_mpll);
 }
 
 void __init s3c2443_init_clocks(int xtal)
@@ -336,7 +192,9 @@ void __init s3c2443_init_clocks(int xtal)
        clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
        clk_epll.parent = &clk_epllref.clk;
 
-       s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div);
+       s3c2443_common_init_clocks(xtal, s3c2443_get_mpll,
+                                  armdiv, ARRAY_SIZE(armdiv),
+                                  S3C2443_CLKDIV0_ARMDIV_MASK);
 
        s3c2443_setup_clocks();
 
@@ -345,10 +203,6 @@ void __init s3c2443_init_clocks(int xtal)
        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
                s3c_register_clksrc(clksrcs[ptr], 1);
 
-       /* register clocks from clock array */
-
-       s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-
        /* We must be careful disabling the clocks we are not intending to
         * be using at boot time, as subsystems such as the LCD which do
         * their own DMA requests to the bus can cause the system to lockup
index e6a28ba..a22b771 100644 (file)
@@ -41,6 +41,7 @@
 #include <plat/cpu.h>
 #include <plat/fb-core.h>
 #include <plat/nand-core.h>
+#include <plat/adc-core.h>
 
 static struct map_desc s3c2443_iodesc[] __initdata = {
        IODESC_ENT(WATCHDOG),
@@ -70,6 +71,8 @@ int __init s3c2443_init(void)
        s3c_nand_setname("s3c2412-nand");
        s3c_fb_setname("s3c2443-fb");
 
+       s3c_adc_setname("s3c2443-adc");
+
        /* change WDT IRQ number */
        s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
        s3c_device_wdt.resource[1].end   = IRQ_S3C2443_WDT;
@@ -90,8 +93,8 @@ void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 
 void __init s3c2443_map_io(void)
 {
-       s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_s3c2443;
-       s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_s3c2443;
+       s3c24xx_gpiocfg_default.set_pull = s3c2443_gpio_setpull;
+       s3c24xx_gpiocfg_default.get_pull = s3c2443_gpio_getpull;
 
        iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
 }
index f057b6a..5552e04 100644 (file)
@@ -288,5 +288,6 @@ config MACH_WLF_CRAGG_6410
        select S3C_DEV_RTC
        select S3C64XX_DEV_SPI
        select S3C24XX_GPIO_EXTRA128
+       select I2C
        help
          Machine support for the Wolfson Cragganmore S3C6410 variant.
index 61b4034..cfc0b99 100644 (file)
@@ -13,7 +13,6 @@ obj-                          :=
 # Core files
 obj-y                          += cpu.o
 obj-y                          += clock.o
-obj-y                          += gpiolib.o
 
 # Core support for S3C6400 system
 
@@ -55,12 +54,10 @@ obj-$(CONFIG_MACH_HMT)              += mach-hmt.o
 obj-$(CONFIG_MACH_SMARTQ)      += mach-smartq.o
 obj-$(CONFIG_MACH_SMARTQ5)     += mach-smartq5.o
 obj-$(CONFIG_MACH_SMARTQ7)     += mach-smartq7.o
-obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o
+obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
 
 # device support
 
 obj-y                          += dev-uart.o
 obj-y                          += dev-audio.o
 obj-$(CONFIG_S3C64XX_DEV_SPI)  += dev-spi.o
-obj-$(CONFIG_S3C64XX_DEV_TS)   += dev-ts.o
-obj-$(CONFIG_S3C64XX_DEV_ONENAND1)     += dev-onenand1.o
index 8cf39e3..39c238d 100644 (file)
 
 #include <mach/regs-sys.h>
 #include <mach/regs-clock.h>
-#include <mach/pll.h>
 
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/cpu-freq.h>
 #include <plat/clock.h>
 #include <plat/clock-clksrc.h>
+#include <plat/pll.h>
 
 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
  * ext_xtal_mux for want of an actual name from the manual.
@@ -735,7 +735,8 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
        /* For now assume the mux always selects the crystal */
        clk_ext_xtal_mux.parent = xtal_clk;
 
-       epll = s3c6400_get_epll(xtal);
+       epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
+                               __raw_readl(S3C_EPLL_CON1));
        mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
        apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
 
@@ -744,7 +745,13 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
        printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
               apll, mpll, epll);
 
-       hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
+       if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
+               /* Synchronous mode */
+               hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
+       else
+               /* Asynchronous mode */
+               hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
+
        hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
        pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);