arm: tegra: cardhu: move VI to PLL_P
Jihoon Bang [Fri, 29 Jun 2012 20:54:34 +0000 (13:54 -0700)]
As a part of effort to bring in 437MHz clock frequency in EMC,
We need to move VI from PLL_M to PLL_P.

Bug 1005576

Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/112704
(cherry picked from commit c175857e80355857b55e8eb2012c12e94e532835)

Change-Id: Icd314c01625f5c4765b0215735ceafb7d3f25d1e
Reviewed-on: http://git-master/r/114241
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

arch/arm/mach-tegra/board-cardhu.c

index 402d8dd..1fa3f4f 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/board-cardhu.c
  *
- * Copyright (c) 2011-2012, NVIDIA Corporation.
+ * Copyright (c) 2011-2012, NVIDIA Corporation.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -234,6 +234,7 @@ static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
        { "i2c3",       "pll_p",        3200000,        false},
        { "i2c4",       "pll_p",        3200000,        false},
        { "i2c5",       "pll_p",        3200000,        false},
+       { "vi",         "pll_p",        0,              false},
        { NULL,         NULL,           0,              0},
 };