ARM: tegra11: dvfs: Acquire CL-DVFS clocks in probe
Alex Frid [Tue, 9 Oct 2012 06:00:48 +0000 (23:00 -0700)]
Acquired CL-DVFS clocks in driver probe function (instead of
pre-populating during dfll initialization).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142850
(cherry picked from commit 66dc99a9ce766bb464a1ddfab49cf89776fc006b)

Change-Id: I9b94f9c61f7b0a76ae3433fe752b0ed5e1941cb6
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146276

arch/arm/mach-tegra/devices.c
arch/arm/mach-tegra/tegra11_clocks.c
arch/arm/mach-tegra/tegra_cl_dvfs.c

index c3e9718..f20873f 100644 (file)
@@ -2134,7 +2134,7 @@ static struct resource cl_dvfs_resource[] = {
 
 struct platform_device tegra_cl_dvfs_device = {
        .name           = "tegra_cl_dvfs",
-       .id             = 0,
+       .id             = -1,
        .resource       = cl_dvfs_resource,
        .num_resources  = ARRAY_SIZE(cl_dvfs_resource),
 };
index 9cf875b..8453d92 100644 (file)
@@ -3198,8 +3198,6 @@ static struct clk_ops tegra_plle_ops = {
 static void __init tegra11_dfll_cpu_late_init(struct clk *c)
 {
        int ret;
-       struct clk *cpu_clk;
-       struct tegra_cl_dvfs *cld = c->u.dfll.cl_dvfs;
 
 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
        u32 netlist, patchid;
@@ -3210,22 +3208,6 @@ static void __init tegra11_dfll_cpu_late_init(struct clk *c)
                return;
        }
 #endif
-
-       cpu_clk = tegra_get_clock_by_name("cpu_g");
-       BUG_ON(!cpu_clk);
-
-       cld->safe_dvfs = cpu_clk->dvfs;
-       cld->ref_clk = clk_get_sys("dfll_cpu", "ref");
-       cld->soc_clk = clk_get_sys("dfll_cpu", "soc");
-       cld->i2c_clk = clk_get_sys("dfll_cpu", "i2c");
-       if (IS_ERR_OR_NULL(cld->ref_clk) || IS_ERR_OR_NULL(cld->soc_clk) ||
-              IS_ERR_OR_NULL(cld->i2c_clk))
-       {
-               WARN(1, "%s: could not find CPU DFLL control clocks\n",
-                    __func__);
-               return;
-       }
-
        /* release dfll clock source reset, init cl_dvfs control logic, and
           move dfll to initialized state, so it can be used as CPU source */
        tegra_periph_reset_deassert(c);
@@ -6271,8 +6253,8 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("afi",       "tegra-pcie",           "afi",  72,     0,      250000000, mux_clk_m,                   0),
        PERIPH_CLK("se",        "se",                   NULL,   127,    0x42c,  600000000, mux_pllp_pllc2_c_c3_pllm_clkm,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
        PERIPH_CLK("mselect",   "mselect",              NULL,   99,     0x3b4,  108000000, mux_pllp_clkm,               MUX | DIV_U71),
-       PERIPH_CLK("cl_dvfs_ref", "dfll_cpu",           "ref",  155,    0x62c,  54000000,  mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
-       PERIPH_CLK("cl_dvfs_soc", "dfll_cpu",           "soc",  155,    0x630,  54000000,  mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
+       PERIPH_CLK("cl_dvfs_ref", "tegra_cl_dvfs",      "ref",  155,    0x62c,  54000000,  mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
+       PERIPH_CLK("cl_dvfs_soc", "tegra_cl_dvfs",      "soc",  155,    0x630,  54000000,  mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
        PERIPH_CLK("soc_therm", "soc_therm",            NULL,   78,     0x644,  136000000, mux_pllm_pllc_pllp_plla,     MUX | MUX8 | DIV_U71 | PERIPH_ON_APB),
 
        PERIPH_CLK("dds",       "dds",                  NULL,   150,    0,      26000000, mux_clk_m,                    PERIPH_ON_APB),
@@ -6459,7 +6441,8 @@ struct clk_duplicate tegra_clk_duplicates[] = {
        CLK_DUPLICATE("avp.sclk", "nvavp", "sclk"),
        CLK_DUPLICATE("avp.emc", "nvavp", "emc"),
        CLK_DUPLICATE("vde.cbus", "nvavp", "vde"),
-       CLK_DUPLICATE("i2c5", "dfll_cpu", "i2c"),
+       CLK_DUPLICATE("i2c5", "tegra_cl_dvfs", "i2c"),
+       CLK_DUPLICATE("cpu_g", "tegra_cl_dvfs", "safe_dvfs"),
        CLK_DUPLICATE("host1x", "tegra_host1x", "host1x"),
        CLK_DUPLICATE("epp.cbus", "tegra_isp", "epp"),
 };
index 9f8acf4..f534305 100644 (file)
@@ -492,7 +492,7 @@ static int __init tegra_cl_dvfs_probe(struct platform_device *pdev)
 {
        struct tegra_cl_dvfs_platform_data *p_data;
        struct resource *res;
-       struct clk *c;
+       struct clk *c, *ref_clk, *soc_clk, *i2c_clk, *safe_dvfs_clk;
 
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        if (!res) {
@@ -505,6 +505,20 @@ static int __init tegra_cl_dvfs_probe(struct platform_device *pdev)
                dev_err(&pdev->dev, "missing platform data\n");
                return -ENODATA;
        }
+
+       ref_clk = clk_get(&pdev->dev, "ref");
+       soc_clk = clk_get(&pdev->dev, "soc");
+       i2c_clk = clk_get(&pdev->dev, "i2c");
+       safe_dvfs_clk = clk_get(&pdev->dev, "safe_dvfs");
+       if (IS_ERR(ref_clk) || IS_ERR(soc_clk) || IS_ERR(i2c_clk)) {
+               dev_err(&pdev->dev, "missing control clock\n");
+               return -ENODEV;
+       }
+       if (IS_ERR(safe_dvfs_clk)) {
+               dev_err(&pdev->dev, "missing safe dvfs source clock\n");
+               return PTR_ERR(safe_dvfs_clk);
+       }
+
        c = tegra_get_clock_by_name(p_data->dfll_clk_name);
        if (!c || !c->u.dfll.cl_dvfs) {
                dev_err(&pdev->dev, "missing target dfll\n");
@@ -513,6 +527,10 @@ static int __init tegra_cl_dvfs_probe(struct platform_device *pdev)
 
        c->u.dfll.cl_dvfs->cl_base = (u32)IO_ADDRESS(res->start);
        c->u.dfll.cl_dvfs->p_data = p_data;
+       c->u.dfll.cl_dvfs->ref_clk = ref_clk;
+       c->u.dfll.cl_dvfs->soc_clk = soc_clk;
+       c->u.dfll.cl_dvfs->i2c_clk = i2c_clk;
+       c->u.dfll.cl_dvfs->safe_dvfs = safe_dvfs_clk->dvfs;
        return cl_dvfs_init(c->u.dfll.cl_dvfs);
 }