ARM: tegra: clock: increase Tegra3 pll post-lock delay
Sang-Hun Lee [Fri, 27 Jul 2012 16:57:54 +0000 (09:57 -0700)]
Bug 1022877

Change-Id: I9200d3345a933ab0ccb31f833184ee4a621228f0
Reviewed-on: http://git-master/r/118774
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Sang-Hun Lee <sanlee@nvidia.com>
Tested-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com>

arch/arm/mach-tegra/clock.h

index 8888084..c27176b 100644 (file)
@@ -27,7 +27,7 @@
 #else
 #define USE_PLL_LOCK_BITS 1    /* Use lock bits for PLL stabiliation */
 #define USE_PLLE_SS 1          /* Use spread spectrum coefficients for PLLE */
-#define PLL_POST_LOCK_DELAY 2  /* Safety delay after lock is detected */
+#define PLL_POST_LOCK_DELAY 50 /* Safety delay after lock is detected */
 #endif
 
 #define DIV_BUS                        (1 << 0)