Merge branch 'samsung/exynos5' into next/soc2
Arnd Bergmann [Thu, 15 Mar 2012 21:07:57 +0000 (21:07 +0000)]
257 files changed:
MAINTAINERS
Makefile
arch/arm/Makefile
arch/arm/boot/dts/exynos5250-smdk5250.dts [new file with mode: 0644]
arch/arm/boot/dts/exynos5250.dtsi [new file with mode: 0644]
arch/arm/mach-exynos/Kconfig
arch/arm/mach-exynos/Makefile
arch/arm/mach-exynos/clock-exynos4.c [new file with mode: 0644]
arch/arm/mach-exynos/clock-exynos4.h [new file with mode: 0644]
arch/arm/mach-exynos/clock-exynos4210.c
arch/arm/mach-exynos/clock-exynos4212.c
arch/arm/mach-exynos/clock-exynos5.c [new file with mode: 0644]
arch/arm/mach-exynos/clock.c [deleted file]
arch/arm/mach-exynos/common.c
arch/arm/mach-exynos/common.h
arch/arm/mach-exynos/dev-ahci.c
arch/arm/mach-exynos/dev-audio.c
arch/arm/mach-exynos/dev-uart.c [new file with mode: 0644]
arch/arm/mach-exynos/dma.c
arch/arm/mach-exynos/include/mach/debug-macro.S
arch/arm/mach-exynos/include/mach/exynos4-clock.h [deleted file]
arch/arm/mach-exynos/include/mach/irqs.h
arch/arm/mach-exynos/include/mach/map.h
arch/arm/mach-exynos/include/mach/regs-clock.h
arch/arm/mach-exynos/include/mach/regs-gpio.h
arch/arm/mach-exynos/include/mach/regs-pmu.h
arch/arm/mach-exynos/include/mach/uncompress.h
arch/arm/mach-exynos/mach-exynos4-dt.c
arch/arm/mach-exynos/mach-exynos5-dt.c [new file with mode: 0644]
arch/arm/mach-exynos/mach-origen.c
arch/arm/mach-exynos/mach-universal_c210.c
arch/arm/mach-exynos/mct.c
arch/arm/mach-exynos/platsmp.c
arch/arm/mach-exynos/pm.c
arch/arm/mach-exynos/setup-i2c0.c
arch/arm/mach-lpc32xx/include/mach/irqs.h
arch/arm/mach-lpc32xx/irq.c
arch/arm/mach-lpc32xx/serial.c
arch/arm/mach-mmp/aspenite.c
arch/arm/mach-mmp/pxa168.c
arch/arm/mach-mmp/tavorevb.c
arch/arm/mach-omap1/board-innovator.c
arch/arm/mach-omap2/Kconfig
arch/arm/mach-omap2/board-n8x0.c
arch/arm/mach-omap2/board-omap3evm.c
arch/arm/mach-omap2/common.h
arch/arm/mach-omap2/cpuidle44xx.c
arch/arm/mach-omap2/gpmc-smsc911x.c
arch/arm/mach-omap2/hsmmc.c
arch/arm/mach-omap2/io.c
arch/arm/mach-omap2/mailbox.c
arch/arm/mach-omap2/mux.c
arch/arm/mach-omap2/omap4-common.c
arch/arm/mach-omap2/pm.c
arch/arm/mach-omap2/usb-host.c
arch/arm/mach-pxa/hx4700.c
arch/arm/mach-pxa/pxa25x.c
arch/arm/mach-pxa/pxa27x.c
arch/arm/mach-pxa/saarb.c
arch/arm/mach-pxa/sharpsl_pm.c
arch/arm/mach-pxa/spitz_pm.c
arch/arm/mach-s3c2410/mach-h1940.c
arch/arm/mach-s3c2416/clock.c
arch/arm/mach-s3c2416/mach-smdk2416.c
arch/arm/mach-s3c2440/mach-gta02.c
arch/arm/mach-s3c2440/mach-rx1950.c
arch/arm/mach-s3c64xx/common.h
arch/arm/mach-s3c64xx/irq-pm.c
arch/arm/mach-s5p64x0/clock.c
arch/arm/mach-s5p64x0/dma.c
arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
arch/arm/mach-s5pc100/clock.c
arch/arm/mach-s5pc100/dma.c
arch/arm/mach-s5pv210/dma.c
arch/arm/mach-s5pv210/mach-goni.c
arch/arm/mach-s5pv210/mach-smdkv210.c
arch/arm/plat-omap/common.c
arch/arm/plat-omap/include/plat/omap-secure.h
arch/arm/plat-s3c24xx/s3c2443-clock.c
arch/arm/plat-s5p/Kconfig
arch/arm/plat-s5p/Makefile
arch/arm/plat-s5p/clock.c
arch/arm/plat-s5p/irq-eint.c
arch/arm/plat-s5p/irq-gpioint.c
arch/arm/plat-s5p/irq-pm.c
arch/arm/plat-samsung/devs.c
arch/arm/plat-samsung/dma-ops.c
arch/arm/plat-samsung/include/plat/cpu.h
arch/arm/plat-samsung/include/plat/devs.h
arch/arm/plat-samsung/include/plat/dma-pl330.h
arch/arm/plat-samsung/include/plat/s5p-clock.h
arch/arm/plat-samsung/include/plat/uncompress.h
arch/arm/plat-samsung/irq-vic-timer.c
arch/openrisc/include/asm/ptrace.h
arch/openrisc/kernel/init_task.c
arch/openrisc/kernel/irq.c
arch/openrisc/kernel/ptrace.c
arch/parisc/Makefile
arch/s390/Kconfig
arch/s390/include/asm/compat.h
arch/s390/kernel/crash_dump.c
arch/s390/kernel/process.c
arch/s390/kernel/ptrace.c
arch/s390/kernel/setup.c
arch/s390/kernel/signal.c
arch/s390/mm/fault.c
arch/s390/mm/init.c
arch/s390/mm/mmap.c
arch/x86/include/asm/perf_event.h
arch/x86/kernel/cpu/intel_cacheinfo.c
arch/x86/kernel/cpu/mcheck/mce_amd.c
arch/x86/kernel/cpu/perf_event.h
arch/x86/kernel/cpu/perf_event_amd.c
arch/x86/kernel/entry_64.S
arch/x86/kernel/microcode_amd.c
arch/x86/kvm/svm.c
arch/x86/xen/enlighten.c
arch/x86/xen/mmu.c
block/partitions/ldm.c
drivers/atm/solos-pci.c
drivers/bluetooth/btusb.c
drivers/crypto/mv_cesa.c
drivers/devfreq/exynos4_bus.c
drivers/gpu/drm/exynos/exynos_drm_connector.c
drivers/gpu/drm/exynos/exynos_drm_drv.h
drivers/gpu/drm/exynos/exynos_drm_fimd.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_ringbuffer.c
drivers/gpu/drm/radeon/r600_cs.c
drivers/gpu/drm/radeon/radeon_connectors.c
drivers/gpu/drm/radeon/radeon_gart.c
drivers/hwmon/f75375s.c
drivers/i2c/busses/i2c-mxs.c
drivers/iommu/omap-iommu-debug.c
drivers/iommu/omap-iommu.c
drivers/net/can/sja1000/sja1000.c
drivers/net/ethernet/atheros/atl1c/atl1c_main.c
drivers/net/ethernet/broadcom/b44.c
drivers/net/ethernet/broadcom/cnic.c
drivers/net/ethernet/cisco/enic/cq_enet_desc.h
drivers/net/ethernet/cisco/enic/enic_pp.c
drivers/net/ethernet/jme.c
drivers/net/ethernet/jme.h
drivers/net/ethernet/mellanox/mlx4/eq.c
drivers/net/ethernet/mellanox/mlx4/main.c
drivers/net/ethernet/mellanox/mlx4/mlx4.h
drivers/net/ethernet/micrel/ks8851_mll.c
drivers/net/ethernet/sfc/rx.c
drivers/net/ethernet/ti/davinci_emac.c
drivers/net/phy/icplus.c
drivers/net/ppp/ppp_generic.c
drivers/net/usb/cdc_ether.c
drivers/net/usb/hso.c
drivers/net/usb/zaurus.c
drivers/net/vmxnet3/vmxnet3_drv.c
drivers/net/wireless/ath/ath9k/rc.c
drivers/net/wireless/mwifiex/cfg80211.c
drivers/parisc/iommu-helpers.h
drivers/pcmcia/pxa2xx_base.c
drivers/regulator/88pm8607.c
drivers/s390/block/dasd_eckd.c
drivers/s390/block/dasd_ioctl.c
drivers/s390/char/fs3270.c
drivers/s390/char/vmcp.c
drivers/s390/cio/chsc_sch.c
drivers/s390/scsi/zfcp_cfdc.c
drivers/scsi/osd/osd_uld.c
drivers/video/omap2/displays/Kconfig
drivers/video/omap2/dss/apply.c
drivers/video/omap2/dss/hdmi.c
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
drivers/video/via/hw.c
drivers/virtio/virtio_balloon.c
drivers/watchdog/Kconfig
drivers/watchdog/booke_wdt.c
drivers/watchdog/hpwdt.c
drivers/watchdog/pnx4008_wdt.c
drivers/watchdog/s3c2410_wdt.c
fs/binfmt_elf.c
fs/dcache.c
fs/ecryptfs/miscdev.c
fs/gfs2/glock.c
fs/gfs2/inode.c
fs/gfs2/ops_fstype.c
fs/gfs2/rgrp.c
fs/namei.c
fs/ntfs/attrib.c
fs/ntfs/mft.c
fs/ntfs/super.c
include/asm-generic/iomap.h
include/asm-generic/pci_iomap.h
include/drm/Kbuild
include/drm/exynos_drm.h
include/linux/compat.h
include/linux/dcache.h
include/linux/if_link.h
include/linux/netfilter_bridge/ebtables.h
include/linux/regset.h
include/linux/rtnetlink.h
include/linux/skbuff.h
include/net/bluetooth/bluetooth.h
include/net/bluetooth/hci_core.h
include/net/bluetooth/l2cap.h
include/net/netfilter/nf_conntrack.h
include/net/rtnetlink.h
include/trace/events/sched.h
kernel/events/hw_breakpoint.c
kernel/irq/autoprobe.c
kernel/irq/chip.c
kernel/irq/internals.h
kernel/irq/manage.c
kernel/sched/core.c
kernel/sched/fair.c
mm/memblock.c
net/atm/clip.c
net/bluetooth/af_bluetooth.c
net/bluetooth/hci_conn.c
net/bluetooth/hci_core.c
net/bluetooth/l2cap_core.c
net/bluetooth/l2cap_sock.c
net/bluetooth/rfcomm/core.c
net/bluetooth/rfcomm/sock.c
net/core/neighbour.c
net/core/rtnetlink.c
net/ipv4/ip_gre.c
net/ipv4/ping.c
net/ipv4/xfrm4_mode_beet.c
net/ipv4/xfrm4_mode_tunnel.c
net/ipv6/ip6mr.c
net/ipv6/ndisc.c
net/ipv6/xfrm6_mode_beet.c
net/ipv6/xfrm6_mode_tunnel.c
net/mac80211/debugfs_sta.c
net/mac80211/rate.c
net/mac80211/rate.h
net/mac80211/sta_info.h
net/netfilter/ipvs/ip_vs_core.c
net/netfilter/nf_conntrack_core.c
net/netfilter/nf_conntrack_netlink.c
net/netfilter/nf_queue.c
net/netfilter/xt_TEE.c
net/sched/sch_netem.c
scripts/mod/file2alias.c
sound/pci/azt3328.c
sound/pci/hda/hda_codec.c
sound/pci/hda/hda_codec.h
sound/pci/hda/patch_cirrus.c
sound/pci/hda/patch_conexant.c
sound/pci/hda/patch_realtek.c
sound/pci/hda/patch_sigmatel.c
sound/soc/imx/imx-ssi.c
sound/soc/soc-dapm.c
tools/perf/util/event.c
tools/perf/util/evlist.c
tools/perf/util/probe-event.c
tools/perf/util/probe-finder.c
tools/testing/ktest/ktest.pl

index 75a9a5f..4e41d52 100644 (file)
@@ -3780,7 +3780,7 @@ F:        Documentation/kdump/
 
 KERNEL AUTOMOUNTER v4 (AUTOFS4)
 M:     Ian Kent <raven@themaw.net>
-L:     autofs@linux.kernel.org
+L:     autofs@vger.kernel.org
 S:     Maintained
 F:     fs/autofs4/
 
@@ -4685,7 +4685,7 @@ NTFS FILESYSTEM
 M:     Anton Altaparmakov <anton@tuxera.com>
 L:     linux-ntfs-dev@lists.sourceforge.net
 W:     http://www.tuxera.com/
-T:     git git://git.kernel.org/pub/scm/linux/kernel/git/aia21/ntfs-2.6.git
+T:     git git://git.kernel.org/pub/scm/linux/kernel/git/aia21/ntfs.git
 S:     Supported
 F:     Documentation/filesystems/ntfs.txt
 F:     fs/ntfs/
@@ -7271,7 +7271,7 @@ WATCHDOG DEVICE DRIVERS
 M:     Wim Van Sebroeck <wim@iguana.be>
 L:     linux-watchdog@vger.kernel.org
 W:     http://www.linux-watchdog.org/
-T:     git git://git.kernel.org/pub/scm/linux/kernel/git/wim/linux-2.6-watchdog.git
+T:     git git://www.linux-watchdog.org/linux-watchdog.git
 S:     Maintained
 F:     Documentation/watchdog/
 F:     drivers/watchdog/
index b61a963..66d13c9 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 3
 PATCHLEVEL = 3
 SUBLEVEL = 0
-EXTRAVERSION = -rc5
+EXTRAVERSION = -rc6
 NAME = Saber-toothed Squirrel
 
 # *DOCUMENTATION*
index 1683bfb..a826ffc 100644 (file)
@@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_S5P64X0)              := s5p64x0
 machine-$(CONFIG_ARCH_S5PC100)         := s5pc100
 machine-$(CONFIG_ARCH_S5PV210)         := s5pv210
 machine-$(CONFIG_ARCH_EXYNOS4)         := exynos
+machine-$(CONFIG_ARCH_EXYNOS5)         := exynos
 machine-$(CONFIG_ARCH_SA1100)          := sa1100
 machine-$(CONFIG_ARCH_SHARK)           := shark
 machine-$(CONFIG_ARCH_SHMOBILE)        := shmobile
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
new file mode 100644 (file)
index 0000000..399d17b
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * SAMSUNG SMDK5250 board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5250.dtsi"
+
+/ {
+       model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
+       compatible = "samsung,smdk5250", "samsung,exynos5250";
+
+       memory {
+               reg = <0x40000000 0x80000000>;
+       };
+
+       chosen {
+               bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
+       };
+};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
new file mode 100644 (file)
index 0000000..dfc4335
--- /dev/null
@@ -0,0 +1,413 @@
+/*
+ * SAMSUNG EXYNOS5250 SoC device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
+ * EXYNOS5250 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
+ * additional nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "skeleton.dtsi"
+
+/ {
+       compatible = "samsung,exynos5250";
+       interrupt-parent = <&gic>;
+
+       gic:interrupt-controller@10490000 {
+               compatible = "arm,cortex-a9-gic";
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+       };
+
+       watchdog {
+               compatible = "samsung,s3c2410-wdt";
+               reg = <0x101D0000 0x100>;
+               interrupts = <0 42 0>;
+       };
+
+       rtc {
+               compatible = "samsung,s3c6410-rtc";
+               reg = <0x101E0000 0x100>;
+               interrupts = <0 43 0>, <0 44 0>;
+       };
+
+       sdhci@12200000 {
+               compatible = "samsung,exynos4210-sdhci";
+               reg = <0x12200000 0x100>;
+               interrupts = <0 75 0>;
+       };
+
+       sdhci@12210000 {
+               compatible = "samsung,exynos4210-sdhci";
+               reg = <0x12210000 0x100>;
+               interrupts = <0 76 0>;
+       };
+
+       sdhci@12220000 {
+               compatible = "samsung,exynos4210-sdhci";
+               reg = <0x12220000 0x100>;
+               interrupts = <0 77 0>;
+       };
+
+       sdhci@12230000 {
+               compatible = "samsung,exynos4210-sdhci";
+               reg = <0x12230000 0x100>;
+               interrupts = <0 78 0>;
+       };
+
+       serial@12C00000 {
+               compatible = "samsung,exynos4210-uart";
+               reg = <0x12C00000 0x100>;
+               interrupts = <0 51 0>;
+       };
+
+       serial@12C10000 {
+               compatible = "samsung,exynos4210-uart";
+               reg = <0x12C10000 0x100>;
+               interrupts = <0 52 0>;
+       };
+
+       serial@12C20000 {
+               compatible = "samsung,exynos4210-uart";
+               reg = <0x12C20000 0x100>;
+               interrupts = <0 53 0>;
+       };
+
+       serial@12C30000 {
+               compatible = "samsung,exynos4210-uart";
+               reg = <0x12C30000 0x100>;
+               interrupts = <0 54 0>;
+       };
+
+       i2c@12C60000 {
+               compatible = "samsung,s3c2440-i2c";
+               reg = <0x12C60000 0x100>;
+               interrupts = <0 56 0>;
+       };
+
+       i2c@12C70000 {
+               compatible = "samsung,s3c2440-i2c";
+               reg = <0x12C70000 0x100>;
+               interrupts = <0 57 0>;
+       };
+
+       i2c@12C80000 {
+               compatible = "samsung,s3c2440-i2c";
+               reg = <0x12C80000 0x100>;
+               interrupts = <0 58 0>;
+       };
+
+       i2c@12C90000 {
+               compatible = "samsung,s3c2440-i2c";
+               reg = <0x12C90000 0x100>;
+               interrupts = <0 59 0>;
+       };
+
+       i2c@12CA0000 {
+               compatible = "samsung,s3c2440-i2c";
+               reg = <0x12CA0000 0x100>;
+               interrupts = <0 60 0>;
+       };
+
+       i2c@12CB0000 {
+               compatible = "samsung,s3c2440-i2c";
+               reg = <0x12CB0000 0x100>;
+               interrupts = <0 61 0>;
+       };
+
+       i2c@12CC0000 {
+               compatible = "samsung,s3c2440-i2c";
+               reg = <0x12CC0000 0x100>;
+               interrupts = <0 62 0>;
+       };
+
+       i2c@12CD0000 {
+               compatible = "samsung,s3c2440-i2c";
+               reg = <0x12CD0000 0x100>;
+               interrupts = <0 63 0>;
+       };
+
+       amba {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "arm,amba-bus";
+               interrupt-parent = <&gic>;
+               ranges;
+
+               pdma0: pdma@121A0000 {
+                       compatible = "arm,pl330", "arm,primecell";
+                       reg = <0x121A0000 0x1000>;
+                       interrupts = <0 34 0>;
+               };
+
+               pdma1: pdma@121B0000 {
+                       compatible = "arm,pl330", "arm,primecell";
+                       reg = <0x121B0000 0x1000>;
+                       interrupts = <0 35 0>;
+               };
+
+               mdma0: pdma@10800000 {
+                       compatible = "arm,pl330", "arm,primecell";
+                       reg = <0x10800000 0x1000>;
+                       interrupts = <0 33 0>;
+               };
+
+               mdma1: pdma@11C10000 {
+                       compatible = "arm,pl330", "arm,primecell";
+                       reg = <0x11C10000 0x1000>;
+                       interrupts = <0 124 0>;
+               };
+       };
+
+       gpio-controllers {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               gpio-controller;
+               ranges;
+
+               gpa0: gpio-controller@11400000 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400000 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpa1: gpio-controller@11400020 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400020 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpa2: gpio-controller@11400040 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400040 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpb0: gpio-controller@11400060 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400060 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpb1: gpio-controller@11400080 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400080 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpb2: gpio-controller@114000A0 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x114000A0 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpb3: gpio-controller@114000C0 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x114000C0 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpc0: gpio-controller@114000E0 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x114000E0 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpc1: gpio-controller@11400100 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400100 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpc2: gpio-controller@11400120 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400120 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpc3: gpio-controller@11400140 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400140 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpd0: gpio-controller@11400160 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400160 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpd1: gpio-controller@11400180 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400180 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpy0: gpio-controller@114001A0 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x114001A0 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpy1: gpio-controller@114001C0 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x114001C0 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpy2: gpio-controller@114001E0 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x114001E0 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpy3: gpio-controller@11400200 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400200 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpy4: gpio-controller@11400220 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400220 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpy5: gpio-controller@11400240 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400240 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpy6: gpio-controller@11400260 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400260 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpx0: gpio-controller@11400C00 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400C00 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpx1: gpio-controller@11400C20 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400C20 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpx2: gpio-controller@11400C40 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400C40 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpx3: gpio-controller@11400C60 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x11400C60 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpe0: gpio-controller@13400000 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x13400000 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpe1: gpio-controller@13400020 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x13400020 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpf0: gpio-controller@13400040 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x13400040 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpf1: gpio-controller@13400060 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x13400060 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpg0: gpio-controller@13400080 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x13400080 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpg1: gpio-controller@134000A0 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x134000A0 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpg2: gpio-controller@134000C0 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x134000C0 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gph0: gpio-controller@134000E0 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x134000E0 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gph1: gpio-controller@13400100 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x13400100 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpv0: gpio-controller@10D10000 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x10D10000 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpv1: gpio-controller@10D10020 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x10D10020 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpv2: gpio-controller@10D10040 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x10D10040 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpv3: gpio-controller@10D10060 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x10D10060 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpv4: gpio-controller@10D10080 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x10D10080 0x20>;
+                       #gpio-cells = <4>;
+               };
+
+               gpz: gpio-controller@03860000 {
+                       compatible = "samsung,exynos4-gpio";
+                       reg = <0x03860000 0x20>;
+                       #gpio-cells = <4>;
+               };
+       };
+};
index 5d602f6..42f072d 100644 (file)
@@ -11,18 +11,19 @@ if ARCH_EXYNOS
 
 menu "SAMSUNG EXYNOS SoCs Support"
 
-choice
-       prompt "EXYNOS System Type"
-       default ARCH_EXYNOS4
-
 config ARCH_EXYNOS4
        bool "SAMSUNG EXYNOS4"
+       default y
        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
        help
          Samsung EXYNOS4 SoCs based systems
 
-endchoice
+config ARCH_EXYNOS5
+       bool "SAMSUNG EXYNOS5"
+       select HAVE_SMP
+       help
+         Samsung EXYNOS5 (Cortex-A15) SoC based systems
 
 comment "EXYNOS SoCs"
 
@@ -41,6 +42,7 @@ config SOC_EXYNOS4212
        bool "SAMSUNG EXYNOS4212"
        default y
        depends on ARCH_EXYNOS4
+       select SAMSUNG_DMADEV
        select S5P_PM if PM
        select S5P_SLEEP if PM
        help
@@ -50,9 +52,17 @@ config SOC_EXYNOS4412
        bool "SAMSUNG EXYNOS4412"
        default y
        depends on ARCH_EXYNOS4
+       select SAMSUNG_DMADEV
        help
          Enable EXYNOS4412 SoC support
 
+config SOC_EXYNOS5250
+       bool "SAMSUNG EXYNOS5250"
+       default y
+       depends on ARCH_EXYNOS5
+       help
+         Enable EXYNOS5250 SoC support
+
 config EXYNOS4_MCT
        bool
        default y
@@ -333,6 +343,7 @@ config MACH_SMDK4212
        select SAMSUNG_DEV_BACKLIGHT
        select SAMSUNG_DEV_KEYPAD
        select SAMSUNG_DEV_PWM
+       select EXYNOS4_DEV_DMA
        select EXYNOS4_SETUP_I2C1
        select EXYNOS4_SETUP_I2C3
        select EXYNOS4_SETUP_I2C7
@@ -351,7 +362,7 @@ config MACH_SMDK4412
          Machine support for Samsung SMDK4412
 endif
 
-comment "Flattened Device Tree based board for Exynos4 based SoC"
+comment "Flattened Device Tree based board for EXYNOS SoCs"
 
 config MACH_EXYNOS4_DT
        bool "Samsung Exynos4 Machine using device tree"
@@ -365,6 +376,15 @@ config MACH_EXYNOS4_DT
          Note: This is under development and not all peripherals can be supported
          with this machine file.
 
+config MACH_EXYNOS5_DT
+       bool "SAMSUNG EXYNOS5 Machine using device tree"
+       select SOC_EXYNOS5250
+       select USE_OF
+       select ARM_AMBA
+       help
+         Machine support for Samsung Exynos4 machine with device tree enabled.
+         Select this if a fdt blob is available for the EXYNOS4 SoC based board.
+
 if ARCH_EXYNOS4
 
 comment "Configuration for HSMMC 8-bit bus width"
index 5fc202c..29967ef 100644 (file)
@@ -12,7 +12,9 @@ obj-                          :=
 
 # Core
 
-obj-$(CONFIG_ARCH_EXYNOS4)     += common.o clock.o
+obj-$(CONFIG_ARCH_EXYNOS)      += common.o
+obj-$(CONFIG_ARCH_EXYNOS4)     += clock-exynos4.o
+obj-$(CONFIG_ARCH_EXYNOS5)     += clock-exynos5.o
 obj-$(CONFIG_CPU_EXYNOS4210)   += clock-exynos4210.o
 obj-$(CONFIG_SOC_EXYNOS4212)   += clock-exynos4212.o
 
@@ -40,9 +42,11 @@ obj-$(CONFIG_MACH_SMDK4212)          += mach-smdk4x12.o
 obj-$(CONFIG_MACH_SMDK4412)            += mach-smdk4x12.o
 
 obj-$(CONFIG_MACH_EXYNOS4_DT)          += mach-exynos4-dt.o
+obj-$(CONFIG_MACH_EXYNOS5_DT)          += mach-exynos5-dt.o
 
 # device support
 
+obj-y                                  += dev-uart.o
 obj-$(CONFIG_ARCH_EXYNOS4)             += dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)         += dev-ahci.o
 obj-$(CONFIG_EXYNOS4_DEV_PD)           += dev-pd.o
@@ -51,7 +55,7 @@ obj-$(CONFIG_EXYNOS4_DEV_DWMCI)               += dev-dwmci.o
 obj-$(CONFIG_EXYNOS4_DEV_DMA)          += dma.o
 obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)     += dev-ohci.o
 
-obj-$(CONFIG_ARCH_EXYNOS4)             += setup-i2c0.o
+obj-$(CONFIG_ARCH_EXYNOS)              += setup-i2c0.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMC)       += setup-fimc.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMD0)      += setup-fimd0.o
 obj-$(CONFIG_EXYNOS4_SETUP_I2C1)       += setup-i2c1.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
new file mode 100644 (file)
index 0000000..6504d8b
--- /dev/null
@@ -0,0 +1,1576 @@
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * EXYNOS4 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/pm.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
+
+#include "common.h"
+#include "clock-exynos4.h"
+
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos4_clock_save[] = {
+       SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
+       SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
+       SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
+       SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
+       SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
+       SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
+       SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
+       SAVE_ITEM(EXYNOS4_CLKSRC_TV),
+       SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
+       SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
+       SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
+       SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
+       SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
+       SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
+       SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
+       SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
+       SAVE_ITEM(EXYNOS4_CLKDIV_TV),
+       SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
+       SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
+       SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
+       SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
+       SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
+       SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
+       SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
+       SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
+       SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
+       SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
+       SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
+       SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
+       SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
+       SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
+       SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
+       SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
+       SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
+       SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
+       SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
+       SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
+       SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
+       SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
+       SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
+       SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
+       SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
+       SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
+       SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
+       SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
+       SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
+       SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
+       SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
+       SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
+       SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
+       SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
+       SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
+       SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
+       SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
+       SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
+       SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
+       SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
+       SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
+       SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
+       SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
+       SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
+};
+#endif
+
+static struct clk exynos4_clk_sclk_hdmi27m = {
+       .name           = "sclk_hdmi27m",
+       .rate           = 27000000,
+};
+
+static struct clk exynos4_clk_sclk_hdmiphy = {
+       .name           = "sclk_hdmiphy",
+};
+
+static struct clk exynos4_clk_sclk_usbphy0 = {
+       .name           = "sclk_usbphy0",
+       .rate           = 27000000,
+};
+
+static struct clk exynos4_clk_sclk_usbphy1 = {
+       .name           = "sclk_usbphy1",
+};
+
+static struct clk dummy_apb_pclk = {
+       .name           = "apb_pclk",
+       .id             = -1,
+};
+
+static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
+}
+
+static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
+}
+
+int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
+}
+
+static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
+}
+
+static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
+}
+
+static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
+}
+
+static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
+}
+
+static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
+}
+
+static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
+}
+
+static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
+}
+
+int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
+}
+
+int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
+}
+
+static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
+}
+
+static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
+}
+
+static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
+static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
+}
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk exynos4_clk_mout_apll = {
+       .clk    = {
+               .name           = "mout_apll",
+       },
+       .sources = &clk_src_apll,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_apll = {
+       .clk    = {
+               .name           = "sclk_apll",
+               .parent         = &exynos4_clk_mout_apll.clk,
+       },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_mout_epll = {
+       .clk    = {
+               .name           = "mout_epll",
+       },
+       .sources = &clk_src_epll,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
+};
+
+struct clksrc_clk exynos4_clk_mout_mpll = {
+       .clk    = {
+               .name           = "mout_mpll",
+       },
+       .sources = &clk_src_mpll,
+
+       /* reg_src will be added in each SoCs' clock */
+};
+
+static struct clk *exynos4_clkset_moutcore_list[] = {
+       [0] = &exynos4_clk_mout_apll.clk,
+       [1] = &exynos4_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_moutcore = {
+       .sources        = exynos4_clkset_moutcore_list,
+       .nr_sources     = ARRAY_SIZE(exynos4_clkset_moutcore_list),
+};
+
+static struct clksrc_clk exynos4_clk_moutcore = {
+       .clk    = {
+               .name           = "moutcore",
+       },
+       .sources = &exynos4_clkset_moutcore,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_coreclk = {
+       .clk    = {
+               .name           = "core_clk",
+               .parent         = &exynos4_clk_moutcore.clk,
+       },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_armclk = {
+       .clk    = {
+               .name           = "armclk",
+               .parent         = &exynos4_clk_coreclk.clk,
+       },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corem0 = {
+       .clk    = {
+               .name           = "aclk_corem0",
+               .parent         = &exynos4_clk_coreclk.clk,
+       },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_cores = {
+       .clk    = {
+               .name           = "aclk_cores",
+               .parent         = &exynos4_clk_coreclk.clk,
+       },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corem1 = {
+       .clk    = {
+               .name           = "aclk_corem1",
+               .parent         = &exynos4_clk_coreclk.clk,
+       },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_periphclk = {
+       .clk    = {
+               .name           = "periphclk",
+               .parent         = &exynos4_clk_coreclk.clk,
+       },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
+};
+
+/* Core list of CMU_CORE side */
+
+static struct clk *exynos4_clkset_corebus_list[] = {
+       [0] = &exynos4_clk_mout_mpll.clk,
+       [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+struct clksrc_sources exynos4_clkset_mout_corebus = {
+       .sources        = exynos4_clkset_corebus_list,
+       .nr_sources     = ARRAY_SIZE(exynos4_clkset_corebus_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_corebus = {
+       .clk    = {
+               .name           = "mout_corebus",
+       },
+       .sources = &exynos4_clkset_mout_corebus,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_dmc = {
+       .clk    = {
+               .name           = "sclk_dmc",
+               .parent         = &exynos4_clk_mout_corebus.clk,
+       },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_cored = {
+       .clk    = {
+               .name           = "aclk_cored",
+               .parent         = &exynos4_clk_sclk_dmc.clk,
+       },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corep = {
+       .clk    = {
+               .name           = "aclk_corep",
+               .parent         = &exynos4_clk_aclk_cored.clk,
+       },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_acp = {
+       .clk    = {
+               .name           = "aclk_acp",
+               .parent         = &exynos4_clk_mout_corebus.clk,
+       },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_pclk_acp = {
+       .clk    = {
+               .name           = "pclk_acp",
+               .parent         = &exynos4_clk_aclk_acp.clk,
+       },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
+};
+
+/* Core list of CMU_TOP side */
+
+struct clk *exynos4_clkset_aclk_top_list[] = {
+       [0] = &exynos4_clk_mout_mpll.clk,
+       [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_aclk = {
+       .sources        = exynos4_clkset_aclk_top_list,
+       .nr_sources     = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
+};
+
+static struct clksrc_clk exynos4_clk_aclk_200 = {
+       .clk    = {
+               .name           = "aclk_200",
+       },
+       .sources = &exynos4_clkset_aclk,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_100 = {
+       .clk    = {
+               .name           = "aclk_100",
+       },
+       .sources = &exynos4_clkset_aclk,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_160 = {
+       .clk    = {
+               .name           = "aclk_160",
+       },
+       .sources = &exynos4_clkset_aclk,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
+};
+
+struct clksrc_clk exynos4_clk_aclk_133 = {
+       .clk    = {
+               .name           = "aclk_133",
+       },
+       .sources = &exynos4_clkset_aclk,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
+};
+
+static struct clk *exynos4_clkset_vpllsrc_list[] = {
+       [0] = &clk_fin_vpll,
+       [1] = &exynos4_clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources exynos4_clkset_vpllsrc = {
+       .sources        = exynos4_clkset_vpllsrc_list,
+       .nr_sources     = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
+};
+
+static struct clksrc_clk exynos4_clk_vpllsrc = {
+       .clk    = {
+               .name           = "vpll_src",
+               .enable         = exynos4_clksrc_mask_top_ctrl,
+               .ctrlbit        = (1 << 0),
+       },
+       .sources = &exynos4_clkset_vpllsrc,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_sclk_vpll_list[] = {
+       [0] = &exynos4_clk_vpllsrc.clk,
+       [1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_vpll = {
+       .sources        = exynos4_clkset_sclk_vpll_list,
+       .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_vpll = {
+       .clk    = {
+               .name           = "sclk_vpll",
+       },
+       .sources = &exynos4_clkset_sclk_vpll,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
+};
+
+static struct clk exynos4_init_clocks_off[] = {
+       {
+               .name           = "timers",
+               .parent         = &exynos4_clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1<<24),
+       }, {
+               .name           = "csis",
+               .devname        = "s5p-mipi-csis.0",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 4),
+       }, {
+               .name           = "csis",
+               .devname        = "s5p-mipi-csis.1",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 5),
+       }, {
+               .name           = "fimc",
+               .devname        = "exynos4-fimc.0",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "fimc",
+               .devname        = "exynos4-fimc.1",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 1),
+       }, {
+               .name           = "fimc",
+               .devname        = "exynos4-fimc.2",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 2),
+       }, {
+               .name           = "fimc",
+               .devname        = "exynos4-fimc.3",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 3),
+       }, {
+               .name           = "hsmmc",
+               .devname        = "s3c-sdhci.0",
+               .parent         = &exynos4_clk_aclk_133.clk,
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 5),
+       }, {
+               .name           = "hsmmc",
+               .devname        = "s3c-sdhci.1",
+               .parent         = &exynos4_clk_aclk_133.clk,
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 6),
+       }, {
+               .name           = "hsmmc",
+               .devname        = "s3c-sdhci.2",
+               .parent         = &exynos4_clk_aclk_133.clk,
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 7),
+       }, {
+               .name           = "hsmmc",
+               .devname        = "s3c-sdhci.3",
+               .parent         = &exynos4_clk_aclk_133.clk,
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 8),
+       }, {
+               .name           = "dwmmc",
+               .parent         = &exynos4_clk_aclk_133.clk,
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 9),
+       }, {
+               .name           = "dac",
+               .devname        = "s5p-sdo",
+               .enable         = exynos4_clk_ip_tv_ctrl,
+               .ctrlbit        = (1 << 2),
+       }, {
+               .name           = "mixer",
+               .devname        = "s5p-mixer",
+               .enable         = exynos4_clk_ip_tv_ctrl,
+               .ctrlbit        = (1 << 1),
+       }, {
+               .name           = "vp",
+               .devname        = "s5p-mixer",
+               .enable         = exynos4_clk_ip_tv_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "hdmi",
+               .devname        = "exynos4-hdmi",
+               .enable         = exynos4_clk_ip_tv_ctrl,
+               .ctrlbit        = (1 << 3),
+       }, {
+               .name           = "hdmiphy",
+               .devname        = "exynos4-hdmi",
+               .enable         = exynos4_clk_hdmiphy_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "dacphy",
+               .devname        = "s5p-sdo",
+               .enable         = exynos4_clk_dac_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "adc",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 15),
+       }, {
+               .name           = "keypad",
+               .enable         = exynos4_clk_ip_perir_ctrl,
+               .ctrlbit        = (1 << 16),
+       }, {
+               .name           = "rtc",
+               .enable         = exynos4_clk_ip_perir_ctrl,
+               .ctrlbit        = (1 << 15),
+       }, {
+               .name           = "watchdog",
+               .parent         = &exynos4_clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_perir_ctrl,
+               .ctrlbit        = (1 << 14),
+       }, {
+               .name           = "usbhost",
+               .enable         = exynos4_clk_ip_fsys_ctrl ,
+               .ctrlbit        = (1 << 12),
+       }, {
+               .name           = "otg",
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 13),
+       }, {
+               .name           = "spi",
+               .devname        = "s3c64xx-spi.0",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 16),
+       }, {
+               .name           = "spi",
+               .devname        = "s3c64xx-spi.1",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 17),
+       }, {
+               .name           = "spi",
+               .devname        = "s3c64xx-spi.2",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 18),
+       }, {
+               .name           = "iis",
+               .devname        = "samsung-i2s.0",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 19),
+       }, {
+               .name           = "iis",
+               .devname        = "samsung-i2s.1",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 20),
+       }, {
+               .name           = "iis",
+               .devname        = "samsung-i2s.2",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 21),
+       }, {
+               .name           = "ac97",
+               .devname        = "samsung-ac97",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 27),
+       }, {
+               .name           = "fimg2d",
+               .enable         = exynos4_clk_ip_image_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "mfc",
+               .devname        = "s5p-mfc",
+               .enable         = exynos4_clk_ip_mfc_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.0",
+               .parent         = &exynos4_clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 6),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.1",
+               .parent         = &exynos4_clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 7),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.2",
+               .parent         = &exynos4_clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 8),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.3",
+               .parent         = &exynos4_clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 9),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.4",
+               .parent         = &exynos4_clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 10),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.5",
+               .parent         = &exynos4_clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 11),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.6",
+               .parent         = &exynos4_clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 12),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.7",
+               .parent         = &exynos4_clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 13),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-hdmiphy-i2c",
+               .parent         = &exynos4_clk_aclk_100.clk,
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 14),
+       }, {
+               .name           = "SYSMMU_MDMA",
+               .enable         = exynos4_clk_ip_image_ctrl,
+               .ctrlbit        = (1 << 5),
+       }, {
+               .name           = "SYSMMU_FIMC0",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 7),
+       }, {
+               .name           = "SYSMMU_FIMC1",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 8),
+       }, {
+               .name           = "SYSMMU_FIMC2",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 9),
+       }, {
+               .name           = "SYSMMU_FIMC3",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 10),
+       }, {
+               .name           = "SYSMMU_JPEG",
+               .enable         = exynos4_clk_ip_cam_ctrl,
+               .ctrlbit        = (1 << 11),
+       }, {
+               .name           = "SYSMMU_FIMD0",
+               .enable         = exynos4_clk_ip_lcd0_ctrl,
+               .ctrlbit        = (1 << 4),
+       }, {
+               .name           = "SYSMMU_FIMD1",
+               .enable         = exynos4_clk_ip_lcd1_ctrl,
+               .ctrlbit        = (1 << 4),
+       }, {
+               .name           = "SYSMMU_PCIe",
+               .enable         = exynos4_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 18),
+       }, {
+               .name           = "SYSMMU_G2D",
+               .enable         = exynos4_clk_ip_image_ctrl,
+               .ctrlbit        = (1 << 3),
+       }, {
+               .name           = "SYSMMU_ROTATOR",
+               .enable         = exynos4_clk_ip_image_ctrl,
+               .ctrlbit        = (1 << 4),
+       }, {
+               .name           = "SYSMMU_TV",
+               .enable         = exynos4_clk_ip_tv_ctrl,
+               .ctrlbit        = (1 << 4),
+       }, {
+               .name           = "SYSMMU_MFC_L",
+               .enable         = exynos4_clk_ip_mfc_ctrl,
+               .ctrlbit        = (1 << 1),
+       }, {
+               .name           = "SYSMMU_MFC_R",
+               .enable         = exynos4_clk_ip_mfc_ctrl,
+               .ctrlbit        = (1 << 2),
+       }
+};
+
+static struct clk exynos4_init_clocks_on[] = {
+       {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.0",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.1",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 1),
+       }, {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.2",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 2),
+       }, {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.3",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 3),
+       }, {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.4",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 4),
+       }, {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.5",
+               .enable         = exynos4_clk_ip_peril_ctrl,
+               .ctrlbit        = (1 << 5),
+       }
+};
+
+static struct clk exynos4_clk_pdma0 = {
+       .name           = "dma",
+       .devname        = "dma-pl330.0",
+       .enable         = exynos4_clk_ip_fsys_ctrl,
+       .ctrlbit        = (1 << 0),
+};
+
+static struct clk exynos4_clk_pdma1 = {
+       .name           = "dma",
+       .devname        = "dma-pl330.1",
+       .enable         = exynos4_clk_ip_fsys_ctrl,
+       .ctrlbit        = (1 << 1),
+};
+
+static struct clk exynos4_clk_mdma1 = {
+       .name           = "dma",
+       .devname        = "dma-pl330.2",
+       .enable         = exynos4_clk_ip_image_ctrl,
+       .ctrlbit        = ((1 << 8) | (1 << 5) | (1 << 2)),
+};
+
+static struct clk exynos4_clk_fimd0 = {
+       .name           = "fimd",
+       .devname        = "exynos4-fb.0",
+       .enable         = exynos4_clk_ip_lcd0_ctrl,
+       .ctrlbit        = (1 << 0),
+};
+
+struct clk *exynos4_clkset_group_list[] = {
+       [0] = &clk_ext_xtal_mux,
+       [1] = &clk_xusbxti,
+       [2] = &exynos4_clk_sclk_hdmi27m,
+       [3] = &exynos4_clk_sclk_usbphy0,
+       [4] = &exynos4_clk_sclk_usbphy1,
+       [5] = &exynos4_clk_sclk_hdmiphy,
+       [6] = &exynos4_clk_mout_mpll.clk,
+       [7] = &exynos4_clk_mout_epll.clk,
+       [8] = &exynos4_clk_sclk_vpll.clk,
+};
+
+struct clksrc_sources exynos4_clkset_group = {
+       .sources        = exynos4_clkset_group_list,
+       .nr_sources     = ARRAY_SIZE(exynos4_clkset_group_list),
+};
+
+static struct clk *exynos4_clkset_mout_g2d0_list[] = {
+       [0] = &exynos4_clk_mout_mpll.clk,
+       [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
+       .sources        = exynos4_clkset_mout_g2d0_list,
+       .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_g2d0 = {
+       .clk    = {
+               .name           = "mout_g2d0",
+       },
+       .sources = &exynos4_clkset_mout_g2d0,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_g2d1_list[] = {
+       [0] = &exynos4_clk_mout_epll.clk,
+       [1] = &exynos4_clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
+       .sources        = exynos4_clkset_mout_g2d1_list,
+       .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_g2d1 = {
+       .clk    = {
+               .name           = "mout_g2d1",
+       },
+       .sources = &exynos4_clkset_mout_g2d1,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_g2d_list[] = {
+       [0] = &exynos4_clk_mout_g2d0.clk,
+       [1] = &exynos4_clk_mout_g2d1.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g2d = {
+       .sources        = exynos4_clkset_mout_g2d_list,
+       .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
+};
+
+static struct clk *exynos4_clkset_mout_mfc0_list[] = {
+       [0] = &exynos4_clk_mout_mpll.clk,
+       [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
+       .sources        = exynos4_clkset_mout_mfc0_list,
+       .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_mfc0 = {
+       .clk    = {
+               .name           = "mout_mfc0",
+       },
+       .sources = &exynos4_clkset_mout_mfc0,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_mfc1_list[] = {
+       [0] = &exynos4_clk_mout_epll.clk,
+       [1] = &exynos4_clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
+       .sources        = exynos4_clkset_mout_mfc1_list,
+       .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_mfc1 = {
+       .clk    = {
+               .name           = "mout_mfc1",
+       },
+       .sources = &exynos4_clkset_mout_mfc1,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_mfc_list[] = {
+       [0] = &exynos4_clk_mout_mfc0.clk,
+       [1] = &exynos4_clk_mout_mfc1.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc = {
+       .sources        = exynos4_clkset_mout_mfc_list,
+       .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
+};
+
+static struct clk *exynos4_clkset_sclk_dac_list[] = {
+       [0] = &exynos4_clk_sclk_vpll.clk,
+       [1] = &exynos4_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_dac = {
+       .sources        = exynos4_clkset_sclk_dac_list,
+       .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_dac = {
+       .clk            = {
+               .name           = "sclk_dac",
+               .enable         = exynos4_clksrc_mask_tv_ctrl,
+               .ctrlbit        = (1 << 8),
+       },
+       .sources = &exynos4_clkset_sclk_dac,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_pixel = {
+       .clk            = {
+               .name           = "sclk_pixel",
+               .parent         = &exynos4_clk_sclk_vpll.clk,
+       },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
+};
+
+static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
+       [0] = &exynos4_clk_sclk_pixel.clk,
+       [1] = &exynos4_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
+       .sources        = exynos4_clkset_sclk_hdmi_list,
+       .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_hdmi = {
+       .clk            = {
+               .name           = "sclk_hdmi",
+               .enable         = exynos4_clksrc_mask_tv_ctrl,
+               .ctrlbit        = (1 << 0),
+       },
+       .sources = &exynos4_clkset_sclk_hdmi,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_sclk_mixer_list[] = {
+       [0] = &exynos4_clk_sclk_dac.clk,
+       [1] = &exynos4_clk_sclk_hdmi.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_mixer = {
+       .sources        = exynos4_clkset_sclk_mixer_list,
+       .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mixer = {
+       .clk    = {
+               .name           = "sclk_mixer",
+               .enable         = exynos4_clksrc_mask_tv_ctrl,
+               .ctrlbit        = (1 << 4),
+       },
+       .sources = &exynos4_clkset_sclk_mixer,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk *exynos4_sclk_tv[] = {
+       &exynos4_clk_sclk_dac,
+       &exynos4_clk_sclk_pixel,
+       &exynos4_clk_sclk_hdmi,
+       &exynos4_clk_sclk_mixer,
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc0 = {
+       .clk    = {
+               .name           = "dout_mmc0",
+       },
+       .sources = &exynos4_clkset_group,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc1 = {
+       .clk    = {
+               .name           = "dout_mmc1",
+       },
+       .sources = &exynos4_clkset_group,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc2 = {
+       .clk    = {
+               .name           = "dout_mmc2",
+       },
+       .sources = &exynos4_clkset_group,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc3 = {
+       .clk    = {
+               .name           = "dout_mmc3",
+       },
+       .sources = &exynos4_clkset_group,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc4 = {
+       .clk            = {
+               .name           = "dout_mmc4",
+       },
+       .sources = &exynos4_clkset_group,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clksrcs[] = {
+       {
+               .clk    = {
+                       .name           = "sclk_pwm",
+                       .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                       .ctrlbit        = (1 << 24),
+               },
+               .sources = &exynos4_clkset_group,
+               .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
+               .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_csis",
+                       .devname        = "s5p-mipi-csis.0",
+                       .enable         = exynos4_clksrc_mask_cam_ctrl,
+                       .ctrlbit        = (1 << 24),
+               },
+               .sources = &exynos4_clkset_group,
+               .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
+               .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_csis",
+                       .devname        = "s5p-mipi-csis.1",
+                       .enable         = exynos4_clksrc_mask_cam_ctrl,
+                       .ctrlbit        = (1 << 28),
+               },
+               .sources = &exynos4_clkset_group,
+               .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
+               .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_cam0",
+                       .enable         = exynos4_clksrc_mask_cam_ctrl,
+                       .ctrlbit        = (1 << 16),
+               },
+               .sources = &exynos4_clkset_group,
+               .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
+               .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_cam1",
+                       .enable         = exynos4_clksrc_mask_cam_ctrl,
+                       .ctrlbit        = (1 << 20),
+               },
+               .sources = &exynos4_clkset_group,
+               .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
+               .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_fimc",
+                       .devname        = "exynos4-fimc.0",
+                       .enable         = exynos4_clksrc_mask_cam_ctrl,
+                       .ctrlbit        = (1 << 0),
+               },
+               .sources = &exynos4_clkset_group,
+               .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
+               .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_fimc",
+                       .devname        = "exynos4-fimc.1",
+                       .enable         = exynos4_clksrc_mask_cam_ctrl,
+                       .ctrlbit        = (1 << 4),
+               },
+               .sources = &exynos4_clkset_group,
+               .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
+               .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_fimc",
+                       .devname        = "exynos4-fimc.2",
+                       .enable         = exynos4_clksrc_mask_cam_ctrl,
+                       .ctrlbit        = (1 << 8),
+               },
+               .sources = &exynos4_clkset_group,
+               .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
+               .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_fimc",
+                       .devname        = "exynos4-fimc.3",
+                       .enable         = exynos4_clksrc_mask_cam_ctrl,
+                       .ctrlbit        = (1 << 12),
+               },
+               .sources = &exynos4_clkset_group,
+               .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
+               .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_fimd",
+                       .devname        = "exynos4-fb.0",
+                       .enable         = exynos4_clksrc_mask_lcd0_ctrl,
+                       .ctrlbit        = (1 << 0),
+               },
+               .sources = &exynos4_clkset_group,
+               .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
+               .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_fimg2d",
+               },
+               .sources = &exynos4_clkset_mout_g2d,
+               .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
+               .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_mfc",
+                       .devname        = "s5p-mfc",
+               },
+               .sources = &exynos4_clkset_mout_mfc,
+               .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
+               .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_dwmmc",
+                       .parent         = &exynos4_clk_dout_mmc4.clk,
+                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                       .ctrlbit        = (1 << 16),
+               },
+               .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+       }
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart0 = {
+       .clk    = {
+               .name           = "uclk1",
+               .devname        = "exynos4210-uart.0",
+               .enable         = exynos4_clksrc_mask_peril0_ctrl,
+               .ctrlbit        = (1 << 0),
+       },
+       .sources = &exynos4_clkset_group,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart1 = {
+       .clk    = {
+               .name           = "uclk1",
+               .devname        = "exynos4210-uart.1",
+               .enable         = exynos4_clksrc_mask_peril0_ctrl,
+               .ctrlbit        = (1 << 4),
+       },
+       .sources = &exynos4_clkset_group,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart2 = {
+       .clk    = {
+               .name           = "uclk1",
+               .devname        = "exynos4210-uart.2",
+               .enable         = exynos4_clksrc_mask_peril0_ctrl,
+               .ctrlbit        = (1 << 8),
+       },
+       .sources = &exynos4_clkset_group,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart3 = {
+       .clk    = {
+               .name           = "uclk1",
+               .devname        = "exynos4210-uart.3",
+               .enable         = exynos4_clksrc_mask_peril0_ctrl,
+               .ctrlbit        = (1 << 12),
+       },
+       .sources = &exynos4_clkset_group,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.0",
+               .parent         = &exynos4_clk_dout_mmc0.clk,
+               .enable         = exynos4_clksrc_mask_fsys_ctrl,
+               .ctrlbit        = (1 << 0),
+       },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.1",
+               .parent         = &exynos4_clk_dout_mmc1.clk,
+               .enable         = exynos4_clksrc_mask_fsys_ctrl,
+               .ctrlbit        = (1 << 4),
+       },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.2",
+               .parent         = &exynos4_clk_dout_mmc2.clk,
+               .enable         = exynos4_clksrc_mask_fsys_ctrl,
+               .ctrlbit        = (1 << 8),
+       },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.3",
+               .parent         = &exynos4_clk_dout_mmc3.clk,
+               .enable         = exynos4_clksrc_mask_fsys_ctrl,
+               .ctrlbit        = (1 << 12),
+       },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_spi0 = {
+       .clk    = {
+               .name           = "sclk_spi",
+               .devname        = "s3c64xx-spi.0",
+               .enable         = exynos4_clksrc_mask_peril1_ctrl,
+               .ctrlbit        = (1 << 16),
+       },
+       .sources = &exynos4_clkset_group,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_spi1 = {
+       .clk    = {
+               .name           = "sclk_spi",
+               .devname        = "s3c64xx-spi.1",
+               .enable         = exynos4_clksrc_mask_peril1_ctrl,
+               .ctrlbit        = (1 << 20),
+       },
+       .sources = &exynos4_clkset_group,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_spi2 = {
+       .clk    = {
+               .name           = "sclk_spi",
+               .devname        = "s3c64xx-spi.2",
+               .enable         = exynos4_clksrc_mask_peril1_ctrl,
+               .ctrlbit        = (1 << 24),
+       },
+       .sources = &exynos4_clkset_group,
+       .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+       .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *exynos4_sysclks[] = {
+       &exynos4_clk_mout_apll,
+       &exynos4_clk_sclk_apll,
+       &exynos4_clk_mout_epll,
+       &exynos4_clk_mout_mpll,
+       &exynos4_clk_moutcore,
+       &exynos4_clk_coreclk,
+       &exynos4_clk_armclk,
+       &exynos4_clk_aclk_corem0,
+       &exynos4_clk_aclk_cores,
+       &exynos4_clk_aclk_corem1,
+       &exynos4_clk_periphclk,
+       &exynos4_clk_mout_corebus,
+       &exynos4_clk_sclk_dmc,
+       &exynos4_clk_aclk_cored,
+       &exynos4_clk_aclk_corep,
+       &exynos4_clk_aclk_acp,
+       &exynos4_clk_pclk_acp,
+       &exynos4_clk_vpllsrc,
+       &exynos4_clk_sclk_vpll,
+       &exynos4_clk_aclk_200,
+       &exynos4_clk_aclk_100,
+       &exynos4_clk_aclk_160,
+       &exynos4_clk_aclk_133,
+       &exynos4_clk_dout_mmc0,
+       &exynos4_clk_dout_mmc1,
+       &exynos4_clk_dout_mmc2,
+       &exynos4_clk_dout_mmc3,
+       &exynos4_clk_dout_mmc4,
+       &exynos4_clk_mout_mfc0,
+       &exynos4_clk_mout_mfc1,
+};
+
+static struct clk *exynos4_clk_cdev[] = {
+       &exynos4_clk_pdma0,
+       &exynos4_clk_pdma1,
+       &exynos4_clk_mdma1,
+       &exynos4_clk_fimd0,
+};
+
+static struct clksrc_clk *exynos4_clksrc_cdev[] = {
+       &exynos4_clk_sclk_uart0,
+       &exynos4_clk_sclk_uart1,
+       &exynos4_clk_sclk_uart2,
+       &exynos4_clk_sclk_uart3,
+       &exynos4_clk_sclk_mmc0,
+       &exynos4_clk_sclk_mmc1,
+       &exynos4_clk_sclk_mmc2,
+       &exynos4_clk_sclk_mmc3,
+       &exynos4_clk_sclk_spi0,
+       &exynos4_clk_sclk_spi1,
+       &exynos4_clk_sclk_spi2,
+
+};
+
+static struct clk_lookup exynos4_clk_lookup[] = {
+       CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
+       CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
+       CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
+       CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
+       CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
+       CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
+       CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
+       CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
+       CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
+       CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
+       CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
+       CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
+       CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
+       CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
+       CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
+};
+
+static int xtal_rate;
+
+static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
+{
+       if (soc_is_exynos4210())
+               return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
+                                       pll_4508);
+       else if (soc_is_exynos4212() || soc_is_exynos4412())
+               return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
+       else
+               return 0;
+}
+
+static struct clk_ops exynos4_fout_apll_ops = {
+       .get_rate = exynos4_fout_apll_get_rate,
+};
+
+static u32 exynos4_vpll_div[][8] = {
+       {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
+       { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
+};
+
+static unsigned long exynos4_vpll_get_rate(struct clk *clk)
+{
+       return clk->rate;
+}
+
+static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
+{
+       unsigned int vpll_con0, vpll_con1 = 0;
+       unsigned int i;
+
+       /* Return if nothing changed */
+       if (clk->rate == rate)
+               return 0;
+
+       vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
+       vpll_con0 &= ~(0x1 << 27 |                                      \
+                       PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
+                       PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
+                       PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+       vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
+       vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
+                       PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
+                       PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
+
+       for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
+               if (exynos4_vpll_div[i][0] == rate) {
+                       vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
+                       vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
+                       vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
+                       vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
+                       vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
+                       vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
+                       vpll_con0 |= exynos4_vpll_div[i][7] << 27;
+                       break;
+               }
+       }
+
+       if (i == ARRAY_SIZE(exynos4_vpll_div)) {
+               printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
+                               __func__);
+               return -EINVAL;
+       }
+
+       __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
+       __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
+
+       /* Wait for VPLL lock */
+       while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
+               continue;
+
+       clk->rate = rate;
+       return 0;
+}
+
+static struct clk_ops exynos4_vpll_ops = {
+       .get_rate = exynos4_vpll_get_rate,
+       .set_rate = exynos4_vpll_set_rate,
+};
+
+void __init_or_cpufreq exynos4_setup_clocks(void)
+{
+       struct clk *xtal_clk;
+       unsigned long apll = 0;
+       unsigned long mpll = 0;
+       unsigned long epll = 0;
+       unsigned long vpll = 0;
+       unsigned long vpllsrc;
+       unsigned long xtal;
+       unsigned long armclk;
+       unsigned long sclk_dmc;
+       unsigned long aclk_200;
+       unsigned long aclk_100;
+       unsigned long aclk_160;
+       unsigned long aclk_133;
+       unsigned int ptr;
+
+       printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+       xtal_clk = clk_get(NULL, "xtal");
+       BUG_ON(IS_ERR(xtal_clk));
+
+       xtal = clk_get_rate(xtal_clk);
+
+       xtal_rate = xtal;
+
+       clk_put(xtal_clk);
+
+       printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+       if (soc_is_exynos4210()) {
+               apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
+                                       pll_4508);
+               mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
+                                       pll_4508);
+               epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
+                                       __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
+
+               vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
+               vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
+                                       __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
+       } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+               apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
+               mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
+               epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
+                                       __raw_readl(EXYNOS4_EPLL_CON1));
+
+               vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
+               vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
+                                       __raw_readl(EXYNOS4_VPLL_CON1));
+       } else {
+               /* nothing */
+       }
+
+       clk_fout_apll.ops = &exynos4_fout_apll_ops;
+       clk_fout_mpll.rate = mpll;
+       clk_fout_epll.rate = epll;
+       clk_fout_vpll.ops = &exynos4_vpll_ops;
+       clk_fout_vpll.rate = vpll;
+
+       printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
+                       apll, mpll, epll, vpll);
+
+       armclk = clk_get_rate(&exynos4_clk_armclk.clk);
+       sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
+
+       aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
+       aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
+       aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
+       aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
+
+       printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
+                        "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
+                       armclk, sclk_dmc, aclk_200,
+                       aclk_100, aclk_160, aclk_133);
+
+       clk_f.rate = armclk;
+       clk_h.rate = sclk_dmc;
+       clk_p.rate = aclk_100;
+
+       for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
+               s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
+}
+
+static struct clk *exynos4_clks[] __initdata = {
+       &exynos4_clk_sclk_hdmi27m,
+       &exynos4_clk_sclk_hdmiphy,
+       &exynos4_clk_sclk_usbphy0,
+       &exynos4_clk_sclk_usbphy1,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos4_clock_suspend(void)
+{
+       s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+       return 0;
+}
+
+static void exynos4_clock_resume(void)
+{
+       s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+}
+
+#else
+#define exynos4_clock_suspend NULL
+#define exynos4_clock_resume NULL
+#endif
+
+static struct syscore_ops exynos4_clock_syscore_ops = {
+       .suspend        = exynos4_clock_suspend,
+       .resume         = exynos4_clock_resume,
+};
+
+void __init exynos4_register_clocks(void)
+{
+       int ptr;
+
+       s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
+
+       for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
+               s3c_register_clksrc(exynos4_sysclks[ptr], 1);
+
+       for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
+               s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
+
+       for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
+               s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
+
+       s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
+       s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
+
+       s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
+       for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
+               s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
+
+       s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
+       s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
+       clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
+
+       register_syscore_ops(&exynos4_clock_syscore_ops);
+       s3c24xx_register_clock(&dummy_apb_pclk);
+
+       s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
new file mode 100644 (file)
index 0000000..cb71c29
--- /dev/null
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Header file for exynos4 clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H __FILE__
+
+#include <linux/clk.h>
+
+extern struct clksrc_clk exynos4_clk_aclk_133;
+extern struct clksrc_clk exynos4_clk_mout_mpll;
+
+extern struct clksrc_sources exynos4_clkset_mout_corebus;
+extern struct clksrc_sources exynos4_clkset_group;
+
+extern struct clk *exynos4_clkset_aclk_top_list[];
+extern struct clk *exynos4_clkset_group_list[];
+
+extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
+
+#endif /* __ASM_ARCH_CLOCK_H */
index 13312cc..3b131e4 100644 (file)
@@ -1,7 +1,5 @@
 /*
- * linux/arch/arm/mach-exynos4/clock-exynos4210.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *             http://www.samsung.com
  *
  * EXYNOS4210 - Clock support
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/exynos4-clock.h>
 
 #include "common.h"
+#include "clock-exynos4.h"
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4210_clock_save[] = {
-       SAVE_ITEM(S5P_CLKSRC_IMAGE),
-       SAVE_ITEM(S5P_CLKSRC_LCD1),
-       SAVE_ITEM(S5P_CLKDIV_IMAGE),
-       SAVE_ITEM(S5P_CLKDIV_LCD1),
-       SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
-       SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
-       SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
-       SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
+       SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
+       SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
+       SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
+       SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
+       SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
+       SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
+       SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
+       SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
 };
 #endif
 
@@ -51,7 +49,7 @@ static struct clksrc_clk *sysclks[] = {
 
 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
 {
-       return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
+       return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
 }
 
 static struct clksrc_clk clksrcs[] = {
@@ -62,9 +60,9 @@ static struct clksrc_clk clksrcs[] = {
                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
                        .ctrlbit        = (1 << 24),
                },
-               .sources = &clkset_mout_corebus,
-               .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
-               .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+               .sources = &exynos4_clkset_mout_corebus,
+               .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
+               .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
        }, {
                .clk            = {
                        .name           = "sclk_fimd",
@@ -72,9 +70,9 @@ static struct clksrc_clk clksrcs[] = {
                        .enable         = exynos4_clksrc_mask_lcd1_ctrl,
                        .ctrlbit        = (1 << 0),
                },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
+               .sources = &exynos4_clkset_group,
+               .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
+               .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
        },
 };
 
@@ -82,13 +80,13 @@ static struct clk init_clocks_off[] = {
        {
                .name           = "sataphy",
                .id             = -1,
-               .parent         = &clk_aclk_133.clk,
+               .parent         = &exynos4_clk_aclk_133.clk,
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 3),
        }, {
                .name           = "sata",
                .id             = -1,
-               .parent         = &clk_aclk_133.clk,
+               .parent         = &exynos4_clk_aclk_133.clk,
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 10),
        }, {
@@ -117,7 +115,7 @@ static void exynos4210_clock_resume(void)
 #define exynos4210_clock_resume NULL
 #endif
 
-struct syscore_ops exynos4210_clock_syscore_ops = {
+static struct syscore_ops exynos4210_clock_syscore_ops = {
        .suspend        = exynos4210_clock_suspend,
        .resume         = exynos4210_clock_resume,
 };
@@ -126,9 +124,9 @@ void __init exynos4210_register_clocks(void)
 {
        int ptr;
 
-       clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
-       clk_mout_mpll.reg_src.shift = 8;
-       clk_mout_mpll.reg_src.size = 1;
+       exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
+       exynos4_clk_mout_mpll.reg_src.shift = 8;
+       exynos4_clk_mout_mpll.reg_src.size = 1;
 
        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
                s3c_register_clksrc(sysclks[ptr], 1);
index 48af285..3ecc01e 100644 (file)
@@ -1,7 +1,5 @@
 /*
- * linux/arch/arm/mach-exynos4/clock-exynos4212.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *             http://www.samsung.com
  *
  * EXYNOS4212 - Clock support
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/exynos4-clock.h>
 
 #include "common.h"
+#include "clock-exynos4.h"
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4212_clock_save[] = {
-       SAVE_ITEM(S5P_CLKSRC_IMAGE),
-       SAVE_ITEM(S5P_CLKDIV_IMAGE),
-       SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
-       SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
+       SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
+       SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
+       SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
+       SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
 };
 #endif
 
 static struct clk *clk_src_mpll_user_list[] = {
        [0] = &clk_fin_mpll,
-       [1] = &clk_mout_mpll.clk,
+       [1] = &exynos4_clk_mout_mpll.clk,
 };
 
 static struct clksrc_sources clk_src_mpll_user = {
@@ -56,7 +54,7 @@ static struct clksrc_clk clk_mout_mpll_user = {
                .name           = "mout_mpll_user",
        },
        .sources        = &clk_src_mpll_user,
-       .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
+       .reg_src        = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
 };
 
 static struct clksrc_clk *sysclks[] = {
@@ -89,7 +87,7 @@ static void exynos4212_clock_resume(void)
 #define exynos4212_clock_resume NULL
 #endif
 
-struct syscore_ops exynos4212_clock_syscore_ops = {
+static struct syscore_ops exynos4212_clock_syscore_ops = {
        .suspend        = exynos4212_clock_suspend,
        .resume         = exynos4212_clock_resume,
 };
@@ -99,15 +97,15 @@ void __init exynos4212_register_clocks(void)
        int ptr;
 
        /* usbphy1 is removed */
-       clkset_group_list[4] = NULL;
+       exynos4_clkset_group_list[4] = NULL;
 
        /* mout_mpll_user is used */
-       clkset_group_list[6] = &clk_mout_mpll_user.clk;
-       clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
+       exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
+       exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
 
-       clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
-       clk_mout_mpll.reg_src.shift = 12;
-       clk_mout_mpll.reg_src.size = 1;
+       exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
+       exynos4_clk_mout_mpll.reg_src.shift = 12;
+       exynos4_clk_mout_mpll.reg_src.size = 1;
 
        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
                s3c_register_clksrc(sysclks[ptr], 1);
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
new file mode 100644 (file)
index 0000000..d013982
--- /dev/null
@@ -0,0 +1,1247 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Clock support for EXYNOS5 SoCs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/pm.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
+
+#include "common.h"
+
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos5_clock_save[] = {
+       /* will be implemented */
+};
+#endif
+
+static struct clk exynos5_clk_sclk_dptxphy = {
+       .name           = "sclk_dptx",
+};
+
+static struct clk exynos5_clk_sclk_hdmi24m = {
+       .name           = "sclk_hdmi24m",
+       .rate           = 24000000,
+};
+
+static struct clk exynos5_clk_sclk_hdmi27m = {
+       .name           = "sclk_hdmi27m",
+       .rate           = 27000000,
+};
+
+static struct clk exynos5_clk_sclk_hdmiphy = {
+       .name           = "sclk_hdmiphy",
+};
+
+static struct clk exynos5_clk_sclk_usbphy = {
+       .name           = "sclk_usbphy",
+       .rate           = 48000000,
+};
+
+static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
+}
+
+static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
+}
+
+static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
+}
+
+static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
+}
+
+static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
+}
+
+static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
+}
+
+static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
+}
+
+static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
+}
+
+static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
+}
+
+static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
+}
+
+static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
+}
+
+static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
+}
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk exynos5_clk_mout_apll = {
+       .clk    = {
+               .name           = "mout_apll",
+       },
+       .sources = &clk_src_apll,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_apll = {
+       .clk    = {
+               .name           = "sclk_apll",
+               .parent         = &exynos5_clk_mout_apll.clk,
+       },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll = {
+       .clk    = {
+               .name           = "mout_bpll",
+       },
+       .sources = &clk_src_bpll,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_bpll_user_list[] = {
+       [0] = &clk_fin_mpll,
+       [1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_bpll_user = {
+       .sources        = exynos5_clk_src_bpll_user_list,
+       .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll_user = {
+       .clk    = {
+               .name           = "mout_bpll_user",
+       },
+       .sources = &exynos5_clk_src_bpll_user,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_cpll = {
+       .clk    = {
+               .name           = "mout_cpll",
+       },
+       .sources = &clk_src_cpll,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_epll = {
+       .clk    = {
+               .name           = "mout_epll",
+       },
+       .sources = &clk_src_epll,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
+};
+
+struct clksrc_clk exynos5_clk_mout_mpll = {
+       .clk = {
+               .name           = "mout_mpll",
+       },
+       .sources = &clk_src_mpll,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
+};
+
+static struct clk *exynos_clkset_vpllsrc_list[] = {
+       [0] = &clk_fin_vpll,
+       [1] = &exynos5_clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources exynos5_clkset_vpllsrc = {
+       .sources        = exynos_clkset_vpllsrc_list,
+       .nr_sources     = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
+};
+
+static struct clksrc_clk exynos5_clk_vpllsrc = {
+       .clk    = {
+               .name           = "vpll_src",
+               .enable         = exynos5_clksrc_mask_top_ctrl,
+               .ctrlbit        = (1 << 0),
+       },
+       .sources = &exynos5_clkset_vpllsrc,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_sclk_vpll_list[] = {
+       [0] = &exynos5_clk_vpllsrc.clk,
+       [1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_vpll = {
+       .sources        = exynos5_clkset_sclk_vpll_list,
+       .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_vpll = {
+       .clk    = {
+               .name           = "sclk_vpll",
+       },
+       .sources = &exynos5_clkset_sclk_vpll,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_pixel = {
+       .clk    = {
+               .name           = "sclk_pixel",
+               .parent         = &exynos5_clk_sclk_vpll.clk,
+       },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
+};
+
+static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
+       [0] = &exynos5_clk_sclk_pixel.clk,
+       [1] = &exynos5_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
+       .sources        = exynos5_clkset_sclk_hdmi_list,
+       .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_hdmi = {
+       .clk    = {
+               .name           = "sclk_hdmi",
+               .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
+               .ctrlbit        = (1 << 20),
+       },
+       .sources = &exynos5_clkset_sclk_hdmi,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
+};
+
+static struct clksrc_clk *exynos5_sclk_tv[] = {
+       &exynos5_clk_sclk_pixel,
+       &exynos5_clk_sclk_hdmi,
+};
+
+static struct clk *exynos5_clk_src_mpll_user_list[] = {
+       [0] = &clk_fin_mpll,
+       [1] = &exynos5_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_mpll_user = {
+       .sources        = exynos5_clk_src_mpll_user_list,
+       .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_mpll_user = {
+       .clk    = {
+               .name           = "mout_mpll_user",
+       },
+       .sources = &exynos5_clk_src_mpll_user,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_mout_cpu_list[] = {
+       [0] = &exynos5_clk_mout_apll.clk,
+       [1] = &exynos5_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_cpu = {
+       .sources        = exynos5_clkset_mout_cpu_list,
+       .nr_sources     = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_cpu = {
+       .clk    = {
+               .name           = "mout_cpu",
+       },
+       .sources = &exynos5_clkset_mout_cpu,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_armclk = {
+       .clk    = {
+               .name           = "dout_armclk",
+               .parent         = &exynos5_clk_mout_cpu.clk,
+       },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_arm2clk = {
+       .clk    = {
+               .name           = "dout_arm2clk",
+               .parent         = &exynos5_clk_dout_armclk.clk,
+       },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
+};
+
+static struct clk exynos5_clk_armclk = {
+       .name           = "armclk",
+       .parent         = &exynos5_clk_dout_arm2clk.clk,
+};
+
+/* Core list of CMU_CDREX side */
+
+static struct clk *exynos5_clkset_cdrex_list[] = {
+       [0] = &exynos5_clk_mout_mpll.clk,
+       [1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_cdrex = {
+       .sources        = exynos5_clkset_cdrex_list,
+       .nr_sources     = ARRAY_SIZE(exynos5_clkset_cdrex_list),
+};
+
+static struct clksrc_clk exynos5_clk_cdrex = {
+       .clk    = {
+               .name           = "clk_cdrex",
+       },
+       .sources = &exynos5_clkset_cdrex,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_acp = {
+       .clk    = {
+               .name           = "aclk_acp",
+               .parent         = &exynos5_clk_mout_mpll.clk,
+       },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_pclk_acp = {
+       .clk    = {
+               .name           = "pclk_acp",
+               .parent         = &exynos5_clk_aclk_acp.clk,
+       },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
+};
+
+/* Core list of CMU_TOP side */
+
+struct clk *exynos5_clkset_aclk_top_list[] = {
+       [0] = &exynos5_clk_mout_mpll_user.clk,
+       [1] = &exynos5_clk_mout_bpll_user.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk = {
+       .sources        = exynos5_clkset_aclk_top_list,
+       .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400 = {
+       .clk    = {
+               .name           = "aclk_400",
+       },
+       .sources = &exynos5_clkset_aclk,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+};
+
+struct clk *exynos5_clkset_aclk_333_166_list[] = {
+       [0] = &exynos5_clk_mout_cpll.clk,
+       [1] = &exynos5_clk_mout_mpll_user.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk_333_166 = {
+       .sources        = exynos5_clkset_aclk_333_166_list,
+       .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_333 = {
+       .clk    = {
+               .name           = "aclk_333",
+       },
+       .sources = &exynos5_clkset_aclk_333_166,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_166 = {
+       .clk    = {
+               .name           = "aclk_166",
+       },
+       .sources = &exynos5_clkset_aclk_333_166,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266 = {
+       .clk    = {
+               .name           = "aclk_266",
+               .parent         = &exynos5_clk_mout_mpll_user.clk,
+       },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_200 = {
+       .clk    = {
+               .name           = "aclk_200",
+       },
+       .sources = &exynos5_clkset_aclk,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_66_pre = {
+       .clk    = {
+               .name           = "aclk_66_pre",
+               .parent         = &exynos5_clk_mout_mpll_user.clk,
+       },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_66 = {
+       .clk    = {
+               .name           = "aclk_66",
+               .parent         = &exynos5_clk_aclk_66_pre.clk,
+       },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
+};
+
+static struct clk exynos5_init_clocks_off[] = {
+       {
+               .name           = "timers",
+               .parent         = &exynos5_clk_aclk_66.clk,
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 24),
+       }, {
+               .name           = "rtc",
+               .parent         = &exynos5_clk_aclk_66.clk,
+               .enable         = exynos5_clk_ip_peris_ctrl,
+               .ctrlbit        = (1 << 20),
+       }, {
+               .name           = "hsmmc",
+               .devname        = "s3c-sdhci.0",
+               .parent         = &exynos5_clk_aclk_200.clk,
+               .enable         = exynos5_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 12),
+       }, {
+               .name           = "hsmmc",
+               .devname        = "s3c-sdhci.1",
+               .parent         = &exynos5_clk_aclk_200.clk,
+               .enable         = exynos5_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 13),
+       }, {
+               .name           = "hsmmc",
+               .devname        = "s3c-sdhci.2",
+               .parent         = &exynos5_clk_aclk_200.clk,
+               .enable         = exynos5_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 14),
+       }, {
+               .name           = "hsmmc",
+               .devname        = "s3c-sdhci.3",
+               .parent         = &exynos5_clk_aclk_200.clk,
+               .enable         = exynos5_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 15),
+       }, {
+               .name           = "dwmci",
+               .parent         = &exynos5_clk_aclk_200.clk,
+               .enable         = exynos5_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 16),
+       }, {
+               .name           = "sata",
+               .devname        = "ahci",
+               .enable         = exynos5_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 6),
+       }, {
+               .name           = "sata_phy",
+               .enable         = exynos5_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 24),
+       }, {
+               .name           = "sata_phy_i2c",
+               .enable         = exynos5_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 25),
+       }, {
+               .name           = "mfc",
+               .devname        = "s5p-mfc",
+               .enable         = exynos5_clk_ip_mfc_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "hdmi",
+               .devname        = "exynos4-hdmi",
+               .enable         = exynos5_clk_ip_disp1_ctrl,
+               .ctrlbit        = (1 << 6),
+       }, {
+               .name           = "mixer",
+               .devname        = "s5p-mixer",
+               .enable         = exynos5_clk_ip_disp1_ctrl,
+               .ctrlbit        = (1 << 5),
+       }, {
+               .name           = "jpeg",
+               .enable         = exynos5_clk_ip_gen_ctrl,
+               .ctrlbit        = (1 << 2),
+       }, {
+               .name           = "dsim0",
+               .enable         = exynos5_clk_ip_disp1_ctrl,
+               .ctrlbit        = (1 << 3),
+       }, {
+               .name           = "iis",
+               .devname        = "samsung-i2s.1",
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 20),
+       }, {
+               .name           = "iis",
+               .devname        = "samsung-i2s.2",
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 21),
+       }, {
+               .name           = "pcm",
+               .devname        = "samsung-pcm.1",
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 22),
+       }, {
+               .name           = "pcm",
+               .devname        = "samsung-pcm.2",
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 23),
+       }, {
+               .name           = "spdif",
+               .devname        = "samsung-spdif",
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 26),
+       }, {
+               .name           = "ac97",
+               .devname        = "samsung-ac97",
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 27),
+       }, {
+               .name           = "usbhost",
+               .enable         = exynos5_clk_ip_fsys_ctrl ,
+               .ctrlbit        = (1 << 18),
+       }, {
+               .name           = "usbotg",
+               .enable         = exynos5_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 7),
+       }, {
+               .name           = "gps",
+               .enable         = exynos5_clk_ip_gps_ctrl,
+               .ctrlbit        = ((1 << 3) | (1 << 2) | (1 << 0)),
+       }, {
+               .name           = "nfcon",
+               .enable         = exynos5_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 22),
+       }, {
+               .name           = "iop",
+               .enable         = exynos5_clk_ip_fsys_ctrl,
+               .ctrlbit        = ((1 << 30) | (1 << 26) | (1 << 23)),
+       }, {
+               .name           = "core_iop",
+               .enable         = exynos5_clk_ip_core_ctrl,
+               .ctrlbit        = ((1 << 21) | (1 << 3)),
+       }, {
+               .name           = "mcu_iop",
+               .enable         = exynos5_clk_ip_fsys_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.0",
+               .parent         = &exynos5_clk_aclk_66.clk,
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 6),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.1",
+               .parent         = &exynos5_clk_aclk_66.clk,
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 7),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.2",
+               .parent         = &exynos5_clk_aclk_66.clk,
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 8),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.3",
+               .parent         = &exynos5_clk_aclk_66.clk,
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 9),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.4",
+               .parent         = &exynos5_clk_aclk_66.clk,
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 10),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.5",
+               .parent         = &exynos5_clk_aclk_66.clk,
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 11),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.6",
+               .parent         = &exynos5_clk_aclk_66.clk,
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 12),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-i2c.7",
+               .parent         = &exynos5_clk_aclk_66.clk,
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 13),
+       }, {
+               .name           = "i2c",
+               .devname        = "s3c2440-hdmiphy-i2c",
+               .parent         = &exynos5_clk_aclk_66.clk,
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 14),
+       }
+};
+
+static struct clk exynos5_init_clocks_on[] = {
+       {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.0",
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.1",
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 1),
+       }, {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.2",
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 2),
+       }, {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.3",
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 3),
+       }, {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.4",
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 4),
+       }, {
+               .name           = "uart",
+               .devname        = "s5pv210-uart.5",
+               .enable         = exynos5_clk_ip_peric_ctrl,
+               .ctrlbit        = (1 << 5),
+       }
+};
+
+static struct clk exynos5_clk_pdma0 = {
+       .name           = "dma",
+       .devname        = "dma-pl330.0",
+       .enable         = exynos5_clk_ip_fsys_ctrl,
+       .ctrlbit        = (1 << 1),
+};
+
+static struct clk exynos5_clk_pdma1 = {
+       .name           = "dma",
+       .devname        = "dma-pl330.1",
+       .enable         = exynos5_clk_ip_fsys_ctrl,
+       .ctrlbit        = (1 << 1),
+};
+
+static struct clk exynos5_clk_mdma1 = {
+       .name           = "dma",
+       .devname        = "dma-pl330.2",
+       .enable         = exynos5_clk_ip_gen_ctrl,
+       .ctrlbit        = (1 << 4),
+};
+
+struct clk *exynos5_clkset_group_list[] = {
+       [0] = &clk_ext_xtal_mux,
+       [1] = NULL,
+       [2] = &exynos5_clk_sclk_hdmi24m,
+       [3] = &exynos5_clk_sclk_dptxphy,
+       [4] = &exynos5_clk_sclk_usbphy,
+       [5] = &exynos5_clk_sclk_hdmiphy,
+       [6] = &exynos5_clk_mout_mpll_user.clk,
+       [7] = &exynos5_clk_mout_epll.clk,
+       [8] = &exynos5_clk_sclk_vpll.clk,
+       [9] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_group = {
+       .sources        = exynos5_clkset_group_list,
+       .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
+};
+
+/* Possible clock sources for aclk_266_gscl_sub Mux */
+static struct clk *clk_src_gscl_266_list[] = {
+       [0] = &clk_ext_xtal_mux,
+       [1] = &exynos5_clk_aclk_266.clk,
+};
+
+static struct clksrc_sources clk_src_gscl_266 = {
+       .sources        = clk_src_gscl_266_list,
+       .nr_sources     = ARRAY_SIZE(clk_src_gscl_266_list),
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc0 = {
+       .clk            = {
+               .name           = "dout_mmc0",
+       },
+       .sources = &exynos5_clkset_group,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc1 = {
+       .clk            = {
+               .name           = "dout_mmc1",
+       },
+       .sources = &exynos5_clkset_group,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc2 = {
+       .clk            = {
+               .name           = "dout_mmc2",
+       },
+       .sources = &exynos5_clkset_group,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc3 = {
+       .clk            = {
+               .name           = "dout_mmc3",
+       },
+       .sources = &exynos5_clkset_group,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc4 = {
+       .clk            = {
+               .name           = "dout_mmc4",
+       },
+       .sources = &exynos5_clkset_group,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart0 = {
+       .clk    = {
+               .name           = "uclk1",
+               .devname        = "exynos4210-uart.0",
+               .enable         = exynos5_clksrc_mask_peric0_ctrl,
+               .ctrlbit        = (1 << 0),
+       },
+       .sources = &exynos5_clkset_group,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart1 = {
+       .clk    = {
+               .name           = "uclk1",
+               .devname        = "exynos4210-uart.1",
+               .enable         = exynos5_clksrc_mask_peric0_ctrl,
+               .ctrlbit        = (1 << 4),
+       },
+       .sources = &exynos5_clkset_group,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart2 = {
+       .clk    = {
+               .name           = "uclk1",
+               .devname        = "exynos4210-uart.2",
+               .enable         = exynos5_clksrc_mask_peric0_ctrl,
+               .ctrlbit        = (1 << 8),
+       },
+       .sources = &exynos5_clkset_group,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart3 = {
+       .clk    = {
+               .name           = "uclk1",
+               .devname        = "exynos4210-uart.3",
+               .enable         = exynos5_clksrc_mask_peric0_ctrl,
+               .ctrlbit        = (1 << 12),
+       },
+       .sources = &exynos5_clkset_group,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.0",
+               .parent         = &exynos5_clk_dout_mmc0.clk,
+               .enable         = exynos5_clksrc_mask_fsys_ctrl,
+               .ctrlbit        = (1 << 0),
+       },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.1",
+               .parent         = &exynos5_clk_dout_mmc1.clk,
+               .enable         = exynos5_clksrc_mask_fsys_ctrl,
+               .ctrlbit        = (1 << 4),
+       },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.2",
+               .parent         = &exynos5_clk_dout_mmc2.clk,
+               .enable         = exynos5_clksrc_mask_fsys_ctrl,
+               .ctrlbit        = (1 << 8),
+       },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.3",
+               .parent         = &exynos5_clk_dout_mmc3.clk,
+               .enable         = exynos5_clksrc_mask_fsys_ctrl,
+               .ctrlbit        = (1 << 12),
+       },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clksrcs[] = {
+       {
+               .clk    = {
+                       .name           = "sclk_dwmci",
+                       .parent         = &exynos5_clk_dout_mmc4.clk,
+                       .enable         = exynos5_clksrc_mask_fsys_ctrl,
+                       .ctrlbit        = (1 << 16),
+               },
+               .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_fimd",
+                       .devname        = "s3cfb.1",
+                       .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
+                       .ctrlbit        = (1 << 0),
+               },
+               .sources = &exynos5_clkset_group,
+               .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
+               .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "aclk_266_gscl",
+               },
+               .sources = &clk_src_gscl_266,
+               .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_g3d",
+                       .devname        = "mali-t604.0",
+                       .enable         = exynos5_clk_block_ctrl,
+                       .ctrlbit        = (1 << 1),
+               },
+               .sources = &exynos5_clkset_aclk,
+               .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
+               .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_gscl_wrap",
+                       .devname        = "s5p-mipi-csis.0",
+                       .enable         = exynos5_clksrc_mask_gscl_ctrl,
+                       .ctrlbit        = (1 << 24),
+               },
+               .sources = &exynos5_clkset_group,
+               .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
+               .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_gscl_wrap",
+                       .devname        = "s5p-mipi-csis.1",
+                       .enable         = exynos5_clksrc_mask_gscl_ctrl,
+                       .ctrlbit        = (1 << 28),
+               },
+               .sources = &exynos5_clkset_group,
+               .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
+               .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_cam0",
+                       .enable         = exynos5_clksrc_mask_gscl_ctrl,
+                       .ctrlbit        = (1 << 16),
+               },
+               .sources = &exynos5_clkset_group,
+               .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
+               .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_cam1",
+                       .enable         = exynos5_clksrc_mask_gscl_ctrl,
+                       .ctrlbit        = (1 << 20),
+               },
+               .sources = &exynos5_clkset_group,
+               .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
+               .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_jpeg",
+                       .parent         = &exynos5_clk_mout_cpll.clk,
+               },
+               .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+       },
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *exynos5_sysclks[] = {
+       &exynos5_clk_mout_apll,
+       &exynos5_clk_sclk_apll,
+       &exynos5_clk_mout_bpll,
+       &exynos5_clk_mout_bpll_user,
+       &exynos5_clk_mout_cpll,
+       &exynos5_clk_mout_epll,
+       &exynos5_clk_mout_mpll,
+       &exynos5_clk_mout_mpll_user,
+       &exynos5_clk_vpllsrc,
+       &exynos5_clk_sclk_vpll,
+       &exynos5_clk_mout_cpu,
+       &exynos5_clk_dout_armclk,
+       &exynos5_clk_dout_arm2clk,
+       &exynos5_clk_cdrex,
+       &exynos5_clk_aclk_400,
+       &exynos5_clk_aclk_333,
+       &exynos5_clk_aclk_266,
+       &exynos5_clk_aclk_200,
+       &exynos5_clk_aclk_166,
+       &exynos5_clk_aclk_66_pre,
+       &exynos5_clk_aclk_66,
+       &exynos5_clk_dout_mmc0,
+       &exynos5_clk_dout_mmc1,
+       &exynos5_clk_dout_mmc2,
+       &exynos5_clk_dout_mmc3,
+       &exynos5_clk_dout_mmc4,
+       &exynos5_clk_aclk_acp,
+       &exynos5_clk_pclk_acp,
+};
+
+static struct clk *exynos5_clk_cdev[] = {
+       &exynos5_clk_pdma0,
+       &exynos5_clk_pdma1,
+       &exynos5_clk_mdma1,
+};
+
+static struct clksrc_clk *exynos5_clksrc_cdev[] = {
+       &exynos5_clk_sclk_uart0,
+       &exynos5_clk_sclk_uart1,
+       &exynos5_clk_sclk_uart2,
+       &exynos5_clk_sclk_uart3,
+       &exynos5_clk_sclk_mmc0,
+       &exynos5_clk_sclk_mmc1,
+       &exynos5_clk_sclk_mmc2,
+       &exynos5_clk_sclk_mmc3,
+};
+
+static struct clk_lookup exynos5_clk_lookup[] = {
+       CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
+       CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
+       CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
+       CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
+       CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
+       CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
+       CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
+       CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+       CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
+       CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
+       CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
+};
+
+static unsigned long exynos5_epll_get_rate(struct clk *clk)
+{
+       return clk->rate;
+}
+
+static struct clk *exynos5_clks[] __initdata = {
+       &exynos5_clk_sclk_hdmi27m,
+       &exynos5_clk_sclk_hdmiphy,
+       &clk_fout_bpll,
+       &clk_fout_cpll,
+       &exynos5_clk_armclk,
+};
+
+static u32 epll_div[][6] = {
+       { 192000000, 0, 48, 3, 1, 0 },
+       { 180000000, 0, 45, 3, 1, 0 },
+       {  73728000, 1, 73, 3, 3, 47710 },
+       {  67737600, 1, 90, 4, 3, 20762 },
+       {  49152000, 0, 49, 3, 3, 9961 },
+       {  45158400, 0, 45, 3, 3, 10381 },
+       { 180633600, 0, 45, 3, 1, 10381 },
+};
+
+static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+       unsigned int epll_con, epll_con_k;
+       unsigned int i;
+       unsigned int tmp;
+       unsigned int epll_rate;
+       unsigned int locktime;
+       unsigned int lockcnt;
+
+       /* Return if nothing changed */
+       if (clk->rate == rate)
+               return 0;
+
+       if (clk->parent)
+               epll_rate = clk_get_rate(clk->parent);
+       else
+               epll_rate = clk_ext_xtal_mux.rate;
+
+       if (epll_rate != 24000000) {
+               pr_err("Invalid Clock : recommended clock is 24MHz.\n");
+               return -EINVAL;
+       }
+
+       epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
+       epll_con &= ~(0x1 << 27 | \
+                       PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
+                       PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
+                       PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+       for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+               if (epll_div[i][0] == rate) {
+                       epll_con_k = epll_div[i][5] << 0;
+                       epll_con |= epll_div[i][1] << 27;
+                       epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
+                       epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
+                       epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
+                       break;
+               }
+       }
+
+       if (i == ARRAY_SIZE(epll_div)) {
+               printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
+                               __func__);
+               return -EINVAL;
+       }
+
+       epll_rate /= 1000000;
+
+       /* 3000 max_cycls : specification data */
+       locktime = 3000 / epll_rate * epll_div[i][3];
+       lockcnt = locktime * 10000 / (10000 / epll_rate);
+
+       __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
+
+       __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
+       __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
+
+       do {
+               tmp = __raw_readl(EXYNOS5_EPLL_CON0);
+       } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
+
+       clk->rate = rate;
+
+       return 0;
+}
+
+static struct clk_ops exynos5_epll_ops = {
+       .get_rate = exynos5_epll_get_rate,
+       .set_rate = exynos5_epll_set_rate,
+};
+
+static int xtal_rate;
+
+static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
+{
+       return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
+}
+
+static struct clk_ops exynos5_fout_apll_ops = {
+       .get_rate = exynos5_fout_apll_get_rate,
+};
+
+#ifdef CONFIG_PM
+static int exynos5_clock_suspend(void)
+{
+       s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
+
+       return 0;
+}
+
+static void exynos5_clock_resume(void)
+{
+       s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
+}
+#else
+#define exynos5_clock_suspend NULL
+#define exynos5_clock_resume NULL
+#endif
+
+struct syscore_ops exynos5_clock_syscore_ops = {
+       .suspend        = exynos5_clock_suspend,
+       .resume         = exynos5_clock_resume,
+};
+
+void __init_or_cpufreq exynos5_setup_clocks(void)
+{
+       struct clk *xtal_clk;
+       unsigned long apll;
+       unsigned long bpll;
+       unsigned long cpll;
+       unsigned long mpll;
+       unsigned long epll;
+       unsigned long vpll;
+       unsigned long vpllsrc;
+       unsigned long xtal;
+       unsigned long armclk;
+       unsigned long mout_cdrex;
+       unsigned long aclk_400;
+       unsigned long aclk_333;
+       unsigned long aclk_266;
+       unsigned long aclk_200;
+       unsigned long aclk_166;
+       unsigned long aclk_66;
+       unsigned int ptr;
+
+       printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+       xtal_clk = clk_get(NULL, "xtal");
+       BUG_ON(IS_ERR(xtal_clk));
+
+       xtal = clk_get_rate(xtal_clk);
+
+       xtal_rate = xtal;
+
+       clk_put(xtal_clk);
+
+       printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+       apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
+       bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
+       cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
+       mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
+       epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
+                       __raw_readl(EXYNOS5_EPLL_CON1));
+
+       vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
+       vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
+                       __raw_readl(EXYNOS5_VPLL_CON1));
+
+       clk_fout_apll.ops = &exynos5_fout_apll_ops;
+       clk_fout_bpll.rate = bpll;
+       clk_fout_cpll.rate = cpll;
+       clk_fout_mpll.rate = mpll;
+       clk_fout_epll.rate = epll;
+       clk_fout_vpll.rate = vpll;
+
+       printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
+                       "M=%ld, E=%ld V=%ld",
+                       apll, bpll, cpll, mpll, epll, vpll);
+
+       armclk = clk_get_rate(&exynos5_clk_armclk);
+       mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
+
+       aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
+       aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
+       aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
+       aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
+       aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
+       aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
+
+       printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
+                       "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
+                       "ACLK166=%ld, ACLK66=%ld\n",
+                       armclk, mout_cdrex, aclk_400,
+                       aclk_333, aclk_266, aclk_200,
+                       aclk_166, aclk_66);
+
+
+       clk_fout_epll.ops = &exynos5_epll_ops;
+
+       if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
+               printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+                               clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
+
+       clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
+       clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
+
+       clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
+       clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
+
+       for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
+               s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
+}
+
+void __init exynos5_register_clocks(void)
+{
+       int ptr;
+
+       s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
+
+       for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
+               s3c_register_clksrc(exynos5_sysclks[ptr], 1);
+
+       for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
+               s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
+
+       for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
+               s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
+
+       s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
+       s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
+
+       s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
+       for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
+               s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
+
+       s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
+       s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
+       clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
+
+       register_syscore_ops(&exynos5_clock_syscore_ops);
+       s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
deleted file mode 100644 (file)
index 187287a..0000000
+++ /dev/null
@@ -1,1564 +0,0 @@
-/* linux/arch/arm/mach-exynos4/clock.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * EXYNOS4 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/sysmmu.h>
-#include <mach/exynos4-clock.h>
-
-#include "common.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4_clock_save[] = {
-       SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
-       SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
-       SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
-       SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
-       SAVE_ITEM(S5P_CLKSRC_TOP0),
-       SAVE_ITEM(S5P_CLKSRC_TOP1),
-       SAVE_ITEM(S5P_CLKSRC_CAM),
-       SAVE_ITEM(S5P_CLKSRC_TV),
-       SAVE_ITEM(S5P_CLKSRC_MFC),
-       SAVE_ITEM(S5P_CLKSRC_G3D),
-       SAVE_ITEM(S5P_CLKSRC_LCD0),
-       SAVE_ITEM(S5P_CLKSRC_MAUDIO),
-       SAVE_ITEM(S5P_CLKSRC_FSYS),
-       SAVE_ITEM(S5P_CLKSRC_PERIL0),
-       SAVE_ITEM(S5P_CLKSRC_PERIL1),
-       SAVE_ITEM(S5P_CLKDIV_CAM),
-       SAVE_ITEM(S5P_CLKDIV_TV),
-       SAVE_ITEM(S5P_CLKDIV_MFC),
-       SAVE_ITEM(S5P_CLKDIV_G3D),
-       SAVE_ITEM(S5P_CLKDIV_LCD0),
-       SAVE_ITEM(S5P_CLKDIV_MAUDIO),
-       SAVE_ITEM(S5P_CLKDIV_FSYS0),
-       SAVE_ITEM(S5P_CLKDIV_FSYS1),
-       SAVE_ITEM(S5P_CLKDIV_FSYS2),
-       SAVE_ITEM(S5P_CLKDIV_FSYS3),
-       SAVE_ITEM(S5P_CLKDIV_PERIL0),
-       SAVE_ITEM(S5P_CLKDIV_PERIL1),
-       SAVE_ITEM(S5P_CLKDIV_PERIL2),
-       SAVE_ITEM(S5P_CLKDIV_PERIL3),
-       SAVE_ITEM(S5P_CLKDIV_PERIL4),
-       SAVE_ITEM(S5P_CLKDIV_PERIL5),
-       SAVE_ITEM(S5P_CLKDIV_TOP),
-       SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
-       SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
-       SAVE_ITEM(S5P_CLKSRC_MASK_TV),
-       SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
-       SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
-       SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
-       SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
-       SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
-       SAVE_ITEM(S5P_CLKDIV2_RATIO),
-       SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
-       SAVE_ITEM(S5P_CLKGATE_IP_CAM),
-       SAVE_ITEM(S5P_CLKGATE_IP_TV),
-       SAVE_ITEM(S5P_CLKGATE_IP_MFC),
-       SAVE_ITEM(S5P_CLKGATE_IP_G3D),
-       SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
-       SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
-       SAVE_ITEM(S5P_CLKGATE_IP_GPS),
-       SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
-       SAVE_ITEM(S5P_CLKGATE_BLOCK),
-       SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
-       SAVE_ITEM(S5P_CLKSRC_DMC),
-       SAVE_ITEM(S5P_CLKDIV_DMC0),
-       SAVE_ITEM(S5P_CLKDIV_DMC1),
-       SAVE_ITEM(S5P_CLKGATE_IP_DMC),
-       SAVE_ITEM(S5P_CLKSRC_CPU),
-       SAVE_ITEM(S5P_CLKDIV_CPU),
-       SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
-       SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
-       SAVE_ITEM(S5P_CLKGATE_IP_CPU),
-};
-#endif
-
-struct clk clk_sclk_hdmi27m = {
-       .name           = "sclk_hdmi27m",
-       .rate           = 27000000,
-};
-
-struct clk clk_sclk_hdmiphy = {
-       .name           = "sclk_hdmiphy",
-};
-
-struct clk clk_sclk_usbphy0 = {
-       .name           = "sclk_usbphy0",
-       .rate           = 27000000,
-};
-
-struct clk clk_sclk_usbphy1 = {
-       .name           = "sclk_usbphy1",
-};
-
-static struct clk dummy_apb_pclk = {
-       .name           = "apb_pclk",
-       .id             = -1,
-};
-
-static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
-}
-
-static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
-}
-
-static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
-}
-
-int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
-}
-
-static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
-}
-
-static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
-}
-
-static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
-}
-
-static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
-}
-
-static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
-}
-
-static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
-}
-
-int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
-}
-
-int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
-}
-
-static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
-}
-
-static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
-}
-
-static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-
-static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
-}
-
-/* Core list of CMU_CPU side */
-
-static struct clksrc_clk clk_mout_apll = {
-       .clk    = {
-               .name           = "mout_apll",
-       },
-       .sources        = &clk_src_apll,
-       .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
-};
-
-struct clksrc_clk clk_sclk_apll = {
-       .clk    = {
-               .name           = "sclk_apll",
-               .parent         = &clk_mout_apll.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
-};
-
-struct clksrc_clk clk_mout_epll = {
-       .clk    = {
-               .name           = "mout_epll",
-       },
-       .sources        = &clk_src_epll,
-       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
-};
-
-struct clksrc_clk clk_mout_mpll = {
-       .clk = {
-               .name           = "mout_mpll",
-       },
-       .sources        = &clk_src_mpll,
-
-       /* reg_src will be added in each SoCs' clock */
-};
-
-static struct clk *clkset_moutcore_list[] = {
-       [0] = &clk_mout_apll.clk,
-       [1] = &clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources clkset_moutcore = {
-       .sources        = clkset_moutcore_list,
-       .nr_sources     = ARRAY_SIZE(clkset_moutcore_list),
-};
-
-static struct clksrc_clk clk_moutcore = {
-       .clk    = {
-               .name           = "moutcore",
-       },
-       .sources        = &clkset_moutcore,
-       .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk clk_coreclk = {
-       .clk    = {
-               .name           = "core_clk",
-               .parent         = &clk_moutcore.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_armclk = {
-       .clk    = {
-               .name           = "armclk",
-               .parent         = &clk_coreclk.clk,
-       },
-};
-
-static struct clksrc_clk clk_aclk_corem0 = {
-       .clk    = {
-               .name           = "aclk_corem0",
-               .parent         = &clk_coreclk.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_cores = {
-       .clk    = {
-               .name           = "aclk_cores",
-               .parent         = &clk_coreclk.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_corem1 = {
-       .clk    = {
-               .name           = "aclk_corem1",
-               .parent         = &clk_coreclk.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk clk_periphclk = {
-       .clk    = {
-               .name           = "periphclk",
-               .parent         = &clk_coreclk.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
-};
-
-/* Core list of CMU_CORE side */
-
-struct clk *clkset_corebus_list[] = {
-       [0] = &clk_mout_mpll.clk,
-       [1] = &clk_sclk_apll.clk,
-};
-
-struct clksrc_sources clkset_mout_corebus = {
-       .sources        = clkset_corebus_list,
-       .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
-};
-
-static struct clksrc_clk clk_mout_corebus = {
-       .clk    = {
-               .name           = "mout_corebus",
-       },
-       .sources        = &clkset_mout_corebus,
-       .reg_src        = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk clk_sclk_dmc = {
-       .clk    = {
-               .name           = "sclk_dmc",
-               .parent         = &clk_mout_corebus.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_cored = {
-       .clk    = {
-               .name           = "aclk_cored",
-               .parent         = &clk_sclk_dmc.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_corep = {
-       .clk    = {
-               .name           = "aclk_corep",
-               .parent         = &clk_aclk_cored.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_acp = {
-       .clk    = {
-               .name           = "aclk_acp",
-               .parent         = &clk_mout_corebus.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_pclk_acp = {
-       .clk    = {
-               .name           = "pclk_acp",
-               .parent         = &clk_aclk_acp.clk,
-       },
-       .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
-};
-
-/* Core list of CMU_TOP side */
-
-struct clk *clkset_aclk_top_list[] = {
-       [0] = &clk_mout_mpll.clk,
-       [1] = &clk_sclk_apll.clk,
-};
-
-struct clksrc_sources clkset_aclk = {
-       .sources        = clkset_aclk_top_list,
-       .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
-};
-
-static struct clksrc_clk clk_aclk_200 = {
-       .clk    = {
-               .name           = "aclk_200",
-       },
-       .sources        = &clkset_aclk,
-       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
-       .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_100 = {
-       .clk    = {
-               .name           = "aclk_100",
-       },
-       .sources        = &clkset_aclk,
-       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
-       .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk clk_aclk_160 = {
-       .clk    = {
-               .name           = "aclk_160",
-       },
-       .sources        = &clkset_aclk,
-       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
-       .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
-};
-
-struct clksrc_clk clk_aclk_133 = {
-       .clk    = {
-               .name           = "aclk_133",
-       },
-       .sources        = &clkset_aclk,
-       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
-       .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
-};
-
-static struct clk *clkset_vpllsrc_list[] = {
-       [0] = &clk_fin_vpll,
-       [1] = &clk_sclk_hdmi27m,
-};
-
-static struct clksrc_sources clkset_vpllsrc = {
-       .sources        = clkset_vpllsrc_list,
-       .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
-};
-
-static struct clksrc_clk clk_vpllsrc = {
-       .clk    = {
-               .name           = "vpll_src",
-               .enable         = exynos4_clksrc_mask_top_ctrl,
-               .ctrlbit        = (1 << 0),
-       },
-       .sources        = &clkset_vpllsrc,
-       .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_sclk_vpll_list[] = {
-       [0] = &clk_vpllsrc.clk,
-       [1] = &clk_fout_vpll,
-};
-
-static struct clksrc_sources clkset_sclk_vpll = {
-       .sources        = clkset_sclk_vpll_list,
-       .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
-};
-
-struct clksrc_clk clk_sclk_vpll = {
-       .clk    = {
-               .name           = "sclk_vpll",
-       },
-       .sources        = &clkset_sclk_vpll,
-       .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
-};
-
-static struct clk init_clocks_off[] = {
-       {
-               .name           = "timers",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1<<24),
-       }, {
-               .name           = "csis",
-               .devname        = "s5p-mipi-csis.0",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 4),
-       }, {
-               .name           = "csis",
-               .devname        = "s5p-mipi-csis.1",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 5),
-       }, {
-               .name           = "fimc",
-               .devname        = "exynos4-fimc.0",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "fimc",
-               .devname        = "exynos4-fimc.1",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 1),
-       }, {
-               .name           = "fimc",
-               .devname        = "exynos4-fimc.2",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 2),
-       }, {
-               .name           = "fimc",
-               .devname        = "exynos4-fimc.3",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 3),
-       }, {
-               .name           = "fimd",
-               .devname        = "exynos4-fb.0",
-               .enable         = exynos4_clk_ip_lcd0_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.0",
-               .parent         = &clk_aclk_133.clk,
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 5),
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.1",
-               .parent         = &clk_aclk_133.clk,
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 6),
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.2",
-               .parent         = &clk_aclk_133.clk,
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 7),
-       }, {
-               .name           = "hsmmc",
-               .devname        = "s3c-sdhci.3",
-               .parent         = &clk_aclk_133.clk,
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 8),
-       }, {
-               .name           = "dwmmc",
-               .parent         = &clk_aclk_133.clk,
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 9),
-       }, {
-               .name           = "dac",
-               .devname        = "s5p-sdo",
-               .enable         = exynos4_clk_ip_tv_ctrl,
-               .ctrlbit        = (1 << 2),
-       }, {
-               .name           = "mixer",
-               .devname        = "s5p-mixer",
-               .enable         = exynos4_clk_ip_tv_ctrl,
-               .ctrlbit        = (1 << 1),
-       }, {
-               .name           = "vp",
-               .devname        = "s5p-mixer",
-               .enable         = exynos4_clk_ip_tv_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "hdmi",
-               .devname        = "exynos4-hdmi",
-               .enable         = exynos4_clk_ip_tv_ctrl,
-               .ctrlbit        = (1 << 3),
-       }, {
-               .name           = "hdmiphy",
-               .devname        = "exynos4-hdmi",
-               .enable         = exynos4_clk_hdmiphy_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "dacphy",
-               .devname        = "s5p-sdo",
-               .enable         = exynos4_clk_dac_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "adc",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 15),
-       }, {
-               .name           = "keypad",
-               .enable         = exynos4_clk_ip_perir_ctrl,
-               .ctrlbit        = (1 << 16),
-       }, {
-               .name           = "rtc",
-               .enable         = exynos4_clk_ip_perir_ctrl,
-               .ctrlbit        = (1 << 15),
-       }, {
-               .name           = "watchdog",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_perir_ctrl,
-               .ctrlbit        = (1 << 14),
-       }, {
-               .name           = "usbhost",
-               .enable         = exynos4_clk_ip_fsys_ctrl ,
-               .ctrlbit        = (1 << 12),
-       }, {
-               .name           = "otg",
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 13),
-       }, {
-               .name           = "spi",
-               .devname        = "s3c64xx-spi.0",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 16),
-       }, {
-               .name           = "spi",
-               .devname        = "s3c64xx-spi.1",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 17),
-       }, {
-               .name           = "spi",
-               .devname        = "s3c64xx-spi.2",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 18),
-       }, {
-               .name           = "iis",
-               .devname        = "samsung-i2s.0",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 19),
-       }, {
-               .name           = "iis",
-               .devname        = "samsung-i2s.1",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 20),
-       }, {
-               .name           = "iis",
-               .devname        = "samsung-i2s.2",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 21),
-       }, {
-               .name           = "ac97",
-               .devname        = "samsung-ac97",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 27),
-       }, {
-               .name           = "fimg2d",
-               .enable         = exynos4_clk_ip_image_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "mfc",
-               .devname        = "s5p-mfc",
-               .enable         = exynos4_clk_ip_mfc_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-i2c.0",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 6),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-i2c.1",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 7),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-i2c.2",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 8),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-i2c.3",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 9),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-i2c.4",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 10),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-i2c.5",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 11),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-i2c.6",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 12),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-i2c.7",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 13),
-       }, {
-               .name           = "i2c",
-               .devname        = "s3c2440-hdmiphy-i2c",
-               .parent         = &clk_aclk_100.clk,
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 14),
-       }, {
-               .name           = "SYSMMU_MDMA",
-               .enable         = exynos4_clk_ip_image_ctrl,
-               .ctrlbit        = (1 << 5),
-       }, {
-               .name           = "SYSMMU_FIMC0",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 7),
-       }, {
-               .name           = "SYSMMU_FIMC1",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 8),
-       }, {
-               .name           = "SYSMMU_FIMC2",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 9),
-       }, {
-               .name           = "SYSMMU_FIMC3",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 10),
-       }, {
-               .name           = "SYSMMU_JPEG",
-               .enable         = exynos4_clk_ip_cam_ctrl,
-               .ctrlbit        = (1 << 11),
-       }, {
-               .name           = "SYSMMU_FIMD0",
-               .enable         = exynos4_clk_ip_lcd0_ctrl,
-               .ctrlbit        = (1 << 4),
-       }, {
-               .name           = "SYSMMU_FIMD1",
-               .enable         = exynos4_clk_ip_lcd1_ctrl,
-               .ctrlbit        = (1 << 4),
-       }, {
-               .name           = "SYSMMU_PCIe",
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 18),
-       }, {
-               .name           = "SYSMMU_G2D",
-               .enable         = exynos4_clk_ip_image_ctrl,
-               .ctrlbit        = (1 << 3),
-       }, {
-               .name           = "SYSMMU_ROTATOR",
-               .enable         = exynos4_clk_ip_image_ctrl,
-               .ctrlbit        = (1 << 4),
-       }, {
-               .name           = "SYSMMU_TV",
-               .enable         = exynos4_clk_ip_tv_ctrl,
-               .ctrlbit        = (1 << 4),
-       }, {
-               .name           = "SYSMMU_MFC_L",
-               .enable         = exynos4_clk_ip_mfc_ctrl,
-               .ctrlbit        = (1 << 1),
-       }, {
-               .name           = "SYSMMU_MFC_R",
-               .enable         = exynos4_clk_ip_mfc_ctrl,
-               .ctrlbit        = (1 << 2),
-       }
-};
-
-static struct clk init_clocks[] = {
-       {
-               .name           = "uart",
-               .devname        = "s5pv210-uart.0",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "uart",
-               .devname        = "s5pv210-uart.1",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 1),
-       }, {
-               .name           = "uart",
-               .devname        = "s5pv210-uart.2",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 2),
-       }, {
-               .name           = "uart",
-               .devname        = "s5pv210-uart.3",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 3),
-       }, {
-               .name           = "uart",
-               .devname        = "s5pv210-uart.4",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 4),
-       }, {
-               .name           = "uart",
-               .devname        = "s5pv210-uart.5",
-               .enable         = exynos4_clk_ip_peril_ctrl,
-               .ctrlbit        = (1 << 5),
-       }
-};
-
-static struct clk clk_pdma0 = {
-       .name           = "dma",
-       .devname        = "dma-pl330.0",
-       .enable         = exynos4_clk_ip_fsys_ctrl,
-       .ctrlbit        = (1 << 0),
-};
-
-static struct clk clk_pdma1 = {
-       .name           = "dma",
-       .devname        = "dma-pl330.1",
-       .enable         = exynos4_clk_ip_fsys_ctrl,
-       .ctrlbit        = (1 << 1),
-};
-
-struct clk *clkset_group_list[] = {
-       [0] = &clk_ext_xtal_mux,
-       [1] = &clk_xusbxti,
-       [2] = &clk_sclk_hdmi27m,
-       [3] = &clk_sclk_usbphy0,
-       [4] = &clk_sclk_usbphy1,
-       [5] = &clk_sclk_hdmiphy,
-       [6] = &clk_mout_mpll.clk,
-       [7] = &clk_mout_epll.clk,
-       [8] = &clk_sclk_vpll.clk,
-};
-
-struct clksrc_sources clkset_group = {
-       .sources        = clkset_group_list,
-       .nr_sources     = ARRAY_SIZE(clkset_group_list),
-};
-
-static struct clk *clkset_mout_g2d0_list[] = {
-       [0] = &clk_mout_mpll.clk,
-       [1] = &clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources clkset_mout_g2d0 = {
-       .sources        = clkset_mout_g2d0_list,
-       .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
-};
-
-static struct clksrc_clk clk_mout_g2d0 = {
-       .clk    = {
-               .name           = "mout_g2d0",
-       },
-       .sources        = &clkset_mout_g2d0,
-       .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_mout_g2d1_list[] = {
-       [0] = &clk_mout_epll.clk,
-       [1] = &clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources clkset_mout_g2d1 = {
-       .sources        = clkset_mout_g2d1_list,
-       .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
-};
-
-static struct clksrc_clk clk_mout_g2d1 = {
-       .clk    = {
-               .name           = "mout_g2d1",
-       },
-       .sources        = &clkset_mout_g2d1,
-       .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
-};
-
-static struct clk *clkset_mout_g2d_list[] = {
-       [0] = &clk_mout_g2d0.clk,
-       [1] = &clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources clkset_mout_g2d = {
-       .sources        = clkset_mout_g2d_list,
-       .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
-};
-
-static struct clk *clkset_mout_mfc0_list[] = {
-       [0] = &clk_mout_mpll.clk,
-       [1] = &clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources clkset_mout_mfc0 = {
-       .sources        = clkset_mout_mfc0_list,
-       .nr_sources     = ARRAY_SIZE(clkset_mout_mfc0_list),
-};
-
-static struct clksrc_clk clk_mout_mfc0 = {
-       .clk    = {
-               .name           = "mout_mfc0",
-       },
-       .sources        = &clkset_mout_mfc0,
-       .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_mout_mfc1_list[] = {
-       [0] = &clk_mout_epll.clk,
-       [1] = &clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources clkset_mout_mfc1 = {
-       .sources        = clkset_mout_mfc1_list,
-       .nr_sources     = ARRAY_SIZE(clkset_mout_mfc1_list),
-};
-
-static struct clksrc_clk clk_mout_mfc1 = {
-       .clk    = {
-               .name           = "mout_mfc1",
-       },
-       .sources        = &clkset_mout_mfc1,
-       .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
-};
-
-static struct clk *clkset_mout_mfc_list[] = {
-       [0] = &clk_mout_mfc0.clk,
-       [1] = &clk_mout_mfc1.clk,
-};
-
-static struct clksrc_sources clkset_mout_mfc = {
-       .sources        = clkset_mout_mfc_list,
-       .nr_sources     = ARRAY_SIZE(clkset_mout_mfc_list),
-};
-
-static struct clk *clkset_sclk_dac_list[] = {
-       [0] = &clk_sclk_vpll.clk,
-       [1] = &clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources clkset_sclk_dac = {
-       .sources        = clkset_sclk_dac_list,
-       .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
-};
-
-static struct clksrc_clk clk_sclk_dac = {
-       .clk            = {
-               .name           = "sclk_dac",
-               .enable         = exynos4_clksrc_mask_tv_ctrl,
-               .ctrlbit        = (1 << 8),
-       },
-       .sources = &clkset_sclk_dac,
-       .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk clk_sclk_pixel = {
-       .clk            = {
-               .name           = "sclk_pixel",
-               .parent = &clk_sclk_vpll.clk,
-       },
-       .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
-};
-
-static struct clk *clkset_sclk_hdmi_list[] = {
-       [0] = &clk_sclk_pixel.clk,
-       [1] = &clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources clkset_sclk_hdmi = {
-       .sources        = clkset_sclk_hdmi_list,
-       .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
-};
-
-static struct clksrc_clk clk_sclk_hdmi = {
-       .clk            = {
-               .name           = "sclk_hdmi",
-               .enable         = exynos4_clksrc_mask_tv_ctrl,
-               .ctrlbit        = (1 << 0),
-       },
-       .sources = &clkset_sclk_hdmi,
-       .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_sclk_mixer_list[] = {
-       [0] = &clk_sclk_dac.clk,
-       [1] = &clk_sclk_hdmi.clk,
-};
-
-static struct clksrc_sources clkset_sclk_mixer = {
-       .sources        = clkset_sclk_mixer_list,
-       .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
-};
-
-static struct clksrc_clk clk_sclk_mixer = {
-       .clk            = {
-               .name           = "sclk_mixer",
-               .enable         = exynos4_clksrc_mask_tv_ctrl,
-               .ctrlbit        = (1 << 4),
-       },
-       .sources = &clkset_sclk_mixer,
-       .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk *sclk_tv[] = {
-       &clk_sclk_dac,
-       &clk_sclk_pixel,
-       &clk_sclk_hdmi,
-       &clk_sclk_mixer,
-};
-
-static struct clksrc_clk clk_dout_mmc0 = {
-       .clk            = {
-               .name           = "dout_mmc0",
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc1 = {
-       .clk            = {
-               .name           = "dout_mmc1",
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc2 = {
-       .clk            = {
-               .name           = "dout_mmc2",
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc3 = {
-       .clk            = {
-               .name           = "dout_mmc3",
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc4 = {
-       .clk            = {
-               .name           = "dout_mmc4",
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clksrcs[] = {
-       {
-               .clk            = {
-                       .name           = "sclk_pwm",
-                       .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                       .ctrlbit        = (1 << 24),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_csis",
-                       .devname        = "s5p-mipi-csis.0",
-                       .enable         = exynos4_clksrc_mask_cam_ctrl,
-                       .ctrlbit        = (1 << 24),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_csis",
-                       .devname        = "s5p-mipi-csis.1",
-                       .enable         = exynos4_clksrc_mask_cam_ctrl,
-                       .ctrlbit        = (1 << 28),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_cam0",
-                       .enable         = exynos4_clksrc_mask_cam_ctrl,
-                       .ctrlbit        = (1 << 16),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_cam1",
-                       .enable         = exynos4_clksrc_mask_cam_ctrl,
-                       .ctrlbit        = (1 << 20),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_fimc",
-                       .devname        = "exynos4-fimc.0",
-                       .enable         = exynos4_clksrc_mask_cam_ctrl,
-                       .ctrlbit        = (1 << 0),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_fimc",
-                       .devname        = "exynos4-fimc.1",
-                       .enable         = exynos4_clksrc_mask_cam_ctrl,
-                       .ctrlbit        = (1 << 4),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_fimc",
-                       .devname        = "exynos4-fimc.2",
-                       .enable         = exynos4_clksrc_mask_cam_ctrl,
-                       .ctrlbit        = (1 << 8),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_fimc",
-                       .devname        = "exynos4-fimc.3",
-                       .enable         = exynos4_clksrc_mask_cam_ctrl,
-                       .ctrlbit        = (1 << 12),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_fimd",
-                       .devname        = "exynos4-fb.0",
-                       .enable         = exynos4_clksrc_mask_lcd0_ctrl,
-                       .ctrlbit        = (1 << 0),
-               },
-               .sources = &clkset_group,
-               .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
-               .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_fimg2d",
-               },
-               .sources = &clkset_mout_g2d,
-               .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
-               .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_mfc",
-                       .devname        = "s5p-mfc",
-               },
-               .sources = &clkset_mout_mfc,
-               .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
-               .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
-       }, {
-               .clk            = {
-                       .name           = "sclk_dwmmc",
-                       .parent         = &clk_dout_mmc4.clk,
-                       .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                       .ctrlbit        = (1 << 16),
-               },
-               .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
-       }
-};
-
-static struct clksrc_clk clk_sclk_uart0 = {
-       .clk    = {
-               .name           = "uclk1",
-               .devname        = "exynos4210-uart.0",
-               .enable         = exynos4_clksrc_mask_peril0_ctrl,
-               .ctrlbit        = (1 << 0),
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uart1 = {
-       .clk            = {
-               .name           = "uclk1",
-               .devname        = "exynos4210-uart.1",
-               .enable         = exynos4_clksrc_mask_peril0_ctrl,
-               .ctrlbit        = (1 << 4),
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uart2 = {
-       .clk            = {
-               .name           = "uclk1",
-               .devname        = "exynos4210-uart.2",
-               .enable         = exynos4_clksrc_mask_peril0_ctrl,
-               .ctrlbit        = (1 << 8),
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uart3 = {
-       .clk            = {
-               .name           = "uclk1",
-               .devname        = "exynos4210-uart.3",
-               .enable         = exynos4_clksrc_mask_peril0_ctrl,
-               .ctrlbit        = (1 << 12),
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_mmc0 = {
-       .clk            = {
-               .name           = "sclk_mmc",
-               .devname        = "s3c-sdhci.0",
-               .parent         = &clk_dout_mmc0.clk,
-               .enable         = exynos4_clksrc_mask_fsys_ctrl,
-               .ctrlbit        = (1 << 0),
-       },
-       .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk clk_sclk_mmc1 = {
-       .clk            = {
-               .name           = "sclk_mmc",
-               .devname        = "s3c-sdhci.1",
-               .parent         = &clk_dout_mmc1.clk,
-               .enable         = exynos4_clksrc_mask_fsys_ctrl,
-               .ctrlbit        = (1 << 4),
-       },
-       .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk clk_sclk_mmc2 = {
-       .clk            = {
-               .name           = "sclk_mmc",
-               .devname        = "s3c-sdhci.2",
-               .parent         = &clk_dout_mmc2.clk,
-               .enable         = exynos4_clksrc_mask_fsys_ctrl,
-               .ctrlbit        = (1 << 8),
-       },
-       .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk clk_sclk_mmc3 = {
-       .clk            = {
-               .name           = "sclk_mmc",
-               .devname        = "s3c-sdhci.3",
-               .parent         = &clk_dout_mmc3.clk,
-               .enable         = exynos4_clksrc_mask_fsys_ctrl,
-               .ctrlbit        = (1 << 12),
-       },
-       .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk clk_sclk_spi0 = {
-       .clk            = {
-               .name           = "sclk_spi",
-               .devname                = "s3c64xx-spi.0",
-               .enable         = exynos4_clksrc_mask_peril1_ctrl,
-               .ctrlbit                = (1 << 16),
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_spi1 = {
-       .clk            = {
-               .name           = "sclk_spi",
-               .devname                = "s3c64xx-spi.1",
-               .enable         = exynos4_clksrc_mask_peril1_ctrl,
-               .ctrlbit                = (1 << 20),
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_spi2 = {
-       .clk            = {
-               .name           = "sclk_spi",
-               .devname                = "s3c64xx-spi.2",
-               .enable         = exynos4_clksrc_mask_peril1_ctrl,
-               .ctrlbit                = (1 << 24),
-       },
-       .sources = &clkset_group,
-       .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
-       .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *sysclks[] = {
-       &clk_mout_apll,
-       &clk_sclk_apll,
-       &clk_mout_epll,
-       &clk_mout_mpll,
-       &clk_moutcore,
-       &clk_coreclk,
-       &clk_armclk,
-       &clk_aclk_corem0,
-       &clk_aclk_cores,
-       &clk_aclk_corem1,
-       &clk_periphclk,
-       &clk_mout_corebus,
-       &clk_sclk_dmc,
-       &clk_aclk_cored,
-       &clk_aclk_corep,
-       &clk_aclk_acp,
-       &clk_pclk_acp,
-       &clk_vpllsrc,
-       &clk_sclk_vpll,
-       &clk_aclk_200,
-       &clk_aclk_100,
-       &clk_aclk_160,
-       &clk_aclk_133,
-       &clk_dout_mmc0,
-       &clk_dout_mmc1,
-       &clk_dout_mmc2,
-       &clk_dout_mmc3,
-       &clk_dout_mmc4,
-       &clk_mout_mfc0,
-       &clk_mout_mfc1,
-};
-
-static struct clk *clk_cdev[] = {
-       &clk_pdma0,
-       &clk_pdma1,
-};
-
-static struct clksrc_clk *clksrc_cdev[] = {
-       &clk_sclk_uart0,
-       &clk_sclk_uart1,
-       &clk_sclk_uart2,
-       &clk_sclk_uart3,
-       &clk_sclk_mmc0,
-       &clk_sclk_mmc1,
-       &clk_sclk_mmc2,
-       &clk_sclk_mmc3,
-       &clk_sclk_spi0,
-       &clk_sclk_spi1,
-       &clk_sclk_spi2,
-
-};
-
-static struct clk_lookup exynos4_clk_lookup[] = {
-       CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
-       CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
-       CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
-       CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
-       CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
-       CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
-       CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
-       CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
-       CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
-       CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
-       CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
-       CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
-       CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
-};
-
-static int xtal_rate;
-
-static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
-{
-       if (soc_is_exynos4210())
-               return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
-                                       pll_4508);
-       else if (soc_is_exynos4212() || soc_is_exynos4412())
-               return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
-       else
-               return 0;
-}
-
-static struct clk_ops exynos4_fout_apll_ops = {
-       .get_rate = exynos4_fout_apll_get_rate,
-};
-
-static u32 vpll_div[][8] = {
-       {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
-       { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
-};
-
-static unsigned long exynos4_vpll_get_rate(struct clk *clk)
-{
-       return clk->rate;
-}
-
-static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
-{
-       unsigned int vpll_con0, vpll_con1 = 0;
-       unsigned int i;
-
-       /* Return if nothing changed */
-       if (clk->rate == rate)
-               return 0;
-
-       vpll_con0 = __raw_readl(S5P_VPLL_CON0);
-       vpll_con0 &= ~(0x1 << 27 |                                      \
-                       PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
-                       PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
-                       PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-
-       vpll_con1 = __raw_readl(S5P_VPLL_CON1);
-       vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
-                       PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
-                       PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
-
-       for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
-               if (vpll_div[i][0] == rate) {
-                       vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
-                       vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
-                       vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
-                       vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
-                       vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
-                       vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
-                       vpll_con0 |= vpll_div[i][7] << 27;
-                       break;
-               }
-       }
-
-       if (i == ARRAY_SIZE(vpll_div)) {
-               printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
-                               __func__);
-               return -EINVAL;
-       }
-
-       __raw_writel(vpll_con0, S5P_VPLL_CON0);
-       __raw_writel(vpll_con1, S5P_VPLL_CON1);
-
-       /* Wait for VPLL lock */
-       while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
-               continue;
-
-       clk->rate = rate;
-       return 0;
-}
-
-static struct clk_ops exynos4_vpll_ops = {
-       .get_rate = exynos4_vpll_get_rate,
-       .set_rate = exynos4_vpll_set_rate,
-};
-
-void __init_or_cpufreq exynos4_setup_clocks(void)
-{
-       struct clk *xtal_clk;
-       unsigned long apll = 0;
-       unsigned long mpll = 0;
-       unsigned long epll = 0;
-       unsigned long vpll = 0;
-       unsigned long vpllsrc;
-       unsigned long xtal;
-       unsigned long armclk;
-       unsigned long sclk_dmc;
-       unsigned long aclk_200;
-       unsigned long aclk_100;
-       unsigned long aclk_160;
-       unsigned long aclk_133;
-       unsigned int ptr;
-
-       printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-       xtal_clk = clk_get(NULL, "xtal");
-       BUG_ON(IS_ERR(xtal_clk));
-
-       xtal = clk_get_rate(xtal_clk);
-
-       xtal_rate = xtal;
-
-       clk_put(xtal_clk);
-
-       printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-       if (soc_is_exynos4210()) {
-               apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
-                                       pll_4508);
-               mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
-                                       pll_4508);
-               epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
-                                       __raw_readl(S5P_EPLL_CON1), pll_4600);
-
-               vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
-               vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
-                                       __raw_readl(S5P_VPLL_CON1), pll_4650c);
-       } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-               apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
-               mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
-               epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
-                                       __raw_readl(S5P_EPLL_CON1));
-
-               vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
-               vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
-                                       __raw_readl(S5P_VPLL_CON1));
-       } else {
-               /* nothing */
-       }
-
-       clk_fout_apll.ops = &exynos4_fout_apll_ops;
-       clk_fout_mpll.rate = mpll;
-       clk_fout_epll.rate = epll;
-       clk_fout_vpll.ops = &exynos4_vpll_ops;
-       clk_fout_vpll.rate = vpll;
-
-       printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
-                       apll, mpll, epll, vpll);
-
-       armclk = clk_get_rate(&clk_armclk.clk);
-       sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
-
-       aclk_200 = clk_get_rate(&clk_aclk_200.clk);
-       aclk_100 = clk_get_rate(&clk_aclk_100.clk);
-       aclk_160 = clk_get_rate(&clk_aclk_160.clk);
-       aclk_133 = clk_get_rate(&clk_aclk_133.clk);
-
-       printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
-                        "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
-                       armclk, sclk_dmc, aclk_200,
-                       aclk_100, aclk_160, aclk_133);
-
-       clk_f.rate = armclk;
-       clk_h.rate = sclk_dmc;
-       clk_p.rate = aclk_100;
-
-       for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-               s3c_set_clksrc(&clksrcs[ptr], true);
-}
-
-static struct clk *clks[] __initdata = {
-       &clk_sclk_hdmi27m,
-       &clk_sclk_hdmiphy,
-       &clk_sclk_usbphy0,
-       &clk_sclk_usbphy1,
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4_clock_suspend(void)
-{
-       s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-       return 0;
-}
-
-static void exynos4_clock_resume(void)
-{
-       s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-}
-
-#else
-#define exynos4_clock_suspend NULL
-#define exynos4_clock_resume NULL
-#endif
-
-struct syscore_ops exynos4_clock_syscore_ops = {
-       .suspend        = exynos4_clock_suspend,
-       .resume         = exynos4_clock_resume,
-};
-
-void __init exynos4_register_clocks(void)
-{
-       int ptr;
-
-       s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-
-       for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-               s3c_register_clksrc(sysclks[ptr], 1);
-
-       for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
-               s3c_register_clksrc(sclk_tv[ptr], 1);
-
-       for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
-               s3c_register_clksrc(clksrc_cdev[ptr], 1);
-
-       s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-       s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-
-       s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
-       for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
-               s3c_disable_clocks(clk_cdev[ptr], 1);
-
-       s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-       s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-       clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
-
-       register_syscore_ops(&exynos4_clock_syscore_ops);
-       s3c24xx_register_clock(&dummy_apb_pclk);
-
-       s3c_pwmclk_init();
-}
index 031c1e5..cbbaca5 100644 (file)
 static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
 static const char name_exynos4412[] = "EXYNOS4412";
+static const char name_exynos5250[] = "EXYNOS5250";
+
+static void exynos4_map_io(void);
+static void exynos5_map_io(void);
+static void exynos4_init_clocks(int xtal);
+static void exynos5_init_clocks(int xtal);
+static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+static int exynos_init(void);
 
 static struct cpu_table cpu_ids[] __initdata = {
        {
@@ -56,7 +64,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idmask         = EXYNOS4_CPU_MASK,
                .map_io         = exynos4_map_io,
                .init_clocks    = exynos4_init_clocks,
-               .init_uarts     = exynos4_init_uarts,
+               .init_uarts     = exynos_init_uarts,
                .init           = exynos_init,
                .name           = name_exynos4210,
        }, {
@@ -64,7 +72,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idmask         = EXYNOS4_CPU_MASK,
                .map_io         = exynos4_map_io,
                .init_clocks    = exynos4_init_clocks,
-               .init_uarts     = exynos4_init_uarts,
+               .init_uarts     = exynos_init_uarts,
                .init           = exynos_init,
                .name           = name_exynos4212,
        }, {
@@ -72,9 +80,17 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idmask         = EXYNOS4_CPU_MASK,
                .map_io         = exynos4_map_io,
                .init_clocks    = exynos4_init_clocks,
-               .init_uarts     = exynos4_init_uarts,
+               .init_uarts     = exynos_init_uarts,
                .init           = exynos_init,
                .name           = name_exynos4412,
+       }, {
+               .idcode         = EXYNOS5250_SOC_ID,
+               .idmask         = EXYNOS5_SOC_MASK,
+               .map_io         = exynos5_map_io,
+               .init_clocks    = exynos5_init_clocks,
+               .init_uarts     = exynos_init_uarts,
+               .init           = exynos_init,
+               .name           = name_exynos5250,
        },
 };
 
@@ -83,10 +99,14 @@ static struct cpu_table cpu_ids[] __initdata = {
 static struct map_desc exynos_iodesc[] __initdata = {
        {
                .virtual        = (unsigned long)S5P_VA_CHIPID,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_CHIPID),
+               .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
-       }, {
+       },
+};
+
+static struct map_desc exynos4_iodesc[] __initdata = {
+       {
                .virtual        = (unsigned long)S3C_VA_SYS,
                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
                .length         = SZ_64K,
@@ -136,11 +156,7 @@ static struct map_desc exynos_iodesc[] __initdata = {
                .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
                .length         = SZ_512K,
                .type           = MT_DEVICE,
-       },
-};
-
-static struct map_desc exynos4_iodesc[] __initdata = {
-       {
+       }, {
                .virtual        = (unsigned long)S5P_VA_CMU,
                .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
                .length         = SZ_128K,
@@ -201,11 +217,80 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
        },
 };
 
+static struct map_desc exynos5_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S3C_VA_SYS,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_TIMER,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
+               .length         = SZ_16K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_WATCHDOG,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SROMC,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SYSTIMER,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_CMU,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
+               .length         = 144 * SZ_1K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_PMU,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_COMBINER),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_UART,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
+               .length         = SZ_512K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GIC_CPU,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GIC_DIST,
+               .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       },
+};
+
 void exynos4_restart(char mode, const char *cmd)
 {
        __raw_writel(0x1, S5P_SWRESET);
 }
 
+void exynos5_restart(char mode, const char *cmd)
+{
+       __raw_writel(0x1, EXYNOS_SWRESET);
+}
+
 /*
  * exynos_map_io
  *
@@ -225,7 +310,7 @@ void __init exynos_init_io(struct map_desc *mach_desc, int size)
        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 }
 
-void __init exynos4_map_io(void)
+static void __init exynos4_map_io(void)
 {
        iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 
@@ -256,7 +341,22 @@ void __init exynos4_map_io(void)
        s5p_hdmi_setname("exynos4-hdmi");
 }
 
-void __init exynos4_init_clocks(int xtal)
+static void __init exynos5_map_io(void)
+{
+       iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
+
+       s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
+       s3c_device_i2c0.resource[0].end   = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
+       s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
+       s3c_device_i2c0.resource[1].end   = EXYNOS5_IRQ_IIC;
+
+       /* The I2C bus controllers are directly compatible with s3c2440 */
+       s3c_i2c0_setname("s3c2440-i2c");
+       s3c_i2c1_setname("s3c2440-i2c");
+       s3c_i2c2_setname("s3c2440-i2c");
+}
+
+static void __init exynos4_init_clocks(int xtal)
 {
        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 
@@ -272,6 +372,17 @@ void __init exynos4_init_clocks(int xtal)
        exynos4_setup_clocks();
 }
 
+static void __init exynos5_init_clocks(int xtal)
+{
+       printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+       s3c24xx_register_baseclocks(xtal);
+       s5p_register_clocks(xtal);
+
+       exynos5_register_clocks();
+       exynos5_setup_clocks();
+}
+
 #define COMBINER_ENABLE_SET    0x0
 #define COMBINER_ENABLE_CLEAR  0x4
 #define COMBINER_INT_STATUS    0xC
@@ -345,7 +456,14 @@ static struct irq_chip combiner_chip = {
 
 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
 {
-       if (combiner_nr >= MAX_COMBINER_NR)
+       unsigned int max_nr;
+
+       if (soc_is_exynos5250())
+               max_nr = EXYNOS5_MAX_COMBINER_NR;
+       else
+               max_nr = EXYNOS4_MAX_COMBINER_NR;
+
+       if (combiner_nr >= max_nr)
                BUG();
        if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
                BUG();
@@ -356,8 +474,14 @@ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
                          unsigned int irq_start)
 {
        unsigned int i;
+       unsigned int max_nr;
+
+       if (soc_is_exynos5250())
+               max_nr = EXYNOS5_MAX_COMBINER_NR;
+       else
+               max_nr = EXYNOS4_MAX_COMBINER_NR;
 
-       if (combiner_nr >= MAX_COMBINER_NR)
+       if (combiner_nr >= max_nr)
                BUG();
 
        combiner_data[combiner_nr].base = base;
@@ -400,8 +524,28 @@ void __init exynos4_init_irq(void)
                of_irq_init(exynos4_dt_irq_match);
 #endif
 
-       for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+       for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
+
+               combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
+                               COMBINER_IRQ(irq, 0));
+               combiner_cascade_irq(irq, IRQ_SPI(irq));
+       }
+
+       /*
+        * The parameters of s5p_init_irq() are for VIC init.
+        * Theses parameters should be NULL and 0 because EXYNOS4
+        * uses GIC instead of VIC.
+        */
+       s5p_init_irq(NULL, 0);
+}
+
+void __init exynos5_init_irq(void)
+{
+       int irq;
+
+       gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 
+       for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
                combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
                                COMBINER_IRQ(irq, 0));
                combiner_cascade_irq(irq, IRQ_SPI(irq));
@@ -420,19 +564,34 @@ struct bus_type exynos4_subsys = {
        .dev_name       = "exynos4-core",
 };
 
+struct bus_type exynos5_subsys = {
+       .name           = "exynos5-core",
+       .dev_name       = "exynos5-core",
+};
+
 static struct device exynos4_dev = {
        .bus    = &exynos4_subsys,
 };
 
-static int __init exynos4_core_init(void)
+static struct device exynos5_dev = {
+       .bus    = &exynos5_subsys,
+};
+
+static int __init exynos_core_init(void)
 {
-       return subsys_system_register(&exynos4_subsys, NULL);
+       if (soc_is_exynos5250())
+               return subsys_system_register(&exynos5_subsys, NULL);
+       else
+               return subsys_system_register(&exynos4_subsys, NULL);
 }
-core_initcall(exynos4_core_init);
+core_initcall(exynos_core_init);
 
 #ifdef CONFIG_CACHE_L2X0
 static int __init exynos4_l2x0_cache_init(void)
 {
+       if (soc_is_exynos5250())
+               return 0;
+
        /* TAG, Data Latency Control: 2cycle */
        __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 
@@ -452,19 +611,47 @@ static int __init exynos4_l2x0_cache_init(void)
 
        return 0;
 }
-
 early_initcall(exynos4_l2x0_cache_init);
 #endif
 
-int __init exynos_init(void)
+static int __init exynos5_l2_cache_init(void)
+{
+       unsigned int val;
+
+       if (!soc_is_exynos5250())
+               return 0;
+
+       asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
+                    "bic %0, %0, #(1 << 2)\n"  /* cache disable */
+                    "mcr p15, 0, %0, c1, c0, 0\n"
+                    "mrc p15, 1, %0, c9, c0, 2\n"
+                    : "=r"(val));
+
+       val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
+
+       asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
+       asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
+                    "orr %0, %0, #(1 << 2)\n"  /* cache enable */
+                    "mcr p15, 0, %0, c1, c0, 0\n"
+                    : : "r"(val));
+
+       return 0;
+}
+early_initcall(exynos5_l2_cache_init);
+
+static int __init exynos_init(void)
 {
        printk(KERN_INFO "EXYNOS: Initializing architecture\n");
-       return device_register(&exynos4_dev);
+
+       if (soc_is_exynos5250())
+               return device_register(&exynos5_dev);
+       else
+               return device_register(&exynos4_dev);
 }
 
 /* uart registration process */
 
-void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
        struct s3c2410_uartcfg *tcfg = cfg;
        u32 ucnt;
@@ -472,69 +659,138 @@ void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
        for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
                tcfg->has_fracval = 1;
 
-       s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
+       if (soc_is_exynos5250())
+               s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
+       else
+               s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 }
 
+static void __iomem *exynos_eint_base;
+
 static DEFINE_SPINLOCK(eint_lock);
 
 static unsigned int eint0_15_data[16];
 
-static unsigned int exynos4_get_irq_nr(unsigned int number)
+static inline int exynos4_irq_to_gpio(unsigned int irq)
 {
-       u32 ret = 0;
+       if (irq < IRQ_EINT(0))
+               return -EINVAL;
 
-       switch (number) {
-       case 0 ... 3:
-               ret = (number + IRQ_EINT0);
-               break;
-       case 4 ... 7:
-               ret = (number + (IRQ_EINT4 - 4));
-               break;
-       case 8 ... 15:
-               ret = (number + (IRQ_EINT8 - 8));
-               break;
-       default:
-               printk(KERN_ERR "number available : %d\n", number);
-       }
+       irq -= IRQ_EINT(0);
+       if (irq < 8)
+               return EXYNOS4_GPX0(irq);
+
+       irq -= 8;
+       if (irq < 8)
+               return EXYNOS4_GPX1(irq);
+
+       irq -= 8;
+       if (irq < 8)
+               return EXYNOS4_GPX2(irq);
 
-       return ret;
+       irq -= 8;
+       if (irq < 8)
+               return EXYNOS4_GPX3(irq);
+
+       return -EINVAL;
 }
 
-static inline void exynos4_irq_eint_mask(struct irq_data *data)
+static inline int exynos5_irq_to_gpio(unsigned int irq)
+{
+       if (irq < IRQ_EINT(0))
+               return -EINVAL;
+
+       irq -= IRQ_EINT(0);
+       if (irq < 8)
+               return EXYNOS5_GPX0(irq);
+
+       irq -= 8;
+       if (irq < 8)
+               return EXYNOS5_GPX1(irq);
+
+       irq -= 8;
+       if (irq < 8)
+               return EXYNOS5_GPX2(irq);
+
+       irq -= 8;
+       if (irq < 8)
+               return EXYNOS5_GPX3(irq);
+
+       return -EINVAL;
+}
+
+static unsigned int exynos4_eint0_15_src_int[16] = {
+       EXYNOS4_IRQ_EINT0,
+       EXYNOS4_IRQ_EINT1,
+       EXYNOS4_IRQ_EINT2,
+       EXYNOS4_IRQ_EINT3,
+       EXYNOS4_IRQ_EINT4,
+       EXYNOS4_IRQ_EINT5,
+       EXYNOS4_IRQ_EINT6,
+       EXYNOS4_IRQ_EINT7,
+       EXYNOS4_IRQ_EINT8,
+       EXYNOS4_IRQ_EINT9,
+       EXYNOS4_IRQ_EINT10,
+       EXYNOS4_IRQ_EINT11,
+       EXYNOS4_IRQ_EINT12,
+       EXYNOS4_IRQ_EINT13,
+       EXYNOS4_IRQ_EINT14,
+       EXYNOS4_IRQ_EINT15,
+};
+
+static unsigned int exynos5_eint0_15_src_int[16] = {
+       EXYNOS5_IRQ_EINT0,
+       EXYNOS5_IRQ_EINT1,
+       EXYNOS5_IRQ_EINT2,
+       EXYNOS5_IRQ_EINT3,
+       EXYNOS5_IRQ_EINT4,
+       EXYNOS5_IRQ_EINT5,
+       EXYNOS5_IRQ_EINT6,
+       EXYNOS5_IRQ_EINT7,
+       EXYNOS5_IRQ_EINT8,
+       EXYNOS5_IRQ_EINT9,
+       EXYNOS5_IRQ_EINT10,
+       EXYNOS5_IRQ_EINT11,
+       EXYNOS5_IRQ_EINT12,
+       EXYNOS5_IRQ_EINT13,
+       EXYNOS5_IRQ_EINT14,
+       EXYNOS5_IRQ_EINT15,
+};
+static inline void exynos_irq_eint_mask(struct irq_data *data)
 {
        u32 mask;
 
        spin_lock(&eint_lock);
-       mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-       mask |= eint_irq_to_bit(data->irq);
-       __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+       mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
+       mask |= EINT_OFFSET_BIT(data->irq);
+       __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
        spin_unlock(&eint_lock);
 }
 
-static void exynos4_irq_eint_unmask(struct irq_data *data)
+static void exynos_irq_eint_unmask(struct irq_data *data)
 {
        u32 mask;
 
        spin_lock(&eint_lock);
-       mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-       mask &= ~(eint_irq_to_bit(data->irq));
-       __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+       mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
+       mask &= ~(EINT_OFFSET_BIT(data->irq));
+       __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
        spin_unlock(&eint_lock);
 }
 
-static inline void exynos4_irq_eint_ack(struct irq_data *data)
+static inline void exynos_irq_eint_ack(struct irq_data *data)
 {
-       __raw_writel(eint_irq_to_bit(data->irq),
-                    S5P_EINT_PEND(EINT_REG_NR(data->irq)));
+       __raw_writel(EINT_OFFSET_BIT(data->irq),
+                    EINT_PEND(exynos_eint_base, data->irq));
 }
 
-static void exynos4_irq_eint_maskack(struct irq_data *data)
+static void exynos_irq_eint_maskack(struct irq_data *data)
 {
-       exynos4_irq_eint_mask(data);
-       exynos4_irq_eint_ack(data);
+       exynos_irq_eint_mask(data);
+       exynos_irq_eint_ack(data);
 }
 
-static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
+static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 {
        int offs = EINT_OFFSET(data->irq);
        int shift;
@@ -571,39 +827,27 @@ static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
        mask = 0x7 << shift;
 
        spin_lock(&eint_lock);
-       ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
+       ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
        ctrl &= ~mask;
        ctrl |= newvalue << shift;
-       __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
+       __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
        spin_unlock(&eint_lock);
 
-       switch (offs) {
-       case 0 ... 7:
-               s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
-               break;
-       case 8 ... 15:
-               s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
-               break;
-       case 16 ... 23:
-               s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
-               break;
-       case 24 ... 31:
-               s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
-               break;
-       default:
-               printk(KERN_ERR "No such irq number %d", offs);
-       }
+       if (soc_is_exynos5250())
+               s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
+       else
+               s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 
        return 0;
 }
 
-static struct irq_chip exynos4_irq_eint = {
-       .name           = "exynos4-eint",
-       .irq_mask       = exynos4_irq_eint_mask,
-       .irq_unmask     = exynos4_irq_eint_unmask,
-       .irq_mask_ack   = exynos4_irq_eint_maskack,
-       .irq_ack        = exynos4_irq_eint_ack,
-       .irq_set_type   = exynos4_irq_eint_set_type,
+static struct irq_chip exynos_irq_eint = {
+       .name           = "exynos-eint",
+       .irq_mask       = exynos_irq_eint_mask,
+       .irq_unmask     = exynos_irq_eint_unmask,
+       .irq_mask_ack   = exynos_irq_eint_maskack,
+       .irq_ack        = exynos_irq_eint_ack,
+       .irq_set_type   = exynos_irq_eint_set_type,
 #ifdef CONFIG_PM
        .irq_set_wake   = s3c_irqext_wake,
 #endif
@@ -618,12 +862,12 @@ static struct irq_chip exynos4_irq_eint = {
  *
  * Each EINT pend/mask registers handle eight of them.
  */
-static inline void exynos4_irq_demux_eint(unsigned int start)
+static inline void exynos_irq_demux_eint(unsigned int start)
 {
        unsigned int irq;
 
-       u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
-       u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+       u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
+       u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 
        status &= ~mask;
        status &= 0xff;
@@ -635,16 +879,16 @@ static inline void exynos4_irq_demux_eint(unsigned int start)
        }
 }
 
-static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 {
        struct irq_chip *chip = irq_get_chip(irq);
        chained_irq_enter(chip, desc);
-       exynos4_irq_demux_eint(IRQ_EINT(16));
-       exynos4_irq_demux_eint(IRQ_EINT(24));
+       exynos_irq_demux_eint(IRQ_EINT(16));
+       exynos_irq_demux_eint(IRQ_EINT(24));
        chained_irq_exit(chip, desc);
 }
 
-static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
+static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 {
        u32 *irq_data = irq_get_handler_data(irq);
        struct irq_chip *chip = irq_get_chip(irq);
@@ -661,27 +905,44 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
        chained_irq_exit(chip, desc);
 }
 
-int __init exynos4_init_irq_eint(void)
+static int __init exynos_init_irq_eint(void)
 {
        int irq;
 
+       if (soc_is_exynos5250())
+               exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
+       else
+               exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
+
+       if (exynos_eint_base == NULL) {
+               pr_err("unable to ioremap for EINT base address\n");
+               return -ENOMEM;
+       }
+
        for (irq = 0 ; irq <= 31 ; irq++) {
-               irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
+               irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
                                         handle_level_irq);
                set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
        }
 
-       irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
+       irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 
        for (irq = 0 ; irq <= 15 ; irq++) {
                eint0_15_data[irq] = IRQ_EINT(irq);
 
-               irq_set_handler_data(exynos4_get_irq_nr(irq),
-                                    &eint0_15_data[irq]);
-               irq_set_chained_handler(exynos4_get_irq_nr(irq),
-                                       exynos4_irq_eint0_15);
+               if (soc_is_exynos5250()) {
+                       irq_set_handler_data(exynos5_eint0_15_src_int[irq],
+                                            &eint0_15_data[irq]);
+                       irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
+                                               exynos_irq_eint0_15);
+               } else {
+                       irq_set_handler_data(exynos4_eint0_15_src_int[irq],
+                                            &eint0_15_data[irq]);
+                       irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
+                                               exynos_irq_eint0_15);
+               }
        }
 
        return 0;
 }
-arch_initcall(exynos4_init_irq_eint);
+arch_initcall(exynos_init_irq_eint);
index 1ac49de..677b546 100644 (file)
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
+extern struct sys_timer exynos4_timer;
+
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
+void exynos5_init_irq(void);
+void exynos4_restart(char mode, const char *cmd);
+void exynos5_restart(char mode, const char *cmd);
 
+#ifdef CONFIG_ARCH_EXYNOS4
 void exynos4_register_clocks(void);
 void exynos4_setup_clocks(void);
 
-void exynos4210_register_clocks(void);
-void exynos4212_register_clocks(void);
+#else
+#define exynos4_register_clocks()
+#define exynos4_setup_clocks()
+#endif
 
-void exynos4_restart(char mode, const char *cmd);
+#ifdef CONFIG_ARCH_EXYNOS5
+void exynos5_register_clocks(void);
+void exynos5_setup_clocks(void);
 
-extern struct sys_timer exynos4_timer;
+#else
+#define exynos5_register_clocks()
+#define exynos5_setup_clocks()
+#endif
+
+#ifdef CONFIG_CPU_EXYNOS4210
+void exynos4210_register_clocks(void);
 
-#ifdef CONFIG_ARCH_EXYNOS
-extern  int exynos_init(void);
-extern void exynos4_map_io(void);
-extern void exynos4_init_clocks(int xtal);
-extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+#else
+#define exynos4210_register_clocks()
+#endif
+
+#ifdef CONFIG_SOC_EXYNOS4212
+void exynos4212_register_clocks(void);
 
 #else
-#define exynos4_init_clocks NULL
-#define exynos4_init_uarts NULL
-#define exynos4_map_io NULL
-#define exynos_init NULL
+#define exynos4212_register_clocks()
 #endif
 
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
index f57a3de..50ce5b0 100644 (file)
@@ -242,8 +242,8 @@ static struct resource exynos4_ahci_resource[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = IRQ_SATA,
-               .end    = IRQ_SATA,
+               .start  = EXYNOS4_IRQ_SATA,
+               .end    = EXYNOS4_IRQ_SATA,
                .flags  = IORESOURCE_IRQ,
        },
 };
index 5a9f9c2..7199e1a 100644 (file)
@@ -304,8 +304,8 @@ static struct resource exynos4_ac97_resource[] = {
                .flags  = IORESOURCE_DMA,
        },
        [4] = {
-               .start  = IRQ_AC97,
-               .end    = IRQ_AC97,
+               .start  = EXYNOS4_IRQ_AC97,
+               .end    = EXYNOS4_IRQ_AC97,
                .flags  = IORESOURCE_IRQ,
        },
 };
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
new file mode 100644 (file)
index 0000000..2e85c02
--- /dev/null
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Base EXYNOS UART resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+
+#define EXYNOS_UART_RESOURCE(_series, _nr)     \
+static struct resource exynos##_series##_uart##_nr##_resource[] = {    \
+       [0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART),        \
+       [1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr),  \
+};
+
+EXYNOS_UART_RESOURCE(4, 0)
+EXYNOS_UART_RESOURCE(4, 1)
+EXYNOS_UART_RESOURCE(4, 2)
+EXYNOS_UART_RESOURCE(4, 3)
+
+struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
+       [0] = {
+               .resources      = exynos4_uart0_resource,
+               .nr_resources   = ARRAY_SIZE(exynos4_uart0_resource),
+       },
+       [1] = {
+               .resources      = exynos4_uart1_resource,
+               .nr_resources   = ARRAY_SIZE(exynos4_uart1_resource),
+       },
+       [2] = {
+               .resources      = exynos4_uart2_resource,
+               .nr_resources   = ARRAY_SIZE(exynos4_uart2_resource),
+       },
+       [3] = {
+               .resources      = exynos4_uart3_resource,
+               .nr_resources   = ARRAY_SIZE(exynos4_uart3_resource),
+       },
+};
+
+EXYNOS_UART_RESOURCE(5, 0)
+EXYNOS_UART_RESOURCE(5, 1)
+EXYNOS_UART_RESOURCE(5, 2)
+EXYNOS_UART_RESOURCE(5, 3)
+
+struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
+       [0] = {
+               .resources      = exynos5_uart0_resource,
+               .nr_resources   = ARRAY_SIZE(exynos5_uart0_resource),
+       },
+       [1] = {
+               .resources      = exynos5_uart1_resource,
+               .nr_resources   = ARRAY_SIZE(exynos5_uart0_resource),
+       },
+       [2] = {
+               .resources      = exynos5_uart2_resource,
+               .nr_resources   = ARRAY_SIZE(exynos5_uart2_resource),
+       },
+       [3] = {
+               .resources      = exynos5_uart3_resource,
+               .nr_resources   = ARRAY_SIZE(exynos5_uart3_resource),
+       },
+};
index 91370de..3983abe 100644 (file)
@@ -29,6 +29,7 @@
 #include <asm/irq.h>
 #include <plat/devs.h>
 #include <plat/irqs.h>
+#include <plat/cpu.h>
 
 #include <mach/map.h>
 #include <mach/irqs.h>
@@ -36,7 +37,7 @@
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-u8 pdma0_peri[] = {
+static u8 exynos4210_pdma0_peri[] = {
        DMACH_PCM0_RX,
        DMACH_PCM0_TX,
        DMACH_PCM2_RX,
@@ -69,15 +70,47 @@ u8 pdma0_peri[] = {
        DMACH_AC97_PCMOUT,
 };
 
-struct dma_pl330_platdata exynos4_pdma0_pdata = {
-       .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
-       .peri_id = pdma0_peri,
+static u8 exynos4212_pdma0_peri[] = {
+       DMACH_PCM0_RX,
+       DMACH_PCM0_TX,
+       DMACH_PCM2_RX,
+       DMACH_PCM2_TX,
+       DMACH_MIPI_HSI0,
+       DMACH_MIPI_HSI1,
+       DMACH_SPI0_RX,
+       DMACH_SPI0_TX,
+       DMACH_SPI2_RX,
+       DMACH_SPI2_TX,
+       DMACH_I2S0S_TX,
+       DMACH_I2S0_RX,
+       DMACH_I2S0_TX,
+       DMACH_I2S2_RX,
+       DMACH_I2S2_TX,
+       DMACH_UART0_RX,
+       DMACH_UART0_TX,
+       DMACH_UART2_RX,
+       DMACH_UART2_TX,
+       DMACH_UART4_RX,
+       DMACH_UART4_TX,
+       DMACH_SLIMBUS0_RX,
+       DMACH_SLIMBUS0_TX,
+       DMACH_SLIMBUS2_RX,
+       DMACH_SLIMBUS2_TX,
+       DMACH_SLIMBUS4_RX,
+       DMACH_SLIMBUS4_TX,
+       DMACH_AC97_MICIN,
+       DMACH_AC97_PCMIN,
+       DMACH_AC97_PCMOUT,
+       DMACH_MIPI_HSI4,
+       DMACH_MIPI_HSI5,
 };
 
-AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, EXYNOS4_PA_PDMA0,
-       {IRQ_PDMA0}, &exynos4_pdma0_pdata);
+struct dma_pl330_platdata exynos4_pdma0_pdata;
+
+static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
+       EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
 
-u8 pdma1_peri[] = {
+static u8 exynos4210_pdma1_peri[] = {
        DMACH_PCM0_RX,
        DMACH_PCM0_TX,
        DMACH_PCM1_RX,
@@ -105,19 +138,84 @@ u8 pdma1_peri[] = {
        DMACH_SLIMBUS5_TX,
 };
 
-struct dma_pl330_platdata exynos4_pdma1_pdata = {
-       .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
-       .peri_id = pdma1_peri,
+static u8 exynos4212_pdma1_peri[] = {
+       DMACH_PCM0_RX,
+       DMACH_PCM0_TX,
+       DMACH_PCM1_RX,
+       DMACH_PCM1_TX,
+       DMACH_MIPI_HSI2,
+       DMACH_MIPI_HSI3,
+       DMACH_SPI1_RX,
+       DMACH_SPI1_TX,
+       DMACH_I2S0S_TX,
+       DMACH_I2S0_RX,
+       DMACH_I2S0_TX,
+       DMACH_I2S1_RX,
+       DMACH_I2S1_TX,
+       DMACH_UART0_RX,
+       DMACH_UART0_TX,
+       DMACH_UART1_RX,
+       DMACH_UART1_TX,
+       DMACH_UART3_RX,
+       DMACH_UART3_TX,
+       DMACH_SLIMBUS1_RX,
+       DMACH_SLIMBUS1_TX,
+       DMACH_SLIMBUS3_RX,
+       DMACH_SLIMBUS3_TX,
+       DMACH_SLIMBUS5_RX,
+       DMACH_SLIMBUS5_TX,
+       DMACH_SLIMBUS0AUX_RX,
+       DMACH_SLIMBUS0AUX_TX,
+       DMACH_SPDIF,
+       DMACH_MIPI_HSI6,
+       DMACH_MIPI_HSI7,
+};
+
+static struct dma_pl330_platdata exynos4_pdma1_pdata;
+
+static AMBA_AHB_DEVICE(exynos4_pdma1,  "dma-pl330.1", 0x00041330,
+       EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
+
+static u8 mdma_peri[] = {
+       DMACH_MTOM_0,
+       DMACH_MTOM_1,
+       DMACH_MTOM_2,
+       DMACH_MTOM_3,
+       DMACH_MTOM_4,
+       DMACH_MTOM_5,
+       DMACH_MTOM_6,
+       DMACH_MTOM_7,
 };
 
-AMBA_AHB_DEVICE(exynos4_pdma1,  "dma-pl330.1", 0x00041330, EXYNOS4_PA_PDMA1,
-       {IRQ_PDMA1}, &exynos4_pdma1_pdata);
+static struct dma_pl330_platdata exynos4_mdma1_pdata = {
+       .nr_valid_peri = ARRAY_SIZE(mdma_peri),
+       .peri_id = mdma_peri,
+};
+
+static AMBA_AHB_DEVICE(exynos4_mdma1,  "dma-pl330.2", 0x00041330,
+       EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
 
 static int __init exynos4_dma_init(void)
 {
        if (of_have_populated_dt())
                return 0;
 
+       if (soc_is_exynos4210()) {
+               exynos4_pdma0_pdata.nr_valid_peri =
+                       ARRAY_SIZE(exynos4210_pdma0_peri);
+               exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
+               exynos4_pdma1_pdata.nr_valid_peri =
+                       ARRAY_SIZE(exynos4210_pdma1_peri);
+               exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
+       } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+               exynos4_pdma0_pdata.nr_valid_peri =
+                       ARRAY_SIZE(exynos4212_pdma0_peri);
+               exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
+               exynos4_pdma1_pdata.nr_valid_peri =
+                       ARRAY_SIZE(exynos4212_pdma1_peri);
+               exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
+       }
+
        dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
        dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
        amba_device_register(&exynos4_pdma0_device, &iomem_resource);
@@ -126,6 +224,9 @@ static int __init exynos4_dma_init(void)
        dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
        amba_device_register(&exynos4_pdma1_device, &iomem_resource);
 
+       dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
+       amba_device_register(&exynos4_mdma1_device, &iomem_resource);
+
        return 0;
 }
 arch_initcall(exynos4_dma_init);
index 6cacf16..6c857ff 100644 (file)
         */
 
        .macro addruart, rp, rv, tmp
-               ldr     \rp, = S3C_PA_UART
-               ldr     \rv, = S3C_VA_UART
+               mov     \rp, #0x10000000
+               ldr     \rp, [\rp, #0x0]
+               and     \rp, \rp, #0xf00000
+               teq     \rp, #0x500000          @@ EXYNOS5
+               ldreq   \rp, =EXYNOS5_PA_UART
+               movne   \rp, #EXYNOS4_PA_UART   @@ EXYNOS4
+               ldr     \rv, =S3C_VA_UART
 #if CONFIG_DEBUG_S3C_UART != 0
                add     \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
                add     \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
diff --git a/arch/arm/mach-exynos/include/mach/exynos4-clock.h b/arch/arm/mach-exynos/include/mach/exynos4-clock.h
deleted file mode 100644 (file)
index a07fcbf..0000000
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Header file for exynos4 clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H __FILE__
-
-#include <linux/clk.h>
-
-extern struct clk clk_sclk_hdmi27m;
-extern struct clk clk_sclk_usbphy0;
-extern struct clk clk_sclk_usbphy1;
-extern struct clk clk_sclk_hdmiphy;
-
-extern struct clksrc_clk clk_sclk_apll;
-extern struct clksrc_clk clk_mout_mpll;
-extern struct clksrc_clk clk_aclk_133;
-extern struct clksrc_clk clk_mout_epll;
-extern struct clksrc_clk clk_sclk_vpll;
-
-extern struct clk *clkset_corebus_list[];
-extern struct clksrc_sources clkset_mout_corebus;
-
-extern struct clk *clkset_aclk_top_list[];
-extern struct clksrc_sources clkset_aclk;
-
-extern struct clk *clkset_group_list[];
-extern struct clksrc_sources clkset_group;
-
-extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
-
-#endif /* __ASM_ARCH_CLOCK_H */
index f77bce0..9bee853 100644 (file)
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *             http://www.samsung.com
  *
- * EXYNOS4 - IRQ definitions
+ * EXYNOS - IRQ definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
 
 /* PPI: Private Peripheral Interrupt */
 
-#define IRQ_PPI(x)             (x+16)
-
-#define IRQ_MCT_LOCALTIMER     IRQ_PPI(12)
+#define IRQ_PPI(x)                     (x + 16)
 
 /* SPI: Shared Peripheral Interrupt */
 
-#define IRQ_SPI(x)             (x+32)
-
-#define IRQ_EINT0              IRQ_SPI(16)
-#define IRQ_EINT1              IRQ_SPI(17)
-#define IRQ_EINT2              IRQ_SPI(18)
-#define IRQ_EINT3              IRQ_SPI(19)
-#define IRQ_EINT4              IRQ_SPI(20)
-#define IRQ_EINT5              IRQ_SPI(21)
-#define IRQ_EINT6              IRQ_SPI(22)
-#define IRQ_EINT7              IRQ_SPI(23)
-#define IRQ_EINT8              IRQ_SPI(24)
-#define IRQ_EINT9              IRQ_SPI(25)
-#define IRQ_EINT10             IRQ_SPI(26)
-#define IRQ_EINT11             IRQ_SPI(27)
-#define IRQ_EINT12             IRQ_SPI(28)
-#define IRQ_EINT13             IRQ_SPI(29)
-#define IRQ_EINT14             IRQ_SPI(30)
-#define IRQ_EINT15             IRQ_SPI(31)
-#define IRQ_EINT16_31          IRQ_SPI(32)
-
-#define IRQ_PDMA0              IRQ_SPI(35)
-#define IRQ_PDMA1              IRQ_SPI(36)
-#define IRQ_TIMER0_VIC         IRQ_SPI(37)
-#define IRQ_TIMER1_VIC         IRQ_SPI(38)
-#define IRQ_TIMER2_VIC         IRQ_SPI(39)
-#define IRQ_TIMER3_VIC         IRQ_SPI(40)
-#define IRQ_TIMER4_VIC         IRQ_SPI(41)
-#define IRQ_MCT_L0             IRQ_SPI(42)
-#define IRQ_WDT                        IRQ_SPI(43)
-#define IRQ_RTC_ALARM          IRQ_SPI(44)
-#define IRQ_RTC_TIC            IRQ_SPI(45)
-#define IRQ_GPIO_XB            IRQ_SPI(46)
-#define IRQ_GPIO_XA            IRQ_SPI(47)
-#define IRQ_MCT_L1             IRQ_SPI(48)
-
-#define IRQ_UART0              IRQ_SPI(52)
-#define IRQ_UART1              IRQ_SPI(53)
-#define IRQ_UART2              IRQ_SPI(54)
-#define IRQ_UART3              IRQ_SPI(55)
-#define IRQ_UART4              IRQ_SPI(56)
-#define IRQ_MCT_G0             IRQ_SPI(57)
-#define IRQ_IIC                        IRQ_SPI(58)
-#define IRQ_IIC1               IRQ_SPI(59)
-#define IRQ_IIC2               IRQ_SPI(60)
-#define IRQ_IIC3               IRQ_SPI(61)
-#define IRQ_IIC4               IRQ_SPI(62)
-#define IRQ_IIC5               IRQ_SPI(63)
-#define IRQ_IIC6               IRQ_SPI(64)
-#define IRQ_IIC7               IRQ_SPI(65)
-#define IRQ_SPI0               IRQ_SPI(66)
-#define IRQ_SPI1               IRQ_SPI(67)
-#define IRQ_SPI2               IRQ_SPI(68)
-
-#define IRQ_USB_HOST           IRQ_SPI(70)
-#define IRQ_USB_HSOTG          IRQ_SPI(71)
-#define IRQ_MODEM_IF           IRQ_SPI(72)
-#define IRQ_HSMMC0             IRQ_SPI(73)
-#define IRQ_HSMMC1             IRQ_SPI(74)
-#define IRQ_HSMMC2             IRQ_SPI(75)
-#define IRQ_HSMMC3             IRQ_SPI(76)
-#define IRQ_DWMCI              IRQ_SPI(77)
-
-#define IRQ_MIPI_CSIS0         IRQ_SPI(78)
-#define IRQ_MIPI_CSIS1         IRQ_SPI(80)
-
-#define IRQ_ONENAND_AUDI       IRQ_SPI(82)
-#define IRQ_ROTATOR            IRQ_SPI(83)
-#define IRQ_FIMC0              IRQ_SPI(84)
-#define IRQ_FIMC1              IRQ_SPI(85)
-#define IRQ_FIMC2              IRQ_SPI(86)
-#define IRQ_FIMC3              IRQ_SPI(87)
-#define IRQ_JPEG               IRQ_SPI(88)
-#define IRQ_2D                 IRQ_SPI(89)
-#define IRQ_PCIE               IRQ_SPI(90)
-
-#define IRQ_MIXER              IRQ_SPI(91)
-#define IRQ_HDMI               IRQ_SPI(92)
-#define IRQ_IIC_HDMIPHY                IRQ_SPI(93)
-#define IRQ_MFC                        IRQ_SPI(94)
-#define IRQ_SDO                        IRQ_SPI(95)
-
-#define IRQ_AUDIO_SS           IRQ_SPI(96)
-#define IRQ_I2S0               IRQ_SPI(97)
-#define IRQ_I2S1               IRQ_SPI(98)
-#define IRQ_I2S2               IRQ_SPI(99)
-#define IRQ_AC97               IRQ_SPI(100)
-
-#define IRQ_SPDIF              IRQ_SPI(104)
-#define IRQ_ADC0               IRQ_SPI(105)
-#define IRQ_PEN0               IRQ_SPI(106)
-#define IRQ_ADC1               IRQ_SPI(107)
-#define IRQ_PEN1               IRQ_SPI(108)
-#define IRQ_KEYPAD             IRQ_SPI(109)
-#define IRQ_PMU                        IRQ_SPI(110)
-#define IRQ_GPS                        IRQ_SPI(111)
-#define IRQ_INTFEEDCTRL_SSS    IRQ_SPI(112)
-#define IRQ_SLIMBUS            IRQ_SPI(113)
-
-#define IRQ_TSI                        IRQ_SPI(115)
-#define IRQ_SATA               IRQ_SPI(116)
-
-#define MAX_IRQ_IN_COMBINER    8
-#define COMBINER_GROUP(x)      ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
-#define COMBINER_IRQ(x, y)     (COMBINER_GROUP(x) + y)
-
-#define IRQ_SYSMMU_MDMA0_0     COMBINER_IRQ(4, 0)
-#define IRQ_SYSMMU_SSS_0       COMBINER_IRQ(4, 1)
-#define IRQ_SYSMMU_FIMC0_0     COMBINER_IRQ(4, 2)
-#define IRQ_SYSMMU_FIMC1_0     COMBINER_IRQ(4, 3)
-#define IRQ_SYSMMU_FIMC2_0     COMBINER_IRQ(4, 4)
-#define IRQ_SYSMMU_FIMC3_0     COMBINER_IRQ(4, 5)
-#define IRQ_SYSMMU_JPEG_0      COMBINER_IRQ(4, 6)
-#define IRQ_SYSMMU_2D_0                COMBINER_IRQ(4, 7)
-
-#define IRQ_SYSMMU_ROTATOR_0   COMBINER_IRQ(5, 0)
-#define IRQ_SYSMMU_MDMA1_0     COMBINER_IRQ(5, 1)
-#define IRQ_SYSMMU_LCD0_M0_0   COMBINER_IRQ(5, 2)
-#define IRQ_SYSMMU_LCD1_M1_0   COMBINER_IRQ(5, 3)
-#define IRQ_SYSMMU_TV_M0_0     COMBINER_IRQ(5, 4)
-#define IRQ_SYSMMU_MFC_M0_0    COMBINER_IRQ(5, 5)
-#define IRQ_SYSMMU_MFC_M1_0    COMBINER_IRQ(5, 6)
-#define IRQ_SYSMMU_PCIE_0      COMBINER_IRQ(5, 7)
-
-#define IRQ_FIMD0_FIFO         COMBINER_IRQ(11, 0)
-#define IRQ_FIMD0_VSYNC                COMBINER_IRQ(11, 1)
-#define IRQ_FIMD0_SYSTEM       COMBINER_IRQ(11, 2)
-
-#define MAX_COMBINER_NR                16
-
-#define IRQ_ADC                        IRQ_ADC0
-#define IRQ_TC                 IRQ_PEN0
-
-#define S5P_IRQ_EINT_BASE      COMBINER_IRQ(MAX_COMBINER_NR, 0)
-
-#define S5P_EINT_BASE1         (S5P_IRQ_EINT_BASE + 0)
-#define S5P_EINT_BASE2         (S5P_IRQ_EINT_BASE + 16)
-
-/* optional GPIO interrupts */
-#define S5P_GPIOINT_BASE       (S5P_IRQ_EINT_BASE + 32)
-#define IRQ_GPIO1_NR_GROUPS    16
-#define IRQ_GPIO2_NR_GROUPS    9
-#define IRQ_GPIO_END           (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
-
-#define IRQ_TIMER_BASE         (IRQ_GPIO_END + 64)
+#define IRQ_SPI(x)                     (x + 32)
+
+/* COMBINER */
+
+#define MAX_IRQ_IN_COMBINER            8
+#define COMBINER_GROUP(x)              ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
+#define COMBINER_IRQ(x, y)             (COMBINER_GROUP(x) + y)
+
+/* For EXYNOS4 and EXYNOS5 */
+
+#define EXYNOS_IRQ_MCT_LOCALTIMER      IRQ_PPI(12)
+
+#define EXYNOS_IRQ_EINT16_31           IRQ_SPI(32)
+
+/* For EXYNOS4 SoCs */
+
+#define EXYNOS4_IRQ_EINT0              IRQ_SPI(16)
+#define EXYNOS4_IRQ_EINT1              IRQ_SPI(17)
+#define EXYNOS4_IRQ_EINT2              IRQ_SPI(18)
+#define EXYNOS4_IRQ_EINT3              IRQ_SPI(19)
+#define EXYNOS4_IRQ_EINT4              IRQ_SPI(20)
+#define EXYNOS4_IRQ_EINT5              IRQ_SPI(21)
+#define EXYNOS4_IRQ_EINT6              IRQ_SPI(22)
+#define EXYNOS4_IRQ_EINT7              IRQ_SPI(23)
+#define EXYNOS4_IRQ_EINT8              IRQ_SPI(24)
+#define EXYNOS4_IRQ_EINT9              IRQ_SPI(25)
+#define EXYNOS4_IRQ_EINT10             IRQ_SPI(26)
+#define EXYNOS4_IRQ_EINT11             IRQ_SPI(27)
+#define EXYNOS4_IRQ_EINT12             IRQ_SPI(28)
+#define EXYNOS4_IRQ_EINT13             IRQ_SPI(29)
+#define EXYNOS4_IRQ_EINT14             IRQ_SPI(30)
+#define EXYNOS4_IRQ_EINT15             IRQ_SPI(31)
+
+#define EXYNOS4_IRQ_MDMA0              IRQ_SPI(33)
+#define EXYNOS4_IRQ_MDMA1              IRQ_SPI(34)
+#define EXYNOS4_IRQ_PDMA0              IRQ_SPI(35)
+#define EXYNOS4_IRQ_PDMA1              IRQ_SPI(36)
+#define EXYNOS4_IRQ_TIMER0_VIC         IRQ_SPI(37)
+#define EXYNOS4_IRQ_TIMER1_VIC         IRQ_SPI(38)
+#define EXYNOS4_IRQ_TIMER2_VIC         IRQ_SPI(39)
+#define EXYNOS4_IRQ_TIMER3_VIC         IRQ_SPI(40)
+#define EXYNOS4_IRQ_TIMER4_VIC         IRQ_SPI(41)
+#define EXYNOS4_IRQ_MCT_L0             IRQ_SPI(42)
+#define EXYNOS4_IRQ_WDT                        IRQ_SPI(43)
+#define EXYNOS4_IRQ_RTC_ALARM          IRQ_SPI(44)
+#define EXYNOS4_IRQ_RTC_TIC            IRQ_SPI(45)
+#define EXYNOS4_IRQ_GPIO_XB            IRQ_SPI(46)
+#define EXYNOS4_IRQ_GPIO_XA            IRQ_SPI(47)
+#define EXYNOS4_IRQ_MCT_L1             IRQ_SPI(48)
+
+#define EXYNOS4_IRQ_UART0              IRQ_SPI(52)
+#define EXYNOS4_IRQ_UART1              IRQ_SPI(53)
+#define EXYNOS4_IRQ_UART2              IRQ_SPI(54)
+#define EXYNOS4_IRQ_UART3              IRQ_SPI(55)
+#define EXYNOS4_IRQ_UART4              IRQ_SPI(56)
+#define EXYNOS4_IRQ_MCT_G0             IRQ_SPI(57)
+#define EXYNOS4_IRQ_IIC                        IRQ_SPI(58)
+#define EXYNOS4_IRQ_IIC1               IRQ_SPI(59)
+#define EXYNOS4_IRQ_IIC2               IRQ_SPI(60)
+#define EXYNOS4_IRQ_IIC3               IRQ_SPI(61)
+#define EXYNOS4_IRQ_IIC4               IRQ_SPI(62)
+#define EXYNOS4_IRQ_IIC5               IRQ_SPI(63)
+#define EXYNOS4_IRQ_IIC6               IRQ_SPI(64)
+#define EXYNOS4_IRQ_IIC7               IRQ_SPI(65)
+#define EXYNOS4_IRQ_SPI0               IRQ_SPI(66)
+#define EXYNOS4_IRQ_SPI1               IRQ_SPI(67)
+#define EXYNOS4_IRQ_SPI2               IRQ_SPI(68)
+
+#define EXYNOS4_IRQ_USB_HOST           IRQ_SPI(70)
+#define EXYNOS4_IRQ_USB_HSOTG          IRQ_SPI(71)
+#define EXYNOS4_IRQ_MODEM_IF           IRQ_SPI(72)
+#define EXYNOS4_IRQ_HSMMC0             IRQ_SPI(73)
+#define EXYNOS4_IRQ_HSMMC1             IRQ_SPI(74)
+#define EXYNOS4_IRQ_HSMMC2             IRQ_SPI(75)
+#define EXYNOS4_IRQ_HSMMC3             IRQ_SPI(76)
+#define EXYNOS4_IRQ_DWMCI              IRQ_SPI(77)
+
+#define EXYNOS4_IRQ_MIPI_CSIS0         IRQ_SPI(78)
+#define EXYNOS4_IRQ_MIPI_CSIS1         IRQ_SPI(80)
+
+#define EXYNOS4_IRQ_ONENAND_AUDI       IRQ_SPI(82)
+#define EXYNOS4_IRQ_ROTATOR            IRQ_SPI(83)
+#define EXYNOS4_IRQ_FIMC0              IRQ_SPI(84)
+#define EXYNOS4_IRQ_FIMC1              IRQ_SPI(85)
+#define EXYNOS4_IRQ_FIMC2              IRQ_SPI(86)
+#define EXYNOS4_IRQ_FIMC3              IRQ_SPI(87)
+#define EXYNOS4_IRQ_JPEG               IRQ_SPI(88)
+#define EXYNOS4_IRQ_2D                 IRQ_SPI(89)
+#define EXYNOS4_IRQ_PCIE               IRQ_SPI(90)
+
+#define EXYNOS4_IRQ_MIXER              IRQ_SPI(91)
+#define EXYNOS4_IRQ_HDMI               IRQ_SPI(92)
+#define EXYNOS4_IRQ_IIC_HDMIPHY                IRQ_SPI(93)
+#define EXYNOS4_IRQ_MFC                        IRQ_SPI(94)
+#define EXYNOS4_IRQ_SDO                        IRQ_SPI(95)
+
+#define EXYNOS4_IRQ_AUDIO_SS           IRQ_SPI(96)
+#define EXYNOS4_IRQ_I2S0               IRQ_SPI(97)
+#define EXYNOS4_IRQ_I2S1               IRQ_SPI(98)
+#define EXYNOS4_IRQ_I2S2               IRQ_SPI(99)
+#define EXYNOS4_IRQ_AC97               IRQ_SPI(100)
+
+#define EXYNOS4_IRQ_SPDIF              IRQ_SPI(104)
+#define EXYNOS4_IRQ_ADC0               IRQ_SPI(105)
+#define EXYNOS4_IRQ_PEN0               IRQ_SPI(106)
+#define EXYNOS4_IRQ_ADC1               IRQ_SPI(107)
+#define EXYNOS4_IRQ_PEN1               IRQ_SPI(108)
+#define EXYNOS4_IRQ_KEYPAD             IRQ_SPI(109)
+#define EXYNOS4_IRQ_PMU                        IRQ_SPI(110)
+#define EXYNOS4_IRQ_GPS                        IRQ_SPI(111)
+#define EXYNOS4_IRQ_INTFEEDCTRL_SSS    IRQ_SPI(112)
+#define EXYNOS4_IRQ_SLIMBUS            IRQ_SPI(113)
+
+#define EXYNOS4_IRQ_TSI                        IRQ_SPI(115)
+#define EXYNOS4_IRQ_SATA               IRQ_SPI(116)
+
+#define EXYNOS4_IRQ_SYSMMU_MDMA0_0     COMBINER_IRQ(4, 0)
+#define EXYNOS4_IRQ_SYSMMU_SSS_0       COMBINER_IRQ(4, 1)
+#define EXYNOS4_IRQ_SYSMMU_FIMC0_0     COMBINER_IRQ(4, 2)
+#define EXYNOS4_IRQ_SYSMMU_FIMC1_0     COMBINER_IRQ(4, 3)
+#define EXYNOS4_IRQ_SYSMMU_FIMC2_0     COMBINER_IRQ(4, 4)
+#define EXYNOS4_IRQ_SYSMMU_FIMC3_0     COMBINER_IRQ(4, 5)
+#define EXYNOS4_IRQ_SYSMMU_JPEG_0      COMBINER_IRQ(4, 6)
+#define EXYNOS4_IRQ_SYSMMU_2D_0                COMBINER_IRQ(4, 7)
+
+#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0   COMBINER_IRQ(5, 0)
+#define EXYNOS4_IRQ_SYSMMU_MDMA1_0     COMBINER_IRQ(5, 1)
+#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0   COMBINER_IRQ(5, 2)
+#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0   COMBINER_IRQ(5, 3)
+#define EXYNOS4_IRQ_SYSMMU_TV_M0_0     COMBINER_IRQ(5, 4)
+#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0    COMBINER_IRQ(5, 5)
+#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0    COMBINER_IRQ(5, 6)
+#define EXYNOS4_IRQ_SYSMMU_PCIE_0      COMBINER_IRQ(5, 7)
+
+#define EXYNOS4_IRQ_FIMD0_FIFO         COMBINER_IRQ(11, 0)
+#define EXYNOS4_IRQ_FIMD0_VSYNC                COMBINER_IRQ(11, 1)
+#define EXYNOS4_IRQ_FIMD0_SYSTEM       COMBINER_IRQ(11, 2)
+
+#define EXYNOS4_MAX_COMBINER_NR                16
+
+#define EXYNOS4_IRQ_GPIO1_NR_GROUPS    16
+#define EXYNOS4_IRQ_GPIO2_NR_GROUPS    9
+
+/*
+ * For Compatibility:
+ * the default is for EXYNOS4, and
+ * for exynos5, should be re-mapped at function
+ */
+
+#define IRQ_TIMER0_VIC                 EXYNOS4_IRQ_TIMER0_VIC
+#define IRQ_TIMER1_VIC                 EXYNOS4_IRQ_TIMER1_VIC
+#define IRQ_TIMER2_VIC                 EXYNOS4_IRQ_TIMER2_VIC
+#define IRQ_TIMER3_VIC                 EXYNOS4_IRQ_TIMER3_VIC
+#define IRQ_TIMER4_VIC                 EXYNOS4_IRQ_TIMER4_VIC
+
+#define IRQ_WDT                                EXYNOS4_IRQ_WDT
+#define IRQ_RTC_ALARM                  EXYNOS4_IRQ_RTC_ALARM
+#define IRQ_RTC_TIC                    EXYNOS4_IRQ_RTC_TIC
+#define IRQ_GPIO_XB                    EXYNOS4_IRQ_GPIO_XB
+#define IRQ_GPIO_XA                    EXYNOS4_IRQ_GPIO_XA
+
+#define IRQ_IIC                                EXYNOS4_IRQ_IIC
+#define IRQ_IIC1                       EXYNOS4_IRQ_IIC1
+#define IRQ_IIC3                       EXYNOS4_IRQ_IIC3
+#define IRQ_IIC5                       EXYNOS4_IRQ_IIC5
+#define IRQ_IIC6                       EXYNOS4_IRQ_IIC6
+#define IRQ_IIC7                       EXYNOS4_IRQ_IIC7
+
+#define IRQ_USB_HOST                   EXYNOS4_IRQ_USB_HOST
+
+#define IRQ_HSMMC0                     EXYNOS4_IRQ_HSMMC0
+#define IRQ_HSMMC1                     EXYNOS4_IRQ_HSMMC1
+#define IRQ_HSMMC2                     EXYNOS4_IRQ_HSMMC2
+#define IRQ_HSMMC3                     EXYNOS4_IRQ_HSMMC3
+
+#define IRQ_MIPI_CSIS0                 EXYNOS4_IRQ_MIPI_CSIS0
+
+#define IRQ_ONENAND_AUDI               EXYNOS4_IRQ_ONENAND_AUDI
+
+#define IRQ_FIMC0                      EXYNOS4_IRQ_FIMC0
+#define IRQ_FIMC1                      EXYNOS4_IRQ_FIMC1
+#define IRQ_FIMC2                      EXYNOS4_IRQ_FIMC2
+#define IRQ_FIMC3                      EXYNOS4_IRQ_FIMC3
+#define IRQ_JPEG                       EXYNOS4_IRQ_JPEG
+#define IRQ_2D                         EXYNOS4_IRQ_2D
+
+#define IRQ_MIXER                      EXYNOS4_IRQ_MIXER
+#define IRQ_HDMI                       EXYNOS4_IRQ_HDMI
+#define IRQ_IIC_HDMIPHY                        EXYNOS4_IRQ_IIC_HDMIPHY
+#define IRQ_MFC                                EXYNOS4_IRQ_MFC
+#define IRQ_SDO                                EXYNOS4_IRQ_SDO
+
+#define IRQ_ADC                                EXYNOS4_IRQ_ADC0
+#define IRQ_TC                         EXYNOS4_IRQ_PEN0
+
+#define IRQ_KEYPAD                     EXYNOS4_IRQ_KEYPAD
+#define IRQ_PMU                                EXYNOS4_IRQ_PMU
+
+#define IRQ_SYSMMU_MDMA0_0             EXYNOS4_IRQ_SYSMMU_MDMA0_0
+#define IRQ_SYSMMU_SSS_0                EXYNOS4_IRQ_SYSMMU_SSS_0
+#define IRQ_SYSMMU_FIMC0_0              EXYNOS4_IRQ_SYSMMU_FIMC0_0
+#define IRQ_SYSMMU_FIMC1_0              EXYNOS4_IRQ_SYSMMU_FIMC1_0
+#define IRQ_SYSMMU_FIMC2_0              EXYNOS4_IRQ_SYSMMU_FIMC2_0
+#define IRQ_SYSMMU_FIMC3_0              EXYNOS4_IRQ_SYSMMU_FIMC3_0
+#define IRQ_SYSMMU_JPEG_0               EXYNOS4_IRQ_SYSMMU_JPEG_0
+#define IRQ_SYSMMU_2D_0                 EXYNOS4_IRQ_SYSMMU_2D_0
+
+#define IRQ_SYSMMU_ROTATOR_0            EXYNOS4_IRQ_SYSMMU_ROTATOR_0
+#define IRQ_SYSMMU_MDMA1_0              EXYNOS4_IRQ_SYSMMU_MDMA1_0
+#define IRQ_SYSMMU_LCD0_M0_0            EXYNOS4_IRQ_SYSMMU_LCD0_M0_0
+#define IRQ_SYSMMU_LCD1_M1_0            EXYNOS4_IRQ_SYSMMU_LCD1_M1_0
+#define IRQ_SYSMMU_TV_M0_0              EXYNOS4_IRQ_SYSMMU_TV_M0_0
+#define IRQ_SYSMMU_MFC_M0_0             EXYNOS4_IRQ_SYSMMU_MFC_M0_0
+#define IRQ_SYSMMU_MFC_M1_0             EXYNOS4_IRQ_SYSMMU_MFC_M1_0
+#define IRQ_SYSMMU_PCIE_0               EXYNOS4_IRQ_SYSMMU_PCIE_0
+
+#define IRQ_FIMD0_FIFO                 EXYNOS4_IRQ_FIMD0_FIFO
+#define IRQ_FIMD0_VSYNC                        EXYNOS4_IRQ_FIMD0_VSYNC
+#define IRQ_FIMD0_SYSTEM               EXYNOS4_IRQ_FIMD0_SYSTEM
+
+#define IRQ_GPIO1_NR_GROUPS            EXYNOS4_IRQ_GPIO1_NR_GROUPS
+#define IRQ_GPIO2_NR_GROUPS            EXYNOS4_IRQ_GPIO2_NR_GROUPS
+
+/* For EXYNOS5 SoCs */
+
+#define EXYNOS5_IRQ_MDMA0              IRQ_SPI(33)
+#define EXYNOS5_IRQ_PDMA0              IRQ_SPI(34)
+#define EXYNOS5_IRQ_PDMA1              IRQ_SPI(35)
+#define EXYNOS5_IRQ_TIMER0_VIC         IRQ_SPI(36)
+#define EXYNOS5_IRQ_TIMER1_VIC&nbs