msm: 8x60: setup correct handlers for private interrupts
Abhijeet Dharmapurikar [Mon, 1 Feb 2010 20:30:28 +0000 (12:30 -0800)]
Private Peripheral interrupts could be edge triggered or level triggered
depending on the platform. Initialize handlers for these in board file.

Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>

arch/arm/mach-msm/board-msm8x60.c

index e7feb99..70087ca 100644 (file)
@@ -44,7 +44,7 @@ static void __init msm8x60_init_irq(void)
 {
        unsigned int i;
 
-       gic_dist_init(0, MSM_QGIC_DIST_BASE, 1);
+       gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
        gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
        gic_cpu_init(0, MSM_QGIC_CPU_BASE);