ARM: tegra: pm: Fix DPD code offset for T11x
Pavan Kunapuli [Mon, 15 Oct 2012 11:39:35 +0000 (16:39 +0530)]
The DPD code offset for enabling/disabling DPD
modes is different for T30 and T11x. Fixed the
same.

Bug 1051532

Reviewed-on: http://git-master/r/144536
(cherry picked from commit 83ca9c5ee3515f825150211b21411e9cd7eb38a9)

Change-Id: Icdf2ba622a8baa2facb0ba91e0ce068c1104401d
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/146409
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/pm-t3.c

index 594141d..422c5a5 100644 (file)
@@ -527,7 +527,11 @@ void tegra_lp0_cpu_mode(bool enter)
 #define APBDEV_PMC_IO_DPD_STATUS_0     0x1bc
 #define APBDEV_PMC_SEL_DPD_TIM_0       0x1c8
 #define APBDEV_DPD_ENABLE_LSB          30
+#if defined(CONFIG_ARCH_TEGRA_3x_SOC)
 #define APBDEV_DPD2_ENABLE_LSB         5
+#else
+#define APBDEV_DPD2_ENABLE_LSB         30
+#endif
 #define PMC_DPD_SAMPLE                 0x20
 
 static struct tegra_io_dpd tegra_list_io_dpd[] = {