[ARM]: tegra : cardhu Updated clk rate for UART
Pradeep Goudagunta [Mon, 31 Jan 2011 06:32:59 +0000 (11:32 +0530)]
Put clk on PLL_P and Increased clk rate from 13MHz to 216Mhz of UARTB,
UARTC, UARTD and UARTE. To enable them to work on high baudrates.

Original-Change-Id: I28f61a5dc1c9627717b09546c5025058f8f8ee17
Reviewed-on: http://git-master/r/17476
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Original-Change-Id: I64ffd58ada587751f77ab5c9858ba33f79bfd978

Rebase-Id: R27fb6c60f478f4c89341d1cd25b45156c0b5b20a

arch/arm/mach-tegra/board-cardhu.c

index e8fb10f..8532533 100644 (file)
@@ -146,10 +146,10 @@ static inline void cardhu_bt_rfkill(void) { }
 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
        /* name         parent          rate            enabled */
        { "uarta",      "pll_p",        216000000,      true},
-       { "uartb",      "clk_m",        13000000,       true},
-       { "uartc",      "clk_m",        13000000,       true},
-       { "uartd",      "clk_m",        13000000,       true},
-       { "uarte",      "clk_m",        13000000,       true},
+       { "uartb",      "pll_p",        216000000,      false},
+       { "uartc",      "pll_p",        216000000,      false},
+       { "uartd",      "pll_p",        216000000,      false},
+       { "uarte",      "pll_p",        216000000,      false},
        { "pll_m",      NULL,           0,              true},
        { "pll_p_out4", "pll_p",        24000000,       true },
        { "pwm",        "clk_32k",      32768,          false},