ARM: tegra:tegranote7 Added tegranote7 board files
David Pu [Mon, 25 Nov 2013 05:45:21 +0000 (13:45 +0800)]
Bug 1410152

Change-Id: I6d7ff6328867758251360251aa0b46b23eccd6f3
Reviewed-on: http://git-master/r/333936
(cherry picked from commit c1b6511e2d3bca8799c15307f62e53c9b42fe387)

Signed-off-by: David Pu <dpu@nvidia.com>
Change-Id: I817734cfb612ae9e4a66484458ee2198d75366e0
Reviewed-on: http://git-master/r/337148
Reviewed-by: Harry Hong <hhong@nvidia.com>
Tested-by: Harry Hong <hhong@nvidia.com>

15 files changed:
arch/arm/mach-tegra/Kconfig
arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/Makefile.boot
arch/arm/mach-tegra/board-tegranote7c-kbc.c [new file with mode: 0644]
arch/arm/mach-tegra/board-tegranote7c-memory.c [new file with mode: 0644]
arch/arm/mach-tegra/board-tegranote7c-panel.c [new file with mode: 0644]
arch/arm/mach-tegra/board-tegranote7c-pinmux-t11x.h [new file with mode: 0644]
arch/arm/mach-tegra/board-tegranote7c-pinmux.c [new file with mode: 0644]
arch/arm/mach-tegra/board-tegranote7c-power.c [new file with mode: 0644]
arch/arm/mach-tegra/board-tegranote7c-powermon.c [new file with mode: 0644]
arch/arm/mach-tegra/board-tegranote7c-sdhci.c [new file with mode: 0644]
arch/arm/mach-tegra/board-tegranote7c-sensors.c [new file with mode: 0644]
arch/arm/mach-tegra/board-tegranote7c.c [new file with mode: 0644]
arch/arm/mach-tegra/board-tegranote7c.h [new file with mode: 0644]
arch/arm/tools/mach-types

index a26b790..a149a2f 100644 (file)
@@ -350,6 +350,15 @@ config MACH_TEGRATAB
        help
          Support for NVIDIA TEGRATAB development platform
 
+config MACH_TEGRANOTE7C
+       bool "TEGRANOTE7C board"
+       depends on ARCH_TEGRA_11x_SOC
+       select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
+       select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC
+       select EDP_FRAMEWORK
+       help
+         Support for NVIDIA TEGRANOTE7C development platform
+
 choice
        prompt "Tegra platform type"
        default TEGRA_SILICON_PLATFORM
index fd62096..27d39b0 100644 (file)
@@ -316,6 +316,17 @@ obj-${CONFIG_MACH_TEGRATAB}            += board-tegratab-kbc.o
 obj-${CONFIG_MACH_TEGRATAB}            += board-tegratab-sensors.o
 obj-${CONFIG_MACH_TEGRATAB}            += panel-lgd-wxga-7-0.o
 
+obj-${CONFIG_MACH_TEGRANOTE7C}            += board-tegranote7c.o
+obj-${CONFIG_MACH_TEGRANOTE7C}            += board-tegranote7c-memory.o
+obj-${CONFIG_MACH_TEGRANOTE7C}            += board-tegranote7c-pinmux.o
+obj-${CONFIG_MACH_TEGRANOTE7C}            += board-tegranote7c-power.o
+obj-${CONFIG_MACH_TEGRANOTE7C}            += board-tegranote7c-powermon.o
+obj-${CONFIG_MACH_TEGRANOTE7C}            += board-tegranote7c-sdhci.o
+obj-${CONFIG_MACH_TEGRANOTE7C}            += board-tegranote7c-panel.o
+obj-${CONFIG_MACH_TEGRANOTE7C}            += board-tegranote7c-kbc.o
+obj-${CONFIG_MACH_TEGRANOTE7C}            += board-tegranote7c-sensors.o
+obj-${CONFIG_MACH_TEGRANOTE7C}            += panel-lgd-wxga-7-0.o
+
 obj-${CONFIG_MACH_TEGRA_PLUTO}          += board-pluto.o
 obj-${CONFIG_MACH_TEGRA_PLUTO}          += board-pluto-memory.o
 obj-${CONFIG_MACH_TEGRA_PLUTO}          += board-pluto-pinmux.o
index 14639f5..ad05015 100644 (file)
@@ -21,4 +21,5 @@ dtb-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra114-dalmore.dtb
 dtb-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra114-macallan.dtb
 dtb-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra114-roth.dtb
 dtb-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra114-pluto.dtb
-dtb-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra114-tegratab.dtb
\ No newline at end of file
+dtb-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra114-tegratab.dtb
+dtb-$(CONFIG_ARCH_TEGRA_11x_SOC) += tegra114-tegranote7c.dtb
diff --git a/arch/arm/mach-tegra/board-tegranote7c-kbc.c b/arch/arm/mach-tegra/board-tegranote7c-kbc.c
new file mode 100644 (file)
index 0000000..ef0294a
--- /dev/null
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <mach/io.h>
+#include <linux/io.h>
+#include <mach/iomap.h>
+#include <mach/kbc.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/mfd/palmas.h>
+#include "wakeups-t11x.h"
+
+#include "tegra-board-id.h"
+#include "board.h"
+#include "board-tegranote7c.h"
+#include "devices.h"
+
+#define GPIO_KEY(_id, _gpio, _iswake)           \
+       {                                       \
+               .code = _id,                    \
+               .gpio = TEGRA_GPIO_##_gpio,     \
+               .active_low = 1,                \
+               .desc = #_id,                   \
+               .type = EV_KEY,                 \
+               .wakeup = _iswake,              \
+               .debounce_interval = 30,        \
+       }
+
+#define GPIO_SW(_id, _gpio, _active_low, _iswake)   \
+       {                                           \
+               .code = _id,                        \
+               .gpio = TEGRA_GPIO_##_gpio,         \
+               .irq = -1,                          \
+               .type = EV_SW,                      \
+               .desc = #_id,                       \
+               .active_low = _active_low,          \
+               .wakeup = _iswake,                  \
+               .debounce_interval = 0,             \
+       }
+
+static struct gpio_keys_button tegranote7c_e1569_keys[] = {
+       [0] = GPIO_KEY(KEY_POWER, PQ0, 1),
+       [1] = GPIO_KEY(KEY_VOLUMEUP, PR2, 0),
+       [2] = GPIO_KEY(KEY_VOLUMEDOWN, PR1, 0),
+};
+
+static struct gpio_keys_button tegranote7c_p1640_keys[] = {
+       [0] = GPIO_KEY(KEY_POWER, PQ0, 1),
+       [1] = GPIO_KEY(KEY_VOLUMEUP, PR2, 0),
+       [2] = GPIO_KEY(KEY_VOLUMEDOWN, PQ2, 0),
+       [3] = GPIO_SW(SW_LID, PC7, 1, 1),
+       [4] = GPIO_SW(SW_TABLET_MODE, PQ1, 0, 0),
+};
+
+static struct gpio_keys_button tegranote7c_p1640_a01_keys[] = {
+       [0] = GPIO_KEY(KEY_POWER, PQ0, 1),
+       [1] = GPIO_KEY(KEY_VOLUMEUP, PR2, 0),
+       [2] = GPIO_KEY(KEY_VOLUMEDOWN, PQ2, 0),
+       [3] = GPIO_SW(SW_LID, PC7, 1, 1),
+       [4] = GPIO_SW(SW_TABLET_MODE, PO5, 0, 1),
+};
+
+static int tegranote7c_wakeup_key(void)
+{
+       int wakeup_key;
+       u64 status = readl(IO_ADDRESS(TEGRA_PMC_BASE) + PMC_WAKE_STATUS)
+               | (u64)readl(IO_ADDRESS(TEGRA_PMC_BASE)
+               + PMC_WAKE2_STATUS) << 32;
+       if (status & ((u64)1 << TEGRA_WAKE_GPIO_PQ0))
+               wakeup_key = KEY_POWER;
+       else if (status & ((u64)1 << TEGRA_WAKE_GPIO_PC7))
+               wakeup_key = SW_LID;
+       else if (status & ((u64)1 << TEGRA_WAKE_GPIO_PO5))
+               wakeup_key = SW_TABLET_MODE;
+       else
+               wakeup_key = KEY_UNKNOWN;
+
+       return wakeup_key;
+}
+
+static struct gpio_keys_platform_data tegranote7c_keys_pdata = {
+       .buttons        = tegranote7c_e1569_keys,
+       .nbuttons       = ARRAY_SIZE(tegranote7c_e1569_keys),
+       .wakeup_key     = tegranote7c_wakeup_key,
+};
+
+static struct platform_device tegranote7c_keys_device = {
+       .name   = "gpio-keys",
+       .id     = 0,
+       .dev    = {
+               .platform_data  = &tegranote7c_keys_pdata,
+       },
+};
+
+int __init tegranote7c_kbc_init(void)
+{
+       struct board_info board_info;
+
+       tegra_get_board_info(&board_info);
+
+       if (board_info.board_id == BOARD_P1640) {
+               if (board_info.fab == BOARD_FAB_A00) {
+                       tegranote7c_keys_pdata.buttons = tegranote7c_p1640_keys;
+                       tegranote7c_keys_pdata.nbuttons =
+                          ARRAY_SIZE(tegranote7c_p1640_keys);
+               } else {
+                       tegranote7c_keys_pdata.buttons = tegranote7c_p1640_a01_keys;
+                       tegranote7c_keys_pdata.nbuttons =
+                          ARRAY_SIZE(tegranote7c_p1640_a01_keys);
+               }
+       }
+
+       platform_device_register(&tegranote7c_keys_device);
+
+       return 0;
+}
+
diff --git a/arch/arm/mach-tegra/board-tegranote7c-memory.c b/arch/arm/mach-tegra/board-tegranote7c-memory.c
new file mode 100644 (file)
index 0000000..94f91d8
--- /dev/null
@@ -0,0 +1,4193 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_data/tegra_emc.h>
+
+#include "board.h"
+#include "board-tegranote7c.h"
+
+#include "tegra-board-id.h"
+#include "tegra11_emc.h"
+#include "fuse.h"
+#include "devices.h"
+
+static struct tegra11_emc_table e1569_mt41k128m16_125_table[] = {
+       {
+               0x41,       /* Rev 4.0.3 */
+               12750,      /* SDRAM frequency */
+               900,        /* min voltage */
+               "pll_p",    /* clock source id */
+               0x4000003e, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000000, /* EMC_RC */
+                       0x00000003, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000000, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x00000060, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000005, /* EMC_TXSR */
+                       0x00000005, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000001, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000064, /* EMC_TREFBW */
+                       0x00000005, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x800001c6, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x40040001, /* MC_EMEM_ARB_CFG */
+                       0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x77e30303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000007, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               57820,      /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               20400,      /* SDRAM frequency */
+               900,        /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000026, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000000, /* EMC_RC */
+                       0x00000003, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000000, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x0000009a, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000005, /* EMC_TXSR */
+                       0x00000006, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000001, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x000000a0, /* EMC_TREFBW */
+                       0x00000005, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x40020001, /* MC_EMEM_ARB_CFG */
+                       0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x75430303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x0000000a, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               35610,      /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               40800,      /* SDRAM frequency */
+               900,        /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000012, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000001, /* EMC_RC */
+                       0x00000006, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000001, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x00000134, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000007, /* EMC_TXSR */
+                       0x0000000c, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000002, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x0000013f, /* EMC_TREFBW */
+                       0x00000005, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000370, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0xa0000001, /* MC_EMEM_ARB_CFG */
+                       0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x73630303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000015, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               20850,      /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               68000,      /* SDRAM frequency */
+               900,        /* min voltage */
+               "pll_p",    /* clock source id */
+               0x4000000a, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000003, /* EMC_RC */
+                       0x0000000a, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000002, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x00000202, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000008, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x0000000c, /* EMC_TXSR */
+                       0x00000013, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000003, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000213, /* EMC_TREFBW */
+                       0x00000005, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x00000001, /* MC_EMEM_ARB_CFG */
+                       0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x72c30403, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000023, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               10720,      /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               102000,     /* SDRAM frequency */
+               900,        /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000006, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000004, /* EMC_RC */
+                       0x00000010, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000003, /* EMC_RAS */
+                       0x00000001, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000001, /* EMC_RD_RCD */
+                       0x00000001, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x00000303, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x0000000d, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000012, /* EMC_TXSR */
+                       0x0000001c, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000005, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x0000031c, /* EMC_TREFBW */
+                       0x00000005, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000714, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x08000001, /* MC_EMEM_ARB_CFG */
+                       0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
+                       0x72830504, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000034, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               6890,       /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               204000,     /* SDRAM frequency */
+               900,        /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000002, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000009, /* EMC_RC */
+                       0x00000020, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000007, /* EMC_RAS */
+                       0x00000002, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000002, /* EMC_RD_RCD */
+                       0x00000002, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x00000607, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x0000001d, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000023, /* EMC_TXSR */
+                       0x00000038, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000009, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000638, /* EMC_TREFBW */
+                       0x00000006, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x000000a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x05057404, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x01000003, /* MC_EMEM_ARB_CFG */
+                       0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0405, /* MC_EMEM_ARB_DA_COVERS */
+                       0x72440a06, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000068, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               3420,       /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               312000,     /* SDRAM frequency */
+               1000,       /* min voltage */
+               "pll_c",    /* clock source id */
+               0x24000002, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x0000000e, /* EMC_RC */
+                       0x00000030, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000009, /* EMC_RAS */
+                       0x00000003, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x00000008, /* EMC_W2R */
+                       0x00000002, /* EMC_R2P */
+                       0x00000009, /* EMC_W2P */
+                       0x00000003, /* EMC_RD_RCD */
+                       0x00000003, /* EMC_WR_RCD */
+                       0x00000002, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000004, /* EMC_WDV */
+                       0x00000004, /* EMC_WDV_MASK */
+                       0x00000007, /* EMC_IBDLY */
+                       0x00080006, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x00000945, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000001, /* EMC_PDEX2WR */
+                       0x00000008, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x0000002e, /* EMC_AR2PDEN */
+                       0x0000000e, /* EMC_RW2PDEN */
+                       0x00000036, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x0000000d, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000986, /* EMC_TREFBW */
+                       0x00000006, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000ba88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00030000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0001013d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x0190000c, /* EMC_MRS_WAIT_CNT */
+                       0x0190000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80001395, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x0b000004, /* MC_EMEM_ARB_CFG */
+                       0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06040202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000b0607, /* MC_EMEM_ARB_DA_COVERS */
+                       0x76e50f08, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00030000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000b, /* EMC_QSAFE */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00024000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00024000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00024000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00030000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000b, /* EMC_QSAFE */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00024000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00024000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00024000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x000000a0, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x5320000e, /* EMC_CFG */
+               0x80000321, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200000, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               2680,       /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               408000,     /* SDRAM frequency */
+               1000,       /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000000, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000012, /* EMC_RC */
+                       0x00000040, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x0000000d, /* EMC_RAS */
+                       0x00000004, /* EMC_RP */
+                       0x00000005, /* EMC_R2W */
+                       0x00000009, /* EMC_W2R */
+                       0x00000002, /* EMC_R2P */
+                       0x0000000c, /* EMC_W2P */
+                       0x00000004, /* EMC_RD_RCD */
+                       0x00000004, /* EMC_WR_RCD */
+                       0x00000002, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000004, /* EMC_WDV */
+                       0x00000004, /* EMC_WDV_MASK */
+                       0x00000007, /* EMC_IBDLY */
+                       0x00080006, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000e, /* EMC_RDV_MASK */
+                       0x00000c2f, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000001, /* EMC_PDEX2WR */
+                       0x00000008, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x0000003d, /* EMC_AR2PDEN */
+                       0x00000011, /* EMC_RW2PDEN */
+                       0x00000046, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000011, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000c70, /* EMC_TREFBW */
+                       0x00000006, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000ba88, /* EMC_FBIO_CFG5 */
+                       0x002c0080, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00018000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00018000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00018000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00018000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0001013d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x0181000c, /* EMC_MRS_WAIT_CNT */
+                       0x0181000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80001944, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x02000006, /* MC_EMEM_ARB_CFG */
+                       0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+                       0x0000000a, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06040202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000e070a, /* MC_EMEM_ARB_DA_COVERS */
+                       0x7547130b, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00018000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000e, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00020001, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000005, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000005, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000005, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00018000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00018000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00018000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00020001, /* EMC_DLL_XFORM_DQ1 */
+                       0x00020001, /* EMC_DLL_XFORM_DQ2 */
+                       0x00020001, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00018000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000e, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00020001, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000005, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000005, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000005, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00018000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00018000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00018000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00020001, /* EMC_DLL_XFORM_DQ1 */
+                       0x00020001, /* EMC_DLL_XFORM_DQ2 */
+                       0x00020001, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x000000d1, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x53200006, /* EMC_CFG */
+               0x80000731, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               1750,       /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               528000,     /* SDRAM frequency */
+               1100,       /* min voltage */
+               "pll_m",    /* clock source id */
+               0x80000000, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000018, /* EMC_RC */
+                       0x00000053, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000010, /* EMC_RAS */
+                       0x00000006, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x00000009, /* EMC_W2R */
+                       0x00000002, /* EMC_R2P */
+                       0x0000000d, /* EMC_W2P */
+                       0x00000006, /* EMC_RD_RCD */
+                       0x00000006, /* EMC_WR_RCD */
+                       0x00000002, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000009, /* EMC_IBDLY */
+                       0x00090007, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000007, /* EMC_QRST */
+                       0x00000010, /* EMC_RDV_MASK */
+                       0x00000fd8, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000003f6, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x0000000b, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000050, /* EMC_AR2PDEN */
+                       0x00000012, /* EMC_RW2PDEN */
+                       0x0000005a, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000016, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000005, /* EMC_TCLKSTABLE */
+                       0x00000006, /* EMC_TCLKSTOP */
+                       0x00001019, /* EMC_TREFBW */
+                       0x00000008, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000ba88, /* EMC_FBIO_CFG5 */
+                       0xf0120091, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS4 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS5 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS6 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000013d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x07077504, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x016e000c, /* EMC_MRS_WAIT_CNT */
+                       0x016e000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80002066, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x0f000007, /* MC_EMEM_ARB_CFG */
+                       0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RP */
+                       0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06040202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x0010090c, /* MC_EMEM_ARB_DA_COVERS */
+                       0x7428180e, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000009, /* EMC_QUSE */
+                       0x00000007, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000010, /* EMC_RDV */
+                       0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00010000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000909, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00010000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00010000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS2 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000009, /* EMC_QUSE */
+                       0x00000007, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000010, /* EMC_RDV */
+                       0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00010000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000909, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00010000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00010000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS2 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x0000010e, /* MC_PTSA_GRANT_DECREMENT */
+                       0x000d000d, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x000d000f, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x00100012, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x00000012, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00120012, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x00180012, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x00000018, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00180018, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00a3004d, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00a300a3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x73100004, /* EMC_CFG */
+               0x80000941, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               1440,       /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               624000,     /* SDRAM frequency */
+               1100,       /* min voltage */
+               "pll_c",    /* clock source id */
+               0x24000000, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x0000001d, /* EMC_RC */
+                       0x00000062, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000014, /* EMC_RAS */
+                       0x00000007, /* EMC_RP */
+                       0x00000007, /* EMC_R2W */
+                       0x0000000b, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x00000010, /* EMC_W2P */
+                       0x00000007, /* EMC_RD_RCD */
+                       0x00000007, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x0000000a, /* EMC_IBDLY */
+                       0x000c000a, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000007, /* EMC_QRST */
+                       0x00000012, /* EMC_RDV_MASK */
+                       0x000012c4, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000004b1, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x0000000d, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x0000005e, /* EMC_AR2PDEN */
+                       0x00000015, /* EMC_RW2PDEN */
+                       0x0000006b, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000005, /* EMC_TCKE */
+                       0x00000005, /* EMC_TCKESR */
+                       0x00000005, /* EMC_TPD */
+                       0x00000019, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000006, /* EMC_TCLKSTABLE */
+                       0x00000007, /* EMC_TCLKSTOP */
+                       0x00001305, /* EMC_TREFBW */
+                       0x00000009, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000ba88, /* EMC_FBIO_CFG5 */
+                       0xf00d0191, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x007f800b, /* EMC_DLL_XFORM_DQS4 */
+                       0x007f800b, /* EMC_DLL_XFORM_DQS5 */
+                       0x007f800b, /* EMC_DLL_XFORM_DQS6 */
+                       0x007f800b, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000013d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x07077504, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x0160000c, /* EMC_MRS_WAIT_CNT */
+                       0x0160000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x8000261a, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x06000009, /* MC_EMEM_ARB_CFG */
+                       0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_RP */
+                       0x0000000f, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000009, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x07050202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */
+                       0x736a1d10, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x0000000a, /* EMC_QUSE */
+                       0x00000008, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x007f800b, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000012, /* EMC_RDV */
+                       0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000009, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000909, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
+                       0x007f800b, /* EMC_DLL_XFORM_DQS1 */
+                       0x007f800b, /* EMC_DLL_XFORM_DQS2 */
+                       0x007f800b, /* EMC_DLL_XFORM_DQS3 */
+                       0x00000009, /* EMC_DLL_XFORM_DQ1 */
+                       0x00000009, /* EMC_DLL_XFORM_DQ2 */
+                       0x00000009, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x0000000a, /* EMC_QUSE */
+                       0x00000008, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x007f800b, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000012, /* EMC_RDV */
+                       0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000009, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000909, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
+                       0x007f800b, /* EMC_DLL_XFORM_DQS1 */
+                       0x007f800b, /* EMC_DLL_XFORM_DQS2 */
+                       0x007f800b, /* EMC_DLL_XFORM_DQS3 */
+                       0x00000009, /* EMC_DLL_XFORM_DQ1 */
+                       0x00000009, /* EMC_DLL_XFORM_DQ2 */
+                       0x00000009, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x0000013f, /* MC_PTSA_GRANT_DECREMENT */
+                       0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x53200000, /* EMC_CFG */
+               0x80000b61, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200010, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               1440,       /* expected dvfs latency (ns) */
+       },
+       {
+               0x41,       /* Rev 4.0.3 */
+               792000,     /* SDRAM frequency */
+               1100,       /* min voltage */
+               "pll_m",    /* clock source id */
+               0x80000000, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000024, /* EMC_RC */
+                       0x0000007d, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000019, /* EMC_RAS */
+                       0x0000000a, /* EMC_RP */
+                       0x00000009, /* EMC_R2W */
+                       0x0000000d, /* EMC_W2R */
+                       0x00000004, /* EMC_R2P */
+                       0x00000013, /* EMC_W2P */
+                       0x0000000a, /* EMC_RD_RCD */
+                       0x0000000a, /* EMC_WR_RCD */
+                       0x00000004, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000006, /* EMC_WDV */
+                       0x00000006, /* EMC_WDV_MASK */
+                       0x0000000b, /* EMC_IBDLY */
+                       0x000d000a, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000008, /* EMC_QRST */
+                       0x00000014, /* EMC_RDV_MASK */
+                       0x000017e4, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000005f9, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000003, /* EMC_PDEX2WR */
+                       0x00000012, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000077, /* EMC_AR2PDEN */
+                       0x00000018, /* EMC_RW2PDEN */
+                       0x00000087, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000005, /* EMC_TCKE */
+                       0x00000005, /* EMC_TCKESR */
+                       0x00000005, /* EMC_TPD */
+                       0x00000020, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000007, /* EMC_TCLKSTABLE */
+                       0x00000008, /* EMC_TCLKSTOP */
+                       0x00001825, /* EMC_TREFBW */
+                       0x0000000a, /* EMC_QUSE_EXTRA */
+                       0x80000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000ba88, /* EMC_FBIO_CFG5 */
+                       0xf0070191, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00000008, /* EMC_DLL_XFORM_DQS4 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS5 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS6 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000013d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc084, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f508, /* EMC_XM2COMPPADCTRL */
+                       0x07076604, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x0147000c, /* EMC_MRS_WAIT_CNT */
+                       0x0147000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80003018, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x0e00000b, /* MC_EMEM_ARB_CFG */
+                       0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000013, /* MC_EMEM_ARB_TIMING_RC */
+                       0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x08060202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x00170e13, /* MC_EMEM_ARB_DA_COVERS */
+                       0x72cc2414, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x0000000b, /* EMC_QUSE */
+                       0x00000008, /* EMC_EINPUT */
+                       0x00000006, /* EMC_EINPUT_DURATION */
+                       0x00000008, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000d, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000014, /* EMC_RDV */
+                       0x00249249, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x007fc00a, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000b0b, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS1 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS2 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS3 */
+                       0x007fc00a, /* EMC_DLL_XFORM_DQ1 */
+                       0x007fc00a, /* EMC_DLL_XFORM_DQ2 */
+                       0x007fc00a, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x0000000b, /* EMC_QUSE */
+                       0x00000008, /* EMC_EINPUT */
+                       0x00000006, /* EMC_EINPUT_DURATION */
+                       0x00000008, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000d, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000014, /* EMC_RDV */
+                       0x00249249, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x007fc00a, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000b0b, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS1 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS2 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS3 */
+                       0x007fc00a, /* EMC_DLL_XFORM_DQ1 */
+                       0x007fc00a, /* EMC_DLL_XFORM_DQ2 */
+                       0x007fc00a, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000196, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x0010000c, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00100010, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x006d0033, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x006d006d, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x73000000, /* EMC_CFG */
+               0x80000d71, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200218, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               1200,       /* expected dvfs latency (ns) */
+       },
+};
+
+static struct tegra11_emc_table p1640_mt41k128m16_125_table[] = {
+       {
+               0x42,       /* Rev 4.0.3 */
+               12750,      /* SDRAM frequency */
+               900,        /* min voltage */
+               "pll_p",    /* clock source id */
+               0x4000003e, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000000, /* EMC_RC */
+                       0x00000003, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000000, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x00000060, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000005, /* EMC_TXSR */
+                       0x00000005, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000001, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000064, /* EMC_TREFBW */
+                       0x00000005, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x800001c6, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x40040001, /* MC_EMEM_ARB_CFG */
+                       0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x77e30303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x00040320, /* EMC_SEL_DPD_CTRL */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x0000000e, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               57820,      /* expected dvfs latency (ns) */
+       },
+       {
+               0x42,       /* Rev 4.0.3 */
+               20400,      /* SDRAM frequency */
+               900,        /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000026, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000000, /* EMC_RC */
+                       0x00000003, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000000, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x0000009a, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000005, /* EMC_TXSR */
+                       0x00000006, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000001, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x000000a0, /* EMC_TREFBW */
+                       0x00000005, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x40020001, /* MC_EMEM_ARB_CFG */
+                       0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x75430303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x00040320, /* EMC_SEL_DPD_CTRL */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000014, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               35610,      /* expected dvfs latency (ns) */
+       },
+       {
+               0x42,       /* Rev 4.0.3 */
+               40800,      /* SDRAM frequency */
+               900,        /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000012, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000001, /* EMC_RC */
+                       0x00000006, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000001, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x00000134, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000007, /* EMC_TXSR */
+                       0x0000000c, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000002, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x0000013f, /* EMC_TREFBW */
+                       0x00000005, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000370, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0xa0000001, /* MC_EMEM_ARB_CFG */
+                       0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x73630303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x00040320, /* EMC_SEL_DPD_CTRL */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x0000002a, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               20850,      /* expected dvfs latency (ns) */
+       },
+       {
+               0x42,       /* Rev 4.0.3 */
+               68000,      /* SDRAM frequency */
+               900,        /* min voltage */
+               "pll_p",    /* clock source id */
+               0x4000000a, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000003, /* EMC_RC */
+                       0x0000000a, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000002, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x00000202, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000008, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x0000000c, /* EMC_TXSR */
+                       0x00000013, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000003, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000213, /* EMC_TREFBW */
+                       0x00000005, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x00000001, /* MC_EMEM_ARB_CFG */
+                       0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x72c30403, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x00040320, /* EMC_SEL_DPD_CTRL */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000046, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               10720,      /* expected dvfs latency (ns) */
+       },
+       {
+               0x42,       /* Rev 4.0.3 */
+               102000,     /* SDRAM frequency */
+               900,        /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000006, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000004, /* EMC_RC */
+                       0x00000010, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000003, /* EMC_RAS */
+                       0x00000001, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000001, /* EMC_RD_RCD */
+                       0x00000001, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x00000303, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x0000000d, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000012, /* EMC_TXSR */
+                       0x0000001c, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000005, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x0000031c, /* EMC_TREFBW */
+                       0x00000005, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000042, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000714, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x08000001, /* MC_EMEM_ARB_CFG */
+                       0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
+                       0x72830504, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x00040320, /* EMC_SEL_DPD_CTRL */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000068, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               6890,       /* expected dvfs latency (ns) */
+       },
+       {
+               0x42,       /* Rev 4.0.3 */
+               204000,     /* SDRAM frequency */
+               900,        /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000002, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000009, /* EMC_RC */
+                       0x00000020, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000007, /* EMC_RAS */
+                       0x00000002, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000002, /* EMC_RD_RCD */
+                       0x00000002, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x00000006, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x00000607, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x0000001d, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000023, /* EMC_TXSR */
+                       0x00000038, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000009, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000638, /* EMC_TREFBW */
+                       0x00000006, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000aa88, /* EMC_FBIO_CFG5 */
+                       0x000000a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS4 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS5 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS6 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x05057404, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x01000003, /* MC_EMEM_ARB_CFG */
+                       0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0405, /* MC_EMEM_ARB_DA_COVERS */
+                       0x72440a06, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x00040320, /* EMC_SEL_DPD_CTRL */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000004, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000808, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS1 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS2 */
+                       0x0006c000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00048000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x000000d0, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x7320000e, /* EMC_CFG */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               3420,       /* expected dvfs latency (ns) */
+       },
+       {
+               0x42,       /* Rev 4.0.3 */
+               312000,     /* SDRAM frequency */
+               1000,       /* min voltage */
+               "pll_c",    /* clock source id */
+               0x24000002, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x0000000e, /* EMC_RC */
+                       0x00000030, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000009, /* EMC_RAS */
+                       0x00000003, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x00000008, /* EMC_W2R */
+                       0x00000002, /* EMC_R2P */
+                       0x00000009, /* EMC_W2P */
+                       0x00000003, /* EMC_RD_RCD */
+                       0x00000003, /* EMC_WR_RCD */
+                       0x00000002, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000004, /* EMC_WDV */
+                       0x00000004, /* EMC_WDV_MASK */
+                       0x00000007, /* EMC_IBDLY */
+                       0x00080006, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000d, /* EMC_RDV_MASK */
+                       0x00000945, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000001, /* EMC_PDEX2WR */
+                       0x00000008, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x0000002e, /* EMC_AR2PDEN */
+                       0x0000000e, /* EMC_RW2PDEN */
+                       0x00000036, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x0000000d, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000986, /* EMC_TREFBW */
+                       0x00000006, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000ba88, /* EMC_FBIO_CFG5 */
+                       0x002c00a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00038000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0001013d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x0190000c, /* EMC_MRS_WAIT_CNT */
+                       0x0190000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80001395, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x0b000004, /* MC_EMEM_ARB_CFG */
+                       0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06040202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000b0607, /* MC_EMEM_ARB_DA_COVERS */
+                       0x76e50f08, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x00040320, /* EMC_SEL_DPD_CTRL */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00038000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000b, /* EMC_QSAFE */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00024000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00024000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00024000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00038000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000b, /* EMC_QSAFE */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000d, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00024000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00024000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00024000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00028000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000140, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x5300000e, /* EMC_CFG */
+               0x80000321, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200000, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               2180,       /* expected dvfs latency (ns) */
+       },
+       {
+               0x42,       /* Rev 4.0.3 */
+               408000,     /* SDRAM frequency */
+               1000,       /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000000, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000012, /* EMC_RC */
+                       0x00000040, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x0000000d, /* EMC_RAS */
+                       0x00000004, /* EMC_RP */
+                       0x00000005, /* EMC_R2W */
+                       0x00000009, /* EMC_W2R */
+                       0x00000002, /* EMC_R2P */
+                       0x0000000c, /* EMC_W2P */
+                       0x00000004, /* EMC_RD_RCD */
+                       0x00000004, /* EMC_WR_RCD */
+                       0x00000002, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000004, /* EMC_WDV */
+                       0x00000004, /* EMC_WDV_MASK */
+                       0x00000007, /* EMC_IBDLY */
+                       0x00080006, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000e, /* EMC_RDV_MASK */
+                       0x00000c2f, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000001, /* EMC_PDEX2WR */
+                       0x00000008, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x0000003d, /* EMC_AR2PDEN */
+                       0x00000011, /* EMC_RW2PDEN */
+                       0x00000046, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x00000011, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000c70, /* EMC_TREFBW */
+                       0x00000006, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000ba88, /* EMC_FBIO_CFG5 */
+                       0x002c0080, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00028000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0001013d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x03035504, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x0181000c, /* EMC_MRS_WAIT_CNT */
+                       0x0181000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80001944, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x02000006, /* MC_EMEM_ARB_CFG */
+                       0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+                       0x0000000a, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06040202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000e070a, /* MC_EMEM_ARB_DA_COVERS */
+                       0x7547130b, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x00040320, /* EMC_SEL_DPD_CTRL */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00028000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000e, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00020001, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000005, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000005, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000005, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00020001, /* EMC_DLL_XFORM_DQ1 */
+                       0x00020001, /* EMC_DLL_XFORM_DQ2 */
+                       0x00020001, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000007, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00028000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000e, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00020001, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000005, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000005, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000005, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00020001, /* EMC_DLL_XFORM_DQ1 */
+                       0x00020001, /* EMC_DLL_XFORM_DQ2 */
+                       0x00020001, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x000000d1, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x53000006, /* EMC_CFG */
+               0x80000731, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               1750,       /* expected dvfs latency (ns) */
+       },
+       {
+               0x42,       /* Rev 4.0.3 */
+               624000,     /* SDRAM frequency */
+               1100,       /* min voltage */
+               "pll_c",    /* clock source id */
+               0x24000000, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x0000001d, /* EMC_RC */
+                       0x00000062, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000014, /* EMC_RAS */
+                       0x00000007, /* EMC_RP */
+                       0x00000007, /* EMC_R2W */
+                       0x0000000b, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x00000010, /* EMC_W2P */
+                       0x00000007, /* EMC_RD_RCD */
+                       0x00000007, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_WDV_MASK */
+                       0x0000000a, /* EMC_IBDLY */
+                       0x000c000a, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000007, /* EMC_QRST */
+                       0x00000012, /* EMC_RDV_MASK */
+                       0x000012c4, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000004b1, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x0000000d, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x0000005e, /* EMC_AR2PDEN */
+                       0x00000015, /* EMC_RW2PDEN */
+                       0x0000006b, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000005, /* EMC_TCKE */
+                       0x00000005, /* EMC_TCKESR */
+                       0x00000005, /* EMC_TPD */
+                       0x00000019, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000006, /* EMC_TCLKSTABLE */
+                       0x00000007, /* EMC_TCLKSTOP */
+                       0x00001305, /* EMC_TREFBW */
+                       0x00000009, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000ba88, /* EMC_FBIO_CFG5 */
+                       0xf00d0191, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x007fc00b, /* EMC_DLL_XFORM_DQS4 */
+                       0x007fc00b, /* EMC_DLL_XFORM_DQS5 */
+                       0x007fc00b, /* EMC_DLL_XFORM_DQS6 */
+                       0x007fc00b, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000013d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x07077504, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x0160000c, /* EMC_MRS_WAIT_CNT */
+                       0x0160000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x8000261a, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x06000009, /* MC_EMEM_ARB_CFG */
+                       0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_RP */
+                       0x0000000f, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000009, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x07050202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */
+                       0x736a1d10, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x00040320, /* EMC_SEL_DPD_CTRL */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x0000000a, /* EMC_QUSE */
+                       0x00000008, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x007fc00b, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000012, /* EMC_RDV */
+                       0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000009, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000909, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
+                       0x007fc00b, /* EMC_DLL_XFORM_DQS1 */
+                       0x007fc00b, /* EMC_DLL_XFORM_DQS2 */
+                       0x007fc00b, /* EMC_DLL_XFORM_DQS3 */
+                       0x00000009, /* EMC_DLL_XFORM_DQ1 */
+                       0x00000009, /* EMC_DLL_XFORM_DQ2 */
+                       0x00000009, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x0000000a, /* EMC_QUSE */
+                       0x00000008, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x007fc00b, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000012, /* EMC_RDV */
+                       0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000009, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000909, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
+                       0x007fc00b, /* EMC_DLL_XFORM_DQS1 */
+                       0x007fc00b, /* EMC_DLL_XFORM_DQS2 */
+                       0x007fc00b, /* EMC_DLL_XFORM_DQS3 */
+                       0x00000009, /* EMC_DLL_XFORM_DQ1 */
+                       0x00000009, /* EMC_DLL_XFORM_DQ2 */
+                       0x00000009, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x0000013f, /* MC_PTSA_GRANT_DECREMENT */
+                       0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x53200000, /* EMC_CFG */
+               0x80000b61, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200010, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               1230,       /* expected dvfs latency (ns) */
+       },
+       {
+               0x42,       /* Rev 4.0.3 */
+               792000,     /* SDRAM frequency */
+               1100,       /* min voltage */
+               "pll_m",    /* clock source id */
+               0x80000000, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000024, /* EMC_RC */
+                       0x0000007d, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000019, /* EMC_RAS */
+                       0x0000000a, /* EMC_RP */
+                       0x00000009, /* EMC_R2W */
+                       0x0000000d, /* EMC_W2R */
+                       0x00000004, /* EMC_R2P */
+                       0x00000013, /* EMC_W2P */
+                       0x0000000a, /* EMC_RD_RCD */
+                       0x0000000a, /* EMC_WR_RCD */
+                       0x00000004, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000006, /* EMC_WDV */
+                       0x00000006, /* EMC_WDV_MASK */
+                       0x0000000b, /* EMC_IBDLY */
+                       0x000d000a, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000008, /* EMC_QRST */
+                       0x00000014, /* EMC_RDV_MASK */
+                       0x000017e4, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000005f9, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000003, /* EMC_PDEX2WR */
+                       0x00000012, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000077, /* EMC_AR2PDEN */
+                       0x00000018, /* EMC_RW2PDEN */
+                       0x00000087, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000005, /* EMC_TCKE */
+                       0x00000005, /* EMC_TCKESR */
+                       0x00000005, /* EMC_TPD */
+                       0x00000020, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000007, /* EMC_TCLKSTABLE */
+                       0x00000008, /* EMC_TCLKSTOP */
+                       0x00001825, /* EMC_TREFBW */
+                       0x0000000a, /* EMC_QUSE_EXTRA */
+                       0x80000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0000ba88, /* EMC_FBIO_CFG5 */
+                       0xf0070191, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00004008, /* EMC_DLL_XFORM_DQS4 */
+                       0x00004008, /* EMC_DLL_XFORM_DQS5 */
+                       0x00004008, /* EMC_DLL_XFORM_DQS6 */
+                       0x00004008, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000013d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc084, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f508, /* EMC_XM2COMPPADCTRL */
+                       0x07076604, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x0147000c, /* EMC_MRS_WAIT_CNT */
+                       0x0147000c, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80003018, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x0e00000b, /* MC_EMEM_ARB_CFG */
+                       0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000013, /* MC_EMEM_ARB_TIMING_RC */
+                       0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x08060202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x00170e13, /* MC_EMEM_ARB_DA_COVERS */
+                       0x72cc2414, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x00040000, /* EMC_SEL_DPD_CTRL */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x0000000b, /* EMC_QUSE */
+                       0x00000008, /* EMC_EINPUT */
+                       0x00000006, /* EMC_EINPUT_DURATION */
+                       0x00004008, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000d, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000014, /* EMC_RDV */
+                       0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x0000400a, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000b0b, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00004008, /* EMC_DLL_XFORM_DQS1 */
+                       0x00004008, /* EMC_DLL_XFORM_DQS2 */
+                       0x00004008, /* EMC_DLL_XFORM_DQS3 */
+                       0x0000400a, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000400a, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000400a, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x0000000b, /* EMC_QUSE */
+                       0x00000008, /* EMC_EINPUT */
+                       0x00000006, /* EMC_EINPUT_DURATION */
+                       0x00004008, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000d, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000014, /* EMC_RDV */
+                       0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x0000400a, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000b0b, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
+                       0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00004008, /* EMC_DLL_XFORM_DQS1 */
+                       0x00004008, /* EMC_DLL_XFORM_DQS2 */
+                       0x00004008, /* EMC_DLL_XFORM_DQS3 */
+                       0x0000400a, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000400a, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000400a, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000196, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x0010000c, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00100010, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x006d0033, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x006d006d, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x53000000, /* EMC_CFG */
+               0x80000d71, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200218, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               1200,       /* expected dvfs latency (ns) */
+       },
+};
+
+static struct tegra11_emc_pdata e1569_mt41k128m16_125_pdata = {
+       .description = "e1569_mt41k128m16_125",
+       .tables = e1569_mt41k128m16_125_table,
+       .num_tables = ARRAY_SIZE(e1569_mt41k128m16_125_table),
+};
+
+static struct tegra11_emc_pdata p1640_mt41k128m16_125_pdata = {
+       .description = "p1640_mt41k128m16_125",
+       .tables = p1640_mt41k128m16_125_table,
+       .num_tables = ARRAY_SIZE(p1640_mt41k128m16_125_table),
+};
+
+static struct tegra11_emc_pdata *tegranote7c_get_emc_data(void)
+{
+       struct board_info board_info;
+
+       tegra_get_board_info(&board_info);
+
+       if (board_info.board_id == BOARD_E1569)
+               return &e1569_mt41k128m16_125_pdata;
+       else if (board_info.board_id == BOARD_P1640)
+               return &p1640_mt41k128m16_125_pdata;
+       else
+               return NULL;
+}
+
+int __init tegranote7c_emc_init(void)
+{
+       tegra_emc_device.dev.platform_data = tegranote7c_get_emc_data();
+       platform_device_register(&tegra_emc_device);
+       tegra11_emc_init();
+       return 0;
+}
diff --git a/arch/arm/mach-tegra/board-tegranote7c-panel.c b/arch/arm/mach-tegra/board-tegranote7c-panel.c
new file mode 100644 (file)
index 0000000..20c6983
--- /dev/null
@@ -0,0 +1,568 @@
+/*
+ * arch/arm/mach-tegra/board-tegranote7c-panel.c
+ *
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/ioport.h>
+#include <linux/fb.h>
+#include <linux/nvmap.h>
+#include <linux/of.h>
+#include <linux/nvhost.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/tegra_pwm_bl.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pwm_backlight.h>
+
+#include <mach/irqs.h>
+#include <mach/iomap.h>
+#include <mach/dc.h>
+#include <mach/pinmux.h>
+#include <mach/pinmux-t11.h>
+
+#include "board.h"
+#include "devices.h"
+#include "gpio-names.h"
+#include "board-panel.h"
+#include "common.h"
+#include "tegra11_host1x_devices.h"
+
+struct platform_device * __init tegranote7c_host1x_init(void)
+{
+       struct platform_device *pdev = NULL;
+
+#ifdef CONFIG_TEGRA_GRHOST
+       pdev = tegra11_register_host1x_devices();
+       if (!pdev) {
+               pr_err("host1x devices registration failed\n");
+               return NULL;
+       }
+#endif
+       return pdev;
+}
+
+#ifdef CONFIG_TEGRA_DC
+
+/* HDMI Hotplug detection pin */
+#define tegranote7c_hdmi_hpd   TEGRA_GPIO_PN7
+
+static struct regulator *tegranote7c_hdmi_reg;
+static struct regulator *tegranote7c_hdmi_pll;
+static struct regulator *tegranote7c_hdmi_vddio;
+
+static struct resource tegranote7c_disp1_resources[] = {
+       {
+               .name   = "irq",
+               .start  = INT_DISPLAY_GENERAL,
+               .end    = INT_DISPLAY_GENERAL,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               .name   = "regs",
+               .start  = TEGRA_DISPLAY_BASE,
+               .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "fbmem",
+               .start  = 0, /* Filled in by tegranote7c_panel_init() */
+               .end    = 0, /* Filled in by tegranote7c_panel_init() */
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "ganged_dsia_regs",
+               .start  = 0, /* Filled in the panel file by init_resources() */
+               .end    = 0, /* Filled in the panel file by init_resources() */
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "ganged_dsib_regs",
+               .start  = 0, /* Filled in the panel file by init_resources() */
+               .end    = 0, /* Filled in the panel file by init_resources() */
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "dsi_regs",
+               .start  = 0, /* Filled in the panel file by init_resources() */
+               .end    = 0, /* Filled in the panel file by init_resources() */
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "mipi_cal",
+               .start  = TEGRA_MIPI_CAL_BASE,
+               .end    = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct resource tegranote7c_disp2_resources[] = {
+       {
+               .name   = "irq",
+               .start  = INT_DISPLAY_B_GENERAL,
+               .end    = INT_DISPLAY_B_GENERAL,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               .name   = "regs",
+               .start  = TEGRA_DISPLAY2_BASE,
+               .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "fbmem",
+               .start  = 0, /* Filled in by tegranote7c_panel_init() */
+               .end    = 0, /* Filled in by tegranote7c_panel_init() */
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "hdmi_regs",
+               .start  = TEGRA_HDMI_BASE,
+               .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+
+static struct tegra_dc_sd_settings sd_settings;
+
+static struct tegra_dc_out tegranote7c_disp1_out = {
+       .type           = TEGRA_DC_OUT_DSI,
+       .sd_settings    = &sd_settings,
+};
+
+static int tegranote7c_hdmi_enable(struct device *dev)
+{
+       int ret;
+       if (!tegranote7c_hdmi_reg) {
+               tegranote7c_hdmi_reg = regulator_get(dev, "avdd_hdmi");
+               if (IS_ERR_OR_NULL(tegranote7c_hdmi_reg)) {
+                       pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
+                       tegranote7c_hdmi_reg = NULL;
+                       return PTR_ERR(tegranote7c_hdmi_reg);
+               }
+       }
+       ret = regulator_enable(tegranote7c_hdmi_reg);
+       if (ret < 0) {
+               pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
+               return ret;
+       }
+       if (!tegranote7c_hdmi_pll) {
+               tegranote7c_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll");
+               if (IS_ERR_OR_NULL(tegranote7c_hdmi_pll)) {
+                       pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
+                       tegranote7c_hdmi_pll = NULL;
+                       regulator_put(tegranote7c_hdmi_reg);
+                       tegranote7c_hdmi_reg = NULL;
+                       return PTR_ERR(tegranote7c_hdmi_pll);
+               }
+       }
+       ret = regulator_enable(tegranote7c_hdmi_pll);
+       if (ret < 0) {
+               pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
+               return ret;
+       }
+       return 0;
+}
+
+static int tegranote7c_hdmi_disable(void)
+{
+       if (tegranote7c_hdmi_reg) {
+               regulator_disable(tegranote7c_hdmi_reg);
+               regulator_put(tegranote7c_hdmi_reg);
+               tegranote7c_hdmi_reg = NULL;
+       }
+
+       if (tegranote7c_hdmi_pll) {
+               regulator_disable(tegranote7c_hdmi_pll);
+               regulator_put(tegranote7c_hdmi_pll);
+               tegranote7c_hdmi_pll = NULL;
+       }
+
+       return 0;
+}
+
+static int tegranote7c_hdmi_postsuspend(void)
+{
+       if (tegranote7c_hdmi_vddio) {
+               regulator_disable(tegranote7c_hdmi_vddio);
+               regulator_put(tegranote7c_hdmi_vddio);
+               tegranote7c_hdmi_vddio = NULL;
+       }
+       return 0;
+}
+
+static int tegranote7c_hdmi_hotplug_init(struct device *dev)
+{
+       if (!tegranote7c_hdmi_vddio) {
+               tegranote7c_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0");
+               if (WARN_ON(IS_ERR(tegranote7c_hdmi_vddio))) {
+                       pr_err("%s: couldn't get regulator vdd_hdmi_5v0: %ld\n",
+                               __func__, PTR_ERR(tegranote7c_hdmi_vddio));
+                               tegranote7c_hdmi_vddio = NULL;
+               } else {
+                       regulator_enable(tegranote7c_hdmi_vddio);
+                       mdelay(5);
+               }
+       }
+
+       return 0;
+}
+
+static void tegranote7c_hdmi_hotplug_report(bool state)
+{
+       if (state) {
+               tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SDA,
+                                               TEGRA_PUPD_PULL_DOWN);
+               tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SCL,
+                                               TEGRA_PUPD_PULL_DOWN);
+       } else {
+               tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SDA,
+                                               TEGRA_PUPD_NORMAL);
+               tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SCL,
+                                               TEGRA_PUPD_NORMAL);
+       }
+}
+
+static struct tegra_dc_out tegranote7c_disp2_out = {
+       .type           = TEGRA_DC_OUT_HDMI,
+       .flags          = TEGRA_DC_OUT_HOTPLUG_HIGH,
+       .parent_clk     = "pll_d2_out0",
+
+       .dcc_bus        = 3,
+       .hotplug_gpio   = tegranote7c_hdmi_hpd,
+
+       .max_pixclock   = KHZ2PICOS(148500),
+
+       .align          = TEGRA_DC_ALIGN_MSB,
+       .order          = TEGRA_DC_ORDER_RED_BLUE,
+
+       .enable         = tegranote7c_hdmi_enable,
+       .disable        = tegranote7c_hdmi_disable,
+       .postsuspend    = tegranote7c_hdmi_postsuspend,
+       .hotplug_init   = tegranote7c_hdmi_hotplug_init,
+       .hotplug_report = tegranote7c_hdmi_hotplug_report,
+};
+
+static struct tegra_fb_data tegranote7c_disp1_fb_data = {
+       .win            = 0,
+       .bits_per_pixel = 32,
+       .flags          = TEGRA_FB_FLIP_ON_PROBE,
+};
+
+static struct tegra_dc_platform_data tegranote7c_disp1_pdata = {
+       .flags          = TEGRA_DC_FLAG_ENABLED,
+       .default_out    = &tegranote7c_disp1_out,
+       .fb             = &tegranote7c_disp1_fb_data,
+       .emc_clk_rate   = 204000000,
+#ifdef CONFIG_TEGRA_DC_CMU
+       .cmu_enable     = 0,
+#endif
+};
+
+static struct tegra_fb_data tegranote7c_disp2_fb_data = {
+       .win            = 0,
+       .xres           = 1024,
+       .yres           = 600,
+       .bits_per_pixel = 32,
+       .flags          = TEGRA_FB_FLIP_ON_PROBE,
+};
+
+static struct tegra_dc_platform_data tegranote7c_disp2_pdata = {
+       .flags          = 0,
+       .default_out    = &tegranote7c_disp2_out,
+       .fb             = &tegranote7c_disp2_fb_data,
+       .emc_clk_rate   = 300000000,
+};
+
+static struct platform_device tegranote7c_disp2_device = {
+       .name           = "tegradc",
+       .id             = 1,
+       .resource       = tegranote7c_disp2_resources,
+       .num_resources  = ARRAY_SIZE(tegranote7c_disp2_resources),
+       .dev = {
+               .platform_data = &tegranote7c_disp2_pdata,
+       },
+};
+
+static struct platform_device tegranote7c_disp1_device = {
+       .name           = "tegradc",
+       .id             = 0,
+       .resource       = tegranote7c_disp1_resources,
+       .num_resources  = ARRAY_SIZE(tegranote7c_disp1_resources),
+       .dev = {
+               .platform_data = &tegranote7c_disp1_pdata,
+       },
+};
+
+static struct nvmap_platform_carveout tegranote7c_carveouts[] = {
+       [0] = {
+               .name           = "iram",
+               .usage_mask     = NVMAP_HEAP_CARVEOUT_IRAM,
+               .base           = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
+               .size           = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
+               .buddy_size     = 0, /* no buddy allocation for IRAM */
+       },
+       [1] = {
+               .name           = "generic-0",
+               .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
+               .base           = 0, /* Filled in by tegranote7c_panel_init() */
+               .size           = 0, /* Filled in by tegranote7c_panel_init() */
+               .buddy_size     = SZ_32K,
+       },
+       [2] = {
+               .name           = "vpr",
+               .usage_mask     = NVMAP_HEAP_CARVEOUT_VPR,
+               .base           = 0, /* Filled in by tegranote7c_panel_init() */
+               .size           = 0, /* Filled in by tegranote7c_panel_init() */
+               .buddy_size     = SZ_32K,
+       },
+};
+
+static struct nvmap_platform_data tegranote7c_nvmap_data = {
+       .carveouts      = tegranote7c_carveouts,
+       .nr_carveouts   = ARRAY_SIZE(tegranote7c_carveouts),
+};
+static struct platform_device tegranote7c_nvmap_device = {
+       .name   = "tegra-nvmap",
+       .id     = -1,
+       .dev    = {
+               .platform_data = &tegranote7c_nvmap_data,
+       },
+};
+
+static struct tegra_dc_sd_settings tegranote7c_sd_settings = {
+       .enable = 0,
+       .use_auto_pwm = false,
+       .hw_update_delay = 0,
+       .bin_width = -1,
+       .aggressiveness = 5,
+       .use_vid_luma = false,
+       .phase_in_adjustments = 0,
+       .k_limit_enable = true,
+       .k_limit = 200,
+       .sd_window_enable = false,
+       .soft_clipping_enable = true,
+       /* Low soft clipping threshold to compensate for aggressive k_limit */
+       .soft_clipping_threshold = 128,
+       .smooth_k_enable = true,
+       .smooth_k_incr = 128,
+       /* Default video coefficients */
+       .coeff = {5, 9, 2},
+       .fc = {0, 0},
+       /* Immediate backlight changes */
+       .blp = {1024, 255},
+       /* Gammas: R: 2.2 G: 2.2 B: 2.2 */
+       /* Default BL TF */
+       .bltf = {
+                       {
+                               {57, 65, 73, 82},
+                               {92, 103, 114, 125},
+                               {138, 150, 164, 178},
+                               {193, 208, 224, 241},
+                       },
+               },
+       /* Default LUT */
+       .lut = {
+                       {
+                               {255, 255, 255},
+                               {199, 199, 199},
+                               {153, 153, 153},
+                               {116, 116, 116},
+                               {85, 85, 85},
+                               {59, 59, 59},
+                               {36, 36, 36},
+                               {17, 17, 17},
+                               {0, 0, 0},
+                       },
+               },
+       .sd_brightness = &sd_brightness,
+       .use_vpulse2 = true,
+};
+
+static void tegranote7c_panel_select(void)
+{
+       struct tegra_panel *panel = NULL;
+
+       bool is_dt = of_have_populated_dt();
+
+       panel = &dsi_lgd_wxga_7_0;
+
+       if (panel && !is_dt) {
+               if (panel->init_sd_settings)
+                       panel->init_sd_settings(&sd_settings);
+
+               if (panel->init_dc_out)
+                       panel->init_dc_out(&tegranote7c_disp1_out);
+
+               if (panel->init_fb_data)
+                       panel->init_fb_data(&tegranote7c_disp1_fb_data);
+
+               if (panel->init_cmu_data)
+                       panel->init_cmu_data(&tegranote7c_disp1_pdata);
+
+               if (panel->set_disp_device)
+                       panel->set_disp_device(&tegranote7c_disp1_device);
+
+               if (panel->init_resources)
+                       panel->init_resources(tegranote7c_disp1_resources,
+                               ARRAY_SIZE(tegranote7c_disp1_resources));
+
+               if (panel->register_bl_dev)
+                       panel->register_bl_dev();
+
+               if (panel->register_i2c_bridge)
+                       panel->register_i2c_bridge();
+       }
+
+}
+
+static void fb2_copy_or_clear(void)
+{
+       /*
+        * If the bootloader fb2 is valid, copy it to the fb2, or else
+        * clear fb2 to avoid garbage on dispaly2.
+        */
+       if (tegra_bootloader_fb2_size)
+               tegra_move_framebuffer(tegra_fb2_start,
+                       tegra_bootloader_fb2_start,
+                       min(tegra_fb2_size, tegra_bootloader_fb2_size));
+       else
+               tegra_clear_framebuffer(tegra_fb2_start, tegra_fb2_size);
+}
+
+int tegranote7c_init_hdmi(struct platform_device *pdev,
+                    struct platform_device *phost1x)
+{
+       int err = 0;
+       struct resource __maybe_unused *res;
+
+#ifdef CONFIG_ANDROID
+       /* In charger mode, will not register display controller 1
+        * No need to copy or clear fb2, either.
+        */
+       if (get_androidboot_mode_charger())
+               return 0;
+#endif
+
+       if (!of_have_populated_dt()) {
+               fb2_copy_or_clear();
+               res = platform_get_resource_byname(pdev,
+                       IORESOURCE_MEM, "fbmem");
+               res->start = tegra_fb2_start;
+               res->end = tegra_fb2_start + tegra_fb2_size - 1;
+
+               pdev->dev.parent = &phost1x->dev;
+               err = platform_device_register(pdev);
+               if (err) {
+                       pr_err("disp2 device registration failed\n");
+                       return err;
+               }
+       } else {
+#ifdef CONFIG_OF
+               struct device_node *hdmi_node = NULL;
+
+               hdmi_node = of_find_node_by_path("/host1x/hdmi");
+               if (hdmi_node && of_device_is_available(hdmi_node))
+#endif
+                       fb2_copy_or_clear();
+       }
+       return 0;
+}
+
+int __init tegranote7c_panel_init(void)
+{
+       int err = 0;
+       struct resource __maybe_unused *res;
+       struct platform_device *phost1x = NULL;
+
+       bool is_dt = of_have_populated_dt();
+
+       sd_settings = tegranote7c_sd_settings;
+
+       tegranote7c_panel_select();
+
+#ifdef CONFIG_TEGRA_NVMAP
+       tegranote7c_carveouts[1].base = tegra_carveout_start;
+       tegranote7c_carveouts[1].size = tegra_carveout_size;
+       tegranote7c_carveouts[2].base = tegra_vpr_start;
+       tegranote7c_carveouts[2].size = tegra_vpr_size;
+
+       err = platform_device_register(&tegranote7c_nvmap_device);
+       if (err) {
+               pr_err("nvmap device registration failed\n");
+               return err;
+       }
+#endif
+
+       if (!is_dt)
+               phost1x = tegranote7c_host1x_init();
+       else
+               phost1x = to_platform_device(bus_find_device_by_name(
+                       &platform_bus_type, NULL, "host1x"));
+       if (!phost1x) {
+               pr_err("host1x devices registration failed\n");
+               return -EINVAL;
+       }
+
+       gpio_request(tegranote7c_hdmi_hpd, "hdmi_hpd");
+       gpio_direction_input(tegranote7c_hdmi_hpd);
+
+       if (!of_have_populated_dt()) {
+               res = platform_get_resource_byname(&tegranote7c_disp1_device,
+                                        IORESOURCE_MEM, "fbmem");
+               res->start = tegra_fb_start;
+               res->end = tegra_fb_start + tegra_fb_size - 1;
+       }
+
+       /* Copy the bootloader fb to the fb. */
+       __tegra_move_framebuffer(&tegranote7c_nvmap_device,
+               tegra_fb_start, tegra_bootloader_fb_start,
+                       min(tegra_fb_size, tegra_bootloader_fb_size));
+
+       if (!of_have_populated_dt()) {
+               tegranote7c_disp1_device.dev.parent = &phost1x->dev;
+               err = platform_device_register(&tegranote7c_disp1_device);
+               if (err) {
+                       pr_err("disp1 device registration failed\n");
+                       return err;
+               }
+       }
+
+       err = tegranote7c_init_hdmi(&tegranote7c_disp2_device, phost1x);
+       if (err)
+               return err;
+
+#ifdef CONFIG_TEGRA_NVAVP
+       nvavp_device.dev.parent = &phost1x->dev;
+       err = platform_device_register(&nvavp_device);
+       if (err) {
+               pr_err("nvavp device registration failed\n");
+               return err;
+       }
+#endif
+       return err;
+}
+#else
+int __init tegranote7c_panel_init(void)
+{
+       if (tegranote7c_host1x_init())
+               return 0;
+       else
+               return -EINVAL;
+}
+#endif
diff --git a/arch/arm/mach-tegra/board-tegranote7c-pinmux-t11x.h b/arch/arm/mach-tegra/board-tegranote7c-pinmux-t11x.h
new file mode 100644 (file)
index 0000000..cecda57
--- /dev/null
@@ -0,0 +1,648 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* DO NOT EDIT THIS FILE. THIS FILE IS GENERATED FROM TEGRANOTE7C_PINMUX.XLSM */
+
+
+static __initdata struct tegra_pingroup_config tegranote7c_pinmux_common[] = {
+
+       /* EXTPERIPH1 pinmux */
+       DEFAULT_PINMUX(CLK1_OUT,      EXTPERIPH1,  NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2S0 pinmux */
+       DEFAULT_PINMUX(DAP1_DIN,      I2S0,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP1_DOUT,     I2S0,        NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(DAP1_FS,       I2S0,        NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(DAP1_SCLK,     I2S0,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2S1 pinmux */
+       DEFAULT_PINMUX(DAP2_DIN,      I2S1,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP2_DOUT,     I2S1,        NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(DAP2_FS,       I2S1,        NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(DAP2_SCLK,     I2S1,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* CLDVFS pinmux */
+       DEFAULT_PINMUX(DVFS_PWM,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(DVFS_CLK,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+
+       /* SPI1 pinmux */
+       DEFAULT_PINMUX(ULPI_CLK,      SPI1,        NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DIR,      SPI1,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_NXT,      SPI1,        NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_STP,      SPI1,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2C3 pinmux */
+       I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+       I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+       /* VI_ALT3 pinmux */
+       VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+       VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+
+       /* I2C2 pinmux */
+       I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+       I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+       /* UARTD pinmux */
+       DEFAULT_PINMUX(GMI_A16,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(GMI_A17,       UARTD,       NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_A18,       UARTD,       NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_A19,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* SPI4 pinmux */
+       DEFAULT_PINMUX(GMI_AD5,       SPI4,        NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(GMI_AD6,       SPI4,        NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(GMI_AD7,       SPI4,        PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_WR_N,      SPI4,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* PWM1 pinmux */
+       DEFAULT_PINMUX(GMI_AD9,       PWM1,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* SOC pinmux */
+       DEFAULT_PINMUX(GMI_CS1_N,     SOC,         PULL_UP,   TRISTATE, INPUT),
+
+       /* BLINK pinmux */
+       DEFAULT_PINMUX(CLK_32K_OUT,   BLINK,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* EXTPERIPH2 pinmux */
+       DEFAULT_PINMUX(CLK2_OUT,      EXTPERIPH2,  NORMAL,    NORMAL,   OUTPUT),
+
+       /* SDMMC1 pinmux */
+       DEFAULT_PINMUX(SDMMC1_CLK,    SDMMC1,      NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_CMD,    SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT0,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT1,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT2,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT3,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+
+       /* SDMMC3 pinmux */
+       DEFAULT_PINMUX(SDMMC3_CLK,    SDMMC3,      NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(SDMMC3_CMD,    SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT0,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT1,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT2,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT3,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3,  PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3,   PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(KB_COL4,       SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CD_N,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+
+       /* SDMMC4 pinmux */
+       DEFAULT_PINMUX(SDMMC4_CLK,    SDMMC4,      NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_CMD,    SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT0,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT1,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT2,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT3,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT4,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT5,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT6,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT7,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+
+       /* UARTA pinmux */
+       DEFAULT_PINMUX(KB_ROW10,      UARTA,       PULL_DOWN, NORMAL,   INPUT),
+       DEFAULT_PINMUX(KB_ROW9,       UARTA,       NORMAL,    NORMAL,   OUTPUT),
+
+       DEFAULT_PINMUX(KB_ROW6,       KBC,         PULL_DOWN, NORMAL,   INPUT),
+
+       /* KBC pinmux */
+       DEFAULT_PINMUX(KB_ROW8,       KBC,         PULL_UP,   NORMAL,   INPUT),
+
+       /* I2CPWR pinmux */
+       I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+       I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+       /* SYSCLK pinmux */
+       DEFAULT_PINMUX(SYS_CLK_REQ,   SYSCLK,      NORMAL,    NORMAL,   OUTPUT),
+
+       /* RTCK pinmux */
+       DEFAULT_PINMUX(JTAG_RTCK,     RTCK,        NORMAL,    NORMAL,   INPUT),
+
+       /* CLK pinmux */
+       DEFAULT_PINMUX(CLK_32K_IN,    CLK,         NORMAL,    NORMAL,   INPUT),
+
+       /* PWRON pinmux */
+       DEFAULT_PINMUX(CORE_PWR_REQ,  PWRON,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* CPU pinmux */
+       DEFAULT_PINMUX(CPU_PWR_REQ,   CPU,         NORMAL,    NORMAL,   OUTPUT),
+
+       /* PMI pinmux */
+       DEFAULT_PINMUX(PWR_INT_N,     PMI,         PULL_UP,   NORMAL,   INPUT),
+
+       /* RESET_OUT_N pinmux */
+       DEFAULT_PINMUX(RESET_OUT_N,   RESET_OUT_N, NORMAL,    NORMAL,   OUTPUT),
+
+       /* EXTPERIPH3 pinmux */
+       DEFAULT_PINMUX(CLK3_OUT,      EXTPERIPH3,  NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2S3 pinmux */
+       DEFAULT_PINMUX(DAP4_DIN,      I2S3,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP4_DOUT,     I2S3,        NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(DAP4_FS,       I2S3,        NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(DAP4_SCLK,     I2S3,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2C1 pinmux */
+       I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+       I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+       /* UARTB pinmux */
+       DEFAULT_PINMUX(UART2_CTS_N,   UARTB,       PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(UART2_RTS_N,   UARTB,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* IRDA pinmux */
+       DEFAULT_PINMUX(UART2_RXD,     IRDA,        PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(UART2_TXD,     IRDA,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* UARTC pinmux */
+       DEFAULT_PINMUX(UART3_CTS_N,   UARTC,       PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(UART3_RTS_N,   UARTC,       NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(UART3_RXD,     UARTC,       PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(UART3_TXD,     UARTC,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* CEC pinmux */
+       CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+       /* I2C4 pinmux */
+       DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+       DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+
+       /* USB pinmux */
+       DEFAULT_PINMUX(USB_VBUS_EN0,  USB,         NORMAL,    NORMAL,   OUTPUT),
+
+       /* GPIO pinmux */
+       GPIO_PINMUX(GPIO_X4_AUD, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GPIO_X5_AUD, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GPIO_X6_AUD, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GPIO_X7_AUD, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GPIO_W2_AUD, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GPIO_W3_AUD, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GPIO_X1_AUD, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GPIO_X3_AUD, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(DAP3_DIN, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(DAP3_DOUT, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(DAP3_FS, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(DAP3_SCLK, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GPIO_PV0, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GPIO_PV1, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(ULPI_DATA2, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(ULPI_DATA3, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(ULPI_DATA4, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GPIO_PBB3, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GPIO_PBB4, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GPIO_PBB5, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GPIO_PBB6, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GPIO_PBB7, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GPIO_PCC1, PULL_DOWN, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GPIO_PCC2, PULL_DOWN, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GMI_AD0, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GMI_AD1, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GMI_AD10, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GMI_AD11, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GMI_AD12, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GMI_AD13, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GMI_AD14, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GMI_AD2, NORMAL, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GMI_AD3, NORMAL, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GMI_AD8, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GMI_ADV_N, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GMI_CLK, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GMI_CS0_N, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GMI_CS2_N, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GMI_CS3_N, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GMI_CS4_N, NORMAL, TRISTATE, INPUT, DISABLE),
+       GPIO_PINMUX(GMI_CS7_N, NORMAL, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GMI_OE_N, NORMAL, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GMI_DQS_P, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GMI_IORDY, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GMI_RST_N, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GMI_WAIT, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GMI_WP_N, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(CLK2_REQ, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(SDMMC1_WP_N, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(KB_COL0, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(KB_COL1, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(KB_COL2, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(KB_COL3, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(KB_COL5, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(KB_COL6, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(KB_COL7, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(KB_ROW0, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(KB_ROW1, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(KB_ROW2, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(KB_ROW3, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(KB_ROW4, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(KB_ROW5, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(KB_ROW7, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(CLK3_REQ, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GPIO_PU0, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GPIO_PU1, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GPIO_PU2, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GPIO_PU3, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GPIO_PU4, NORMAL, NORMAL, OUTPUT, DISABLE),
+       GPIO_PINMUX(GPIO_PU5, PULL_UP, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(GPIO_PU6, NORMAL, NORMAL, INPUT, DISABLE),
+       GPIO_PINMUX(HDMI_INT, PULL_DOWN, NORMAL, INPUT, DEFAULT),
+       GPIO_PINMUX(SPDIF_IN, PULL_UP, NORMAL, OUTPUT, DISABLE),
+};
+
+static __initdata struct tegra_pingroup_config unused_pins_lowpower[] = {
+       UNUSED_PINMUX(CLK1_REQ),
+       UNUSED_PINMUX(ULPI_DATA0),
+       UNUSED_PINMUX(ULPI_DATA1),
+       UNUSED_PINMUX(ULPI_DATA5),
+       UNUSED_PINMUX(ULPI_DATA6),
+       UNUSED_PINMUX(ULPI_DATA7),
+       UNUSED_PINMUX(GMI_AD15),
+       UNUSED_PINMUX(GMI_AD4),
+       UNUSED_PINMUX(GMI_CS6_N),
+       UNUSED_PINMUX(OWR),
+       UNUSED_PINMUX(SPDIF_OUT),
+       UNUSED_PINMUX(USB_VBUS_EN1),
+};
+
+static struct gpio_init_pin_info init_gpio_mode_tegranote7c_common[] = {
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX4, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX5, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX6, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX7, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PW2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PW3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX1, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP1, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP2, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP0, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PP3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV0, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV1, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PO3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PO4, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PO5, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB4, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB5, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB6, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PBB7, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC1, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG0, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG1, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH2, false, 1),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH4, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH5, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH6, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PG3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PH0, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK0, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK1, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PJ0, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK4, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI6, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PJ3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI1, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI5, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI4, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PI7, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PC7, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC5, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ0, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ1, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ5, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ6, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PQ7, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR0, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR1, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR3, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR4, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR5, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PR7, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PEE1, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU0, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU1, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU2, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU3, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU4, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU5, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PU6, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PN7, true, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK6, false, 0),
+};
+
+/*
+ * This pinmux for FFD of tegranote7c which is auto generated
+ * from T114_CUSTOMER_PINMUX.XLSM
+ */
+static __initdata struct tegra_pingroup_config tegranote7c_ffd_pinmux_common[] = {
+
+       /* EXTPERIPH1 pinmux */
+       DEFAULT_PINMUX(CLK1_OUT,      EXTPERIPH1,  NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2S1 pinmux */
+       DEFAULT_PINMUX(DAP2_DIN,      I2S1,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP2_DOUT,     I2S1,        NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(DAP2_FS,       I2S1,        NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(DAP2_SCLK,     I2S1,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* CLDVFS pinmux */
+       DEFAULT_PINMUX(DVFS_PWM,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(DVFS_CLK,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+
+       /* SPI1 pinmux */
+       DEFAULT_PINMUX(ULPI_CLK,      SPI1,        NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DIR,      SPI1,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_NXT,      SPI1,        NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_STP,      SPI1,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2C3 pinmux */
+       I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+       I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+       /* VI_ALT3 pinmux */
+       VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+       VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+
+       /* I2C2 pinmux */
+       I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+       I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+       /* UARTD pinmux */
+       DEFAULT_PINMUX(GMI_A16,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(GMI_A17,       UARTD,       PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_A18,       UARTD,       NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_A19,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* PWM1 pinmux */
+       DEFAULT_PINMUX(GMI_AD9,       PWM1,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* SOC pinmux */
+       DEFAULT_PINMUX(GMI_CS1_N,     SOC,         PULL_UP,   TRISTATE, INPUT),
+       DEFAULT_PINMUX(CLK_32K_OUT,   SOC,         PULL_UP,   TRISTATE, INPUT),
+
+       /* EXTPERIPH2 pinmux */
+       DEFAULT_PINMUX(CLK2_OUT,      EXTPERIPH2,  NORMAL,    NORMAL,   OUTPUT),
+
+       /* SDMMC1 pinmux */
+       DEFAULT_PINMUX(SDMMC1_CLK,    SDMMC1,      NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_CMD,    SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT0,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT1,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT2,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT3,   SDMMC1,      PULL_UP,   NORMAL,   INPUT),
+
+       /* SDMMC3 pinmux */
+       DEFAULT_PINMUX(SDMMC3_CLK,    SDMMC3,      NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(SDMMC3_CMD,    SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT0,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT1,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT2,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT3,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CD_N,   SDMMC3,      PULL_UP,   NORMAL,   INPUT),
+
+       /* SDMMC4 pinmux */
+       DEFAULT_PINMUX(SDMMC4_CLK,    SDMMC4,      NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_CMD,    SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT0,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT1,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT2,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT3,   SDMMC4,      PULL_UP,   NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT4,&nb