ath9k_hw: Initialize mode registers from initvals.h for AR9340
Vasanthakumar Thiagarajan [Tue, 19 Apr 2011 13:59:04 +0000 (18:59 +0530)]
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

drivers/net/wireless/ath/ath9k/ar9003_hw.c
drivers/net/wireless/ath/ath9k/ar9003_phy.c
drivers/net/wireless/ath/ath9k/hw.h

index aebaad9..37af721 100644 (file)
@@ -18,6 +18,7 @@
 #include "ar9003_mac.h"
 #include "ar9003_2p2_initvals.h"
 #include "ar9485_initvals.h"
+#include "ar9340_initvals.h"
 
 /* General hardware code for the AR9003 hadware family */
 
  */
 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
 {
-       if (AR_SREV_9485_11(ah)) {
+       if (AR_SREV_9340(ah)) {
+               /* mac */
+               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+                               ar9340_1p0_mac_core,
+                               ARRAY_SIZE(ar9340_1p0_mac_core), 2);
+               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+                               ar9340_1p0_mac_postamble,
+                               ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
+
+               /* bb */
+               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+                               ar9340_1p0_baseband_core,
+                               ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
+               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+                               ar9340_1p0_baseband_postamble,
+                               ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
+
+               /* radio */
+               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+                               ar9340_1p0_radio_core,
+                               ARRAY_SIZE(ar9340_1p0_radio_core), 2);
+               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+                               ar9340_1p0_radio_postamble,
+                               ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
+
+               /* soc */
+               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+                               ar9340_1p0_soc_preamble,
+                               ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
+               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+                               ar9340_1p0_soc_postamble,
+                               ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
+
+               /* rx/tx gain */
+               INIT_INI_ARRAY(&ah->iniModesRxGain,
+                               ar9340Common_wo_xlna_rx_gain_table_1p0,
+                               ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
+                               5);
+               INIT_INI_ARRAY(&ah->iniModesTxGain,
+                               ar9340Modes_high_ob_db_tx_gain_table_1p0,
+                               ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
+                               5);
+
+               INIT_INI_ARRAY(&ah->iniModesAdditional,
+                               ar9340Modes_fast_clock_1p0,
+                               ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
+                               3);
+
+               INIT_INI_ARRAY(&ah->iniModesAdditional_40M,
+                               ar9340_1p0_radio_core_40M,
+                               ARRAY_SIZE(ar9340_1p0_radio_core_40M),
+                               2);
+       } else if (AR_SREV_9485_11(ah)) {
                /* mac */
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
index 1bc33f5..c4d0805 100644 (file)
@@ -646,6 +646,9 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
                REG_WRITE_ARRAY(&ah->iniModesAdditional,
                                modesIndex, regWrites);
 
+       if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
+               REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
+
        ar9003_hw_override_ini(ah);
        ar9003_hw_set_channel_regs(ah, chan);
        ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
index 9b1f415..29a745c 100644 (file)
@@ -800,6 +800,7 @@ struct ath_hw {
        struct ar5416IniArray iniPcieSerdes;
        struct ar5416IniArray iniPcieSerdesLowPower;
        struct ar5416IniArray iniModesAdditional;
+       struct ar5416IniArray iniModesAdditional_40M;
        struct ar5416IniArray iniModesRxGain;
        struct ar5416IniArray iniModesTxGain;
        struct ar5416IniArray iniModes_9271_1_0_only;