Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
John W. Linville [Mon, 11 Jul 2011 18:46:59 +0000 (14:46 -0400)]
Conflicts:
drivers/net/wireless/ath/ath5k/sysfs.c
net/bluetooth/l2cap_core.c
net/mac80211/wpa.c

406 files changed:
Documentation/networking/nfc.txt [new file with mode: 0644]
drivers/Kconfig
drivers/Makefile
drivers/bcma/Kconfig
drivers/bcma/Makefile
drivers/bcma/bcma_private.h
drivers/bcma/core.c
drivers/bcma/driver_chipcommon_pmu.c
drivers/bcma/driver_pci.c
drivers/bcma/driver_pci_host.c [new file with mode: 0644]
drivers/bcma/host_pci.c
drivers/bcma/main.c
drivers/bcma/sprom.c [new file with mode: 0644]
drivers/net/b44.c
drivers/net/wireless/ath/ath.h
drivers/net/wireless/ath/ath5k/ahb.c
drivers/net/wireless/ath/ath5k/ani.c
drivers/net/wireless/ath/ath5k/ath5k.h
drivers/net/wireless/ath/ath5k/attach.c
drivers/net/wireless/ath/ath5k/base.c
drivers/net/wireless/ath/ath5k/base.h
drivers/net/wireless/ath/ath5k/debug.c
drivers/net/wireless/ath/ath5k/dma.c
drivers/net/wireless/ath/ath5k/eeprom.c
drivers/net/wireless/ath/ath5k/eeprom.h
drivers/net/wireless/ath/ath5k/initvals.c
drivers/net/wireless/ath/ath5k/led.c
drivers/net/wireless/ath/ath5k/mac80211-ops.c
drivers/net/wireless/ath/ath5k/pci.c
drivers/net/wireless/ath/ath5k/pcu.c
drivers/net/wireless/ath/ath5k/phy.c
drivers/net/wireless/ath/ath5k/reg.h
drivers/net/wireless/ath/ath5k/reset.c
drivers/net/wireless/ath/ath5k/rfbuffer.h
drivers/net/wireless/ath/ath5k/rfgain.h
drivers/net/wireless/ath/ath5k/sysfs.c
drivers/net/wireless/ath/ath5k/trace.h
drivers/net/wireless/ath/ath9k/ahb.c
drivers/net/wireless/ath/ath9k/ar9002_mac.c
drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
drivers/net/wireless/ath/ath9k/ar9003_hw.c
drivers/net/wireless/ath/ath9k/ar9003_mac.c
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
drivers/net/wireless/ath/ath9k/ar9003_phy.c
drivers/net/wireless/ath/ath9k/ar9003_phy.h
drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h [new file with mode: 0644]
drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h [new file with mode: 0644]
drivers/net/wireless/ath/ath9k/ath9k.h
drivers/net/wireless/ath/ath9k/beacon.c
drivers/net/wireless/ath/ath9k/debug.c
drivers/net/wireless/ath/ath9k/debug.h
drivers/net/wireless/ath/ath9k/hif_usb.c
drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
drivers/net/wireless/ath/ath9k/htc_drv_init.c
drivers/net/wireless/ath/ath9k/htc_drv_main.c
drivers/net/wireless/ath/ath9k/hw-ops.h
drivers/net/wireless/ath/ath9k/hw.c
drivers/net/wireless/ath/ath9k/hw.h
drivers/net/wireless/ath/ath9k/init.c
drivers/net/wireless/ath/ath9k/main.c
drivers/net/wireless/ath/ath9k/rc.c
drivers/net/wireless/ath/ath9k/recv.c
drivers/net/wireless/ath/ath9k/reg.h
drivers/net/wireless/ath/ath9k/xmit.c
drivers/net/wireless/ath/carl9170/carl9170.h
drivers/net/wireless/ath/carl9170/fw.c
drivers/net/wireless/ath/carl9170/fwcmd.h
drivers/net/wireless/ath/carl9170/fwdesc.h
drivers/net/wireless/ath/carl9170/hw.h
drivers/net/wireless/ath/carl9170/main.c
drivers/net/wireless/ath/carl9170/phy.c
drivers/net/wireless/ath/carl9170/rx.c
drivers/net/wireless/ath/carl9170/version.h
drivers/net/wireless/ath/carl9170/wlan.h
drivers/net/wireless/b43/Kconfig
drivers/net/wireless/b43/Makefile
drivers/net/wireless/b43/b43.h
drivers/net/wireless/b43/bus.c [new file with mode: 0644]
drivers/net/wireless/b43/bus.h [new file with mode: 0644]
drivers/net/wireless/b43/dma.c
drivers/net/wireless/b43/leds.c
drivers/net/wireless/b43/lo.c
drivers/net/wireless/b43/main.c
drivers/net/wireless/b43/main.h
drivers/net/wireless/b43/phy_a.c
drivers/net/wireless/b43/phy_common.c
drivers/net/wireless/b43/phy_common.h
drivers/net/wireless/b43/phy_g.c
drivers/net/wireless/b43/phy_ht.c [new file with mode: 0644]
drivers/net/wireless/b43/phy_ht.h [new file with mode: 0644]
drivers/net/wireless/b43/phy_lcn.c [new file with mode: 0644]
drivers/net/wireless/b43/phy_lcn.h [new file with mode: 0644]
drivers/net/wireless/b43/phy_lp.c
drivers/net/wireless/b43/phy_n.c
drivers/net/wireless/b43/pio.c
drivers/net/wireless/b43/radio_2055.h
drivers/net/wireless/b43/radio_2056.h
drivers/net/wireless/b43/radio_2059.c [new file with mode: 0644]
drivers/net/wireless/b43/radio_2059.h [new file with mode: 0644]
drivers/net/wireless/b43/rfkill.c
drivers/net/wireless/b43/sdio.c
drivers/net/wireless/b43/sysfs.c
drivers/net/wireless/b43/tables_lpphy.c
drivers/net/wireless/b43/tables_nphy.h
drivers/net/wireless/b43/tables_phy_ht.c [new file with mode: 0644]
drivers/net/wireless/b43/tables_phy_ht.h [new file with mode: 0644]
drivers/net/wireless/b43/tables_phy_lcn.c [new file with mode: 0644]
drivers/net/wireless/b43/tables_phy_lcn.h [new file with mode: 0644]
drivers/net/wireless/b43/wa.c
drivers/net/wireless/b43/xmit.c
drivers/net/wireless/b43legacy/dma.c
drivers/net/wireless/b43legacy/main.c
drivers/net/wireless/b43legacy/xmit.c
drivers/net/wireless/ipw2x00/ipw2100.c
drivers/net/wireless/iwlegacy/iwl-3945.c
drivers/net/wireless/iwlegacy/iwl-4965-lib.c
drivers/net/wireless/iwlegacy/iwl-4965-rs.c
drivers/net/wireless/iwlegacy/iwl-4965-rx.c
drivers/net/wireless/iwlegacy/iwl-4965-tx.c
drivers/net/wireless/iwlegacy/iwl-4965.c
drivers/net/wireless/iwlegacy/iwl-commands.h
drivers/net/wireless/iwlegacy/iwl-core.c
drivers/net/wireless/iwlegacy/iwl-core.h
drivers/net/wireless/iwlegacy/iwl-debugfs.c
drivers/net/wireless/iwlegacy/iwl-dev.h
drivers/net/wireless/iwlegacy/iwl-devtrace.c
drivers/net/wireless/iwlegacy/iwl-devtrace.h
drivers/net/wireless/iwlegacy/iwl-eeprom.c
drivers/net/wireless/iwlegacy/iwl-helpers.h
drivers/net/wireless/iwlegacy/iwl-rx.c
drivers/net/wireless/iwlegacy/iwl-scan.c
drivers/net/wireless/iwlegacy/iwl3945-base.c
drivers/net/wireless/iwlegacy/iwl4965-base.c
drivers/net/wireless/iwlwifi/Makefile
drivers/net/wireless/iwlwifi/iwl-1000.c
drivers/net/wireless/iwlwifi/iwl-2000.c
drivers/net/wireless/iwlwifi/iwl-5000-hw.h
drivers/net/wireless/iwlwifi/iwl-5000.c
drivers/net/wireless/iwlwifi/iwl-6000.c
drivers/net/wireless/iwlwifi/iwl-agn-eeprom.c
drivers/net/wireless/iwlwifi/iwl-agn-hcmd.c
drivers/net/wireless/iwlwifi/iwl-agn-hw.h
drivers/net/wireless/iwlwifi/iwl-agn-ict.c
drivers/net/wireless/iwlwifi/iwl-agn-lib.c
drivers/net/wireless/iwlwifi/iwl-agn-rs.c
drivers/net/wireless/iwlwifi/iwl-agn-rxon.c
drivers/net/wireless/iwlwifi/iwl-agn-sta.c
drivers/net/wireless/iwlwifi/iwl-agn-tt.c
drivers/net/wireless/iwlwifi/iwl-agn-tx.c
drivers/net/wireless/iwlwifi/iwl-agn-ucode.c
drivers/net/wireless/iwlwifi/iwl-agn.c
drivers/net/wireless/iwlwifi/iwl-agn.h
drivers/net/wireless/iwlwifi/iwl-commands.h
drivers/net/wireless/iwlwifi/iwl-core.c
drivers/net/wireless/iwlwifi/iwl-core.h
drivers/net/wireless/iwlwifi/iwl-debug.h
drivers/net/wireless/iwlwifi/iwl-debugfs.c
drivers/net/wireless/iwlwifi/iwl-dev.h
drivers/net/wireless/iwlwifi/iwl-eeprom.c
drivers/net/wireless/iwlwifi/iwl-eeprom.h
drivers/net/wireless/iwlwifi/iwl-hcmd.c
drivers/net/wireless/iwlwifi/iwl-helpers.h
drivers/net/wireless/iwlwifi/iwl-io.h
drivers/net/wireless/iwlwifi/iwl-led.c
drivers/net/wireless/iwlwifi/iwl-pci.c [new file with mode: 0644]
drivers/net/wireless/iwlwifi/iwl-pci.h [new file with mode: 0644]
drivers/net/wireless/iwlwifi/iwl-power.c
drivers/net/wireless/iwlwifi/iwl-power.h
drivers/net/wireless/iwlwifi/iwl-prph.h
drivers/net/wireless/iwlwifi/iwl-rx.c
drivers/net/wireless/iwlwifi/iwl-scan.c
drivers/net/wireless/iwlwifi/iwl-sv-open.c
drivers/net/wireless/iwlwifi/iwl-testmode.h
drivers/net/wireless/iwlwifi/iwl-trans.c [new file with mode: 0644]
drivers/net/wireless/iwlwifi/iwl-trans.h [new file with mode: 0644]
drivers/net/wireless/iwlwifi/iwl-tx.c
drivers/net/wireless/libertas/if_sdio.c
drivers/net/wireless/libertas/if_spi.c
drivers/net/wireless/libertas_tf/main.c
drivers/net/wireless/mac80211_hwsim.c
drivers/net/wireless/mac80211_hwsim.h [new file with mode: 0644]
drivers/net/wireless/mwifiex/11n.c
drivers/net/wireless/mwifiex/11n.h
drivers/net/wireless/mwifiex/11n_aggr.c
drivers/net/wireless/mwifiex/11n_rxreorder.c
drivers/net/wireless/mwifiex/11n_rxreorder.h
drivers/net/wireless/mwifiex/cfg80211.c
drivers/net/wireless/mwifiex/cmdevt.c
drivers/net/wireless/mwifiex/debugfs.c
drivers/net/wireless/mwifiex/decl.h
drivers/net/wireless/mwifiex/join.c
drivers/net/wireless/mwifiex/main.c
drivers/net/wireless/mwifiex/main.h
drivers/net/wireless/mwifiex/scan.c
drivers/net/wireless/mwifiex/sdio.c
drivers/net/wireless/mwifiex/sdio.h
drivers/net/wireless/mwifiex/sta_cmd.c
drivers/net/wireless/mwifiex/sta_cmdresp.c
drivers/net/wireless/mwifiex/sta_rx.c
drivers/net/wireless/mwifiex/sta_tx.c
drivers/net/wireless/mwifiex/txrx.c
drivers/net/wireless/mwifiex/wmm.c
drivers/net/wireless/rt2x00/Kconfig
drivers/net/wireless/rt2x00/rt2400pci.c
drivers/net/wireless/rt2x00/rt2500pci.c
drivers/net/wireless/rt2x00/rt2500usb.c
drivers/net/wireless/rt2x00/rt2800.h
drivers/net/wireless/rt2x00/rt2800lib.c
drivers/net/wireless/rt2x00/rt2800lib.h
drivers/net/wireless/rt2x00/rt2800pci.c
drivers/net/wireless/rt2x00/rt2800usb.c
drivers/net/wireless/rt2x00/rt2x00.h
drivers/net/wireless/rt2x00/rt2x00crypto.c
drivers/net/wireless/rt2x00/rt2x00dev.c
drivers/net/wireless/rt2x00/rt2x00lib.h
drivers/net/wireless/rt2x00/rt2x00mac.c
drivers/net/wireless/rt2x00/rt2x00queue.c
drivers/net/wireless/rt2x00/rt2x00queue.h
drivers/net/wireless/rt2x00/rt2x00usb.c
drivers/net/wireless/rt2x00/rt61pci.c
drivers/net/wireless/rt2x00/rt73usb.c
drivers/net/wireless/rtlwifi/Kconfig
drivers/net/wireless/rtlwifi/Makefile
drivers/net/wireless/rtlwifi/base.c
drivers/net/wireless/rtlwifi/core.c
drivers/net/wireless/rtlwifi/core.h
drivers/net/wireless/rtlwifi/efuse.c
drivers/net/wireless/rtlwifi/pci.c
drivers/net/wireless/rtlwifi/pci.h
drivers/net/wireless/rtlwifi/ps.c
drivers/net/wireless/rtlwifi/ps.h
drivers/net/wireless/rtlwifi/rc.c
drivers/net/wireless/rtlwifi/regd.c
drivers/net/wireless/rtlwifi/rtl8192c/dm_common.c
drivers/net/wireless/rtlwifi/rtl8192c/fw_common.c
drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
drivers/net/wireless/rtlwifi/rtl8192ce/led.c
drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
drivers/net/wireless/rtlwifi/rtl8192ce/rf.c
drivers/net/wireless/rtlwifi/rtl8192ce/trx.c
drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
drivers/net/wireless/rtlwifi/rtl8192cu/led.c
drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
drivers/net/wireless/rtlwifi/rtl8192cu/phy.c
drivers/net/wireless/rtlwifi/rtl8192cu/rf.c
drivers/net/wireless/rtlwifi/rtl8192cu/trx.c
drivers/net/wireless/rtlwifi/rtl8192de/Makefile [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/def.h [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/dm.c [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/dm.h [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/fw.c [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/fw.h [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/hw.c [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/hw.h [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/led.c [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/led.h [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/phy.c [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/phy.h [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/reg.h [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/rf.c [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/rf.h [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/sw.c [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/sw.h [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/table.c [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/table.h [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/trx.c [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192de/trx.h [new file with mode: 0644]
drivers/net/wireless/rtlwifi/rtl8192se/dm.c
drivers/net/wireless/rtlwifi/rtl8192se/fw.c
drivers/net/wireless/rtlwifi/rtl8192se/hw.c
drivers/net/wireless/rtlwifi/rtl8192se/led.c
drivers/net/wireless/rtlwifi/rtl8192se/phy.c
drivers/net/wireless/rtlwifi/rtl8192se/reg.h
drivers/net/wireless/rtlwifi/rtl8192se/rf.c
drivers/net/wireless/rtlwifi/rtl8192se/trx.c
drivers/net/wireless/rtlwifi/wifi.h
drivers/net/wireless/wl12xx/Kconfig
drivers/net/wireless/wl12xx/acx.c
drivers/net/wireless/wl12xx/acx.h
drivers/net/wireless/wl12xx/boot.c
drivers/net/wireless/wl12xx/cmd.c
drivers/net/wireless/wl12xx/cmd.h
drivers/net/wireless/wl12xx/conf.h
drivers/net/wireless/wl12xx/debugfs.c
drivers/net/wireless/wl12xx/event.c
drivers/net/wireless/wl12xx/event.h
drivers/net/wireless/wl12xx/ini.h
drivers/net/wireless/wl12xx/init.c
drivers/net/wireless/wl12xx/io.c
drivers/net/wireless/wl12xx/io.h
drivers/net/wireless/wl12xx/main.c
drivers/net/wireless/wl12xx/ps.c
drivers/net/wireless/wl12xx/rx.c
drivers/net/wireless/wl12xx/rx.h
drivers/net/wireless/wl12xx/scan.c
drivers/net/wireless/wl12xx/scan.h
drivers/net/wireless/wl12xx/sdio.c
drivers/net/wireless/wl12xx/spi.c
drivers/net/wireless/wl12xx/testmode.c
drivers/net/wireless/wl12xx/tx.c
drivers/net/wireless/wl12xx/tx.h
drivers/net/wireless/wl12xx/wl12xx.h
drivers/net/wireless/zd1211rw/zd_chip.h
drivers/net/wireless/zd1211rw/zd_def.h
drivers/net/wireless/zd1211rw/zd_mac.c
drivers/net/wireless/zd1211rw/zd_mac.h
drivers/net/wireless/zd1211rw/zd_usb.c
drivers/net/wireless/zd1211rw/zd_usb.h
drivers/nfc/Kconfig
drivers/nfc/Makefile
drivers/nfc/pn533.c [new file with mode: 0644]
drivers/ssb/driver_chipcommon_pmu.c
drivers/ssb/driver_gige.c
drivers/ssb/driver_pcicore.c
drivers/ssb/main.c
drivers/ssb/pci.c
drivers/ssb/pcihost_wrapper.c
drivers/ssb/scan.c
include/linux/ath9k_platform.h
include/linux/bcma/bcma.h
include/linux/bcma/bcma_driver_chipcommon.h
include/linux/bcma/bcma_driver_pci.h
include/linux/cordic.h [new file with mode: 0644]
include/linux/crc8.h [new file with mode: 0644]
include/linux/ieee80211.h
include/linux/netlink.h
include/linux/nfc.h [new file with mode: 0644]
include/linux/nl80211.h
include/linux/socket.h
include/linux/ssb/ssb.h
include/net/bluetooth/bluetooth.h
include/net/bluetooth/hci.h
include/net/bluetooth/hci_core.h
include/net/bluetooth/l2cap.h
include/net/bluetooth/mgmt.h
include/net/bluetooth/rfcomm.h
include/net/bluetooth/smp.h
include/net/cfg80211.h
include/net/genetlink.h
include/net/mac80211.h
include/net/netlink.h
include/net/nfc.h [new file with mode: 0644]
lib/Kconfig
lib/Makefile
lib/cordic.c [new file with mode: 0644]
lib/crc8.c [new file with mode: 0644]
net/Kconfig
net/Makefile
net/bluetooth/Kconfig
net/bluetooth/Makefile
net/bluetooth/cmtp/capi.c
net/bluetooth/hci_conn.c
net/bluetooth/hci_core.c
net/bluetooth/hci_event.c
net/bluetooth/hci_sock.c
net/bluetooth/l2cap_core.c
net/bluetooth/l2cap_sock.c
net/bluetooth/mgmt.c
net/bluetooth/rfcomm/sock.c
net/bluetooth/smp.c [new file with mode: 0644]
net/core/sock.c
net/mac80211/aes_ccm.c
net/mac80211/aes_ccm.h
net/mac80211/aes_cmac.c
net/mac80211/aes_cmac.h
net/mac80211/agg-rx.c
net/mac80211/cfg.c
net/mac80211/debugfs_key.c
net/mac80211/driver-ops.h
net/mac80211/driver-trace.h
net/mac80211/ht.c
net/mac80211/ieee80211_i.h
net/mac80211/key.c
net/mac80211/key.h
net/mac80211/mesh_pathtbl.c
net/mac80211/mlme.c
net/mac80211/pm.c
net/mac80211/rc80211_minstrel.c
net/mac80211/rc80211_minstrel.h
net/mac80211/rc80211_minstrel_ht.c
net/mac80211/rx.c
net/mac80211/scan.c
net/mac80211/sta_info.h
net/mac80211/tkip.c
net/mac80211/tkip.h
net/mac80211/tx.c
net/mac80211/util.c
net/mac80211/wme.c
net/mac80211/wme.h
net/mac80211/work.c
net/mac80211/wpa.c
net/netlink/af_netlink.c
net/nfc/Kconfig [new file with mode: 0644]
net/nfc/Makefile [new file with mode: 0644]
net/nfc/af_nfc.c [new file with mode: 0644]
net/nfc/core.c [new file with mode: 0644]
net/nfc/netlink.c [new file with mode: 0644]
net/nfc/nfc.h [new file with mode: 0644]
net/nfc/rawsock.c [new file with mode: 0644]
net/wireless/mlme.c
net/wireless/nl80211.c
net/wireless/nl80211.h
net/wireless/scan.c

diff --git a/Documentation/networking/nfc.txt b/Documentation/networking/nfc.txt
new file mode 100644 (file)
index 0000000..b24c29b
--- /dev/null
@@ -0,0 +1,128 @@
+Linux NFC subsystem
+===================
+
+The Near Field Communication (NFC) subsystem is required to standardize the
+NFC device drivers development and to create an unified userspace interface.
+
+This document covers the architecture overview, the device driver interface
+description and the userspace interface description.
+
+Architecture overview
+---------------------
+
+The NFC subsystem is responsible for:
+      - NFC adapters management;
+      - Polling for targets;
+      - Low-level data exchange;
+
+The subsystem is divided in some parts. The 'core' is responsible for
+providing the device driver interface. On the other side, it is also
+responsible for providing an interface to control operations and low-level
+data exchange.
+
+The control operations are available to userspace via generic netlink.
+
+The low-level data exchange interface is provided by the new socket family
+PF_NFC. The NFC_SOCKPROTO_RAW performs raw communication with NFC targets.
+
+
+             +--------------------------------------+
+             |              USER SPACE              |
+             +--------------------------------------+
+                 ^                       ^
+                 | low-level             | control
+                 | data exchange         | operations
+                 |                       |
+                 |                       v
+                 |                  +-----------+
+                 | AF_NFC           |  netlink  |
+                 | socket           +-----------+
+                 | raw                   ^
+                 |                       |
+                 v                       v
+             +---------+            +-----------+
+             | rawsock | <--------> |   core    |
+             +---------+            +-----------+
+                                         ^
+                                         |
+                                         v
+                                    +-----------+
+                                    |  driver   |
+                                    +-----------+
+
+Device Driver Interface
+-----------------------
+
+When registering on the NFC subsystem, the device driver must inform the core
+of the set of supported NFC protocols and the set of ops callbacks. The ops
+callbacks that must be implemented are the following:
+
+* start_poll - setup the device to poll for targets
+* stop_poll - stop on progress polling operation
+* activate_target - select and initialize one of the targets found
+* deactivate_target - deselect and deinitialize the selected target
+* data_exchange - send data and receive the response (transceive operation)
+
+Userspace interface
+--------------------
+
+The userspace interface is divided in control operations and low-level data
+exchange operation.
+
+CONTROL OPERATIONS:
+
+Generic netlink is used to implement the interface to the control operations.
+The operations are composed by commands and events, all listed below:
+
+* NFC_CMD_GET_DEVICE - get specific device info or dump the device list
+* NFC_CMD_START_POLL - setup a specific device to polling for targets
+* NFC_CMD_STOP_POLL - stop the polling operation in a specific device
+* NFC_CMD_GET_TARGET - dump the list of targets found by a specific device
+
+* NFC_EVENT_DEVICE_ADDED - reports an NFC device addition
+* NFC_EVENT_DEVICE_REMOVED - reports an NFC device removal
+* NFC_EVENT_TARGETS_FOUND - reports START_POLL results when 1 or more targets
+are found
+
+The user must call START_POLL to poll for NFC targets, passing the desired NFC
+protocols through NFC_ATTR_PROTOCOLS attribute. The device remains in polling
+state until it finds any target. However, the user can stop the polling
+operation by calling STOP_POLL command. In this case, it will be checked if
+the requester of STOP_POLL is the same of START_POLL.
+
+If the polling operation finds one or more targets, the event TARGETS_FOUND is
+sent (including the device id). The user must call GET_TARGET to get the list of
+all targets found by such device. Each reply message has target attributes with
+relevant information such as the supported NFC protocols.
+
+All polling operations requested through one netlink socket are stopped when
+it's closed.
+
+LOW-LEVEL DATA EXCHANGE:
+
+The userspace must use PF_NFC sockets to perform any data communication with
+targets. All NFC sockets use AF_NFC:
+
+struct sockaddr_nfc {
+       sa_family_t sa_family;
+       __u32 dev_idx;
+       __u32 target_idx;
+       __u32 nfc_protocol;
+};
+
+To establish a connection with one target, the user must create an
+NFC_SOCKPROTO_RAW socket and call the 'connect' syscall with the sockaddr_nfc
+struct correctly filled. All information comes from NFC_EVENT_TARGETS_FOUND
+netlink event. As a target can support more than one NFC protocol, the user
+must inform which protocol it wants to use.
+
+Internally, 'connect' will result in an activate_target call to the driver.
+When the socket is closed, the target is deactivated.
+
+The data format exchanged through the sockets is NFC protocol dependent. For
+instance, when communicating with MIFARE tags, the data exchanged are MIFARE
+commands and their responses.
+
+The first received package is the response to the first sent package and so
+on. In order to allow valid "empty" responses, every data received has a NULL
+header of 1 byte.
index 61631ed..a56b0b8 100644 (file)
@@ -92,8 +92,6 @@ source "drivers/memstick/Kconfig"
 
 source "drivers/leds/Kconfig"
 
-source "drivers/nfc/Kconfig"
-
 source "drivers/accessibility/Kconfig"
 
 source "drivers/infiniband/Kconfig"
index a29527f..843cd31 100644 (file)
@@ -120,3 +120,4 @@ obj-y                               += ieee802154/
 obj-y                          += clk/
 
 obj-$(CONFIG_HWSPINLOCK)       += hwspinlock/
+obj-$(CONFIG_NFC)              += nfc/
index 353781b..ae0a02e 100644 (file)
@@ -13,6 +13,11 @@ config BCMA
          Bus driver for Broadcom specific Advanced Microcontroller Bus
          Architecture.
 
+# Support for Block-I/O. SELECT this from the driver that needs it.
+config BCMA_BLOCKIO
+       bool
+       depends on BCMA
+
 config BCMA_HOST_PCI_POSSIBLE
        bool
        depends on BCMA && PCI = y
@@ -22,6 +27,12 @@ config BCMA_HOST_PCI
        bool "Support for BCMA on PCI-host bus"
        depends on BCMA_HOST_PCI_POSSIBLE
 
+config BCMA_DRIVER_PCI_HOSTMODE
+       bool "Driver for PCI core working in hostmode"
+       depends on BCMA && MIPS
+       help
+         PCI core hostmode operation (external PCI bus).
+
 config BCMA_DEBUG
        bool "BCMA debugging"
        depends on BCMA
index 0d56245..a2161cc 100644 (file)
@@ -1,6 +1,7 @@
-bcma-y                                 += main.o scan.o core.o
+bcma-y                                 += main.o scan.o core.o sprom.o
 bcma-y                                 += driver_chipcommon.o driver_chipcommon_pmu.o
 bcma-y                                 += driver_pci.o
+bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE)        += driver_pci_host.o
 bcma-$(CONFIG_BCMA_HOST_PCI)           += host_pci.o
 obj-$(CONFIG_BCMA)                     += bcma.o
 
index 2f72e9c..e02ff21 100644 (file)
 struct bcma_bus;
 
 /* main.c */
-extern int bcma_bus_register(struct bcma_bus *bus);
-extern void bcma_bus_unregister(struct bcma_bus *bus);
+int bcma_bus_register(struct bcma_bus *bus);
+void bcma_bus_unregister(struct bcma_bus *bus);
 
 /* scan.c */
 int bcma_bus_scan(struct bcma_bus *bus);
 
+/* sprom.c */
+int bcma_sprom_get(struct bcma_bus *bus);
+
 #ifdef CONFIG_BCMA_HOST_PCI
 /* host_pci.c */
 extern int __init bcma_host_pci_init(void);
 extern void __exit bcma_host_pci_exit(void);
 #endif /* CONFIG_BCMA_HOST_PCI */
 
+#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
+void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
+#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
+
 #endif
index ced379f..1ec7d45 100644 (file)
@@ -19,7 +19,7 @@ bool bcma_core_is_enabled(struct bcma_device *core)
 }
 EXPORT_SYMBOL_GPL(bcma_core_is_enabled);
 
-static void bcma_core_disable(struct bcma_device *core, u32 flags)
+void bcma_core_disable(struct bcma_device *core, u32 flags)
 {
        if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
                return;
@@ -31,6 +31,7 @@ static void bcma_core_disable(struct bcma_device *core, u32 flags)
        bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
        udelay(1);
 }
+EXPORT_SYMBOL_GPL(bcma_core_disable);
 
 int bcma_core_enable(struct bcma_device *core, u32 flags)
 {
index f44177a..dd5846b 100644 (file)
@@ -53,6 +53,7 @@ static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
                max_msk = 0xFFFF;
                break;
        case 43224:
+       case 43225:
                break;
        default:
                pr_err("PMU resource config unknown for device 0x%04X\n",
@@ -74,6 +75,7 @@ void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
        case 0x4313:
        case 0x4331:
        case 43224:
+       case 43225:
                break;
        default:
                pr_err("PMU switch/regulators init unknown for device "
@@ -96,11 +98,13 @@ void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
                if (bus->chipinfo.rev == 0) {
                        pr_err("Workarounds for 43224 rev 0 not fully "
                                "implemented\n");
-                       bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
+                       bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
                } else {
                        bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
                }
                break;
+       case 43225:
+               break;
        default:
                pr_err("Workarounds unknown for device 0x%04X\n",
                        bus->chipinfo.id);
index e757e4e..dc6f34a 100644 (file)
@@ -157,7 +157,67 @@ static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
  * Init.
  **************************************************/
 
-void bcma_core_pci_init(struct bcma_drv_pci *pc)
+static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
 {
        bcma_pcicore_serdes_workaround(pc);
 }
+
+static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
+{
+       struct bcma_bus *bus = pc->core->bus;
+       u16 chipid_top;
+
+       chipid_top = (bus->chipinfo.id & 0xFF00);
+       if (chipid_top != 0x4700 &&
+           chipid_top != 0x5300)
+               return false;
+
+       if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
+               return false;
+
+#if 0
+       /* TODO: on BCMA we use address from EROM instead of magic formula */
+       u32 tmp;
+       return !mips_busprobe32(tmp, (bus->mmio +
+               (pc->core->core_index * BCMA_CORE_SIZE)));
+#endif
+
+       return true;
+}
+
+void bcma_core_pci_init(struct bcma_drv_pci *pc)
+{
+       if (bcma_core_pci_is_in_hostmode(pc)) {
+#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
+               bcma_core_pci_hostmode_init(pc);
+#else
+               pr_err("Driver compiled without support for hostmode PCI\n");
+#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
+       } else {
+               bcma_core_pci_clientmode_init(pc);
+       }
+}
+
+int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
+                         bool enable)
+{
+       struct pci_dev *pdev = pc->core->bus->host_pci;
+       u32 coremask, tmp;
+       int err;
+
+       err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
+       if (err)
+               goto out;
+
+       coremask = BIT(core->core_index) << 8;
+       if (enable)
+               tmp |= coremask;
+       else
+               tmp &= ~coremask;
+
+       err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);
+
+out:
+       return err;
+}
+EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
diff --git a/drivers/bcma/driver_pci_host.c b/drivers/bcma/driver_pci_host.c
new file mode 100644 (file)
index 0000000..eb332b7
--- /dev/null
@@ -0,0 +1,14 @@
+/*
+ * Broadcom specific AMBA
+ * PCI Core in hostmode
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include "bcma_private.h"
+#include <linux/bcma/bcma.h>
+
+void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
+{
+       pr_err("No support for PCI core in hostmode yet\n");
+}
index ffd8797..c4b313a 100644 (file)
@@ -64,6 +64,54 @@ static void bcma_host_pci_write32(struct bcma_device *core, u16 offset,
        iowrite32(value, core->bus->mmio + offset);
 }
 
+#ifdef CONFIG_BCMA_BLOCKIO
+void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
+                             size_t count, u16 offset, u8 reg_width)
+{
+       void __iomem *addr = core->bus->mmio + offset;
+       if (core->bus->mapped_core != core)
+               bcma_host_pci_switch_core(core);
+       switch (reg_width) {
+       case sizeof(u8):
+               ioread8_rep(addr, buffer, count);
+               break;
+       case sizeof(u16):
+               WARN_ON(count & 1);
+               ioread16_rep(addr, buffer, count >> 1);
+               break;
+       case sizeof(u32):
+               WARN_ON(count & 3);
+               ioread32_rep(addr, buffer, count >> 2);
+               break;
+       default:
+               WARN_ON(1);
+       }
+}
+
+void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
+                              size_t count, u16 offset, u8 reg_width)
+{
+       void __iomem *addr = core->bus->mmio + offset;
+       if (core->bus->mapped_core != core)
+               bcma_host_pci_switch_core(core);
+       switch (reg_width) {
+       case sizeof(u8):
+               iowrite8_rep(addr, buffer, count);
+               break;
+       case sizeof(u16):
+               WARN_ON(count & 1);
+               iowrite16_rep(addr, buffer, count >> 1);
+               break;
+       case sizeof(u32):
+               WARN_ON(count & 3);
+               iowrite32_rep(addr, buffer, count >> 2);
+               break;
+       default:
+               WARN_ON(1);
+       }
+}
+#endif
+
 static u32 bcma_host_pci_aread32(struct bcma_device *core, u16 offset)
 {
        if (core->bus->mapped_core != core)
@@ -86,6 +134,10 @@ const struct bcma_host_ops bcma_host_pci_ops = {
        .write8         = bcma_host_pci_write8,
        .write16        = bcma_host_pci_write16,
        .write32        = bcma_host_pci_write32,
+#ifdef CONFIG_BCMA_BLOCKIO
+       .block_read     = bcma_host_pci_block_read,
+       .block_write    = bcma_host_pci_block_write,
+#endif
        .aread32        = bcma_host_pci_aread32,
        .awrite32       = bcma_host_pci_awrite32,
 };
@@ -174,6 +226,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
        { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
        { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
        { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
+       { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
        { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
        { 0, },
 };
index be52344..08a14a3 100644 (file)
@@ -7,6 +7,7 @@
 
 #include "bcma_private.h"
 #include <linux/bcma/bcma.h>
+#include <linux/slab.h>
 
 MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
 MODULE_LICENSE("GPL");
@@ -89,6 +90,8 @@ static int bcma_register_cores(struct bcma_bus *bus)
                switch (bus->hosttype) {
                case BCMA_HOSTTYPE_PCI:
                        core->dev.parent = &bus->host_pci->dev;
+                       core->dma_dev = &bus->host_pci->dev;
+                       core->irq = bus->host_pci->irq;
                        break;
                case BCMA_HOSTTYPE_NONE:
                case BCMA_HOSTTYPE_SDIO:
@@ -144,6 +147,13 @@ int bcma_bus_register(struct bcma_bus *bus)
                bcma_core_pci_init(&bus->drv_pci);
        }
 
+       /* Try to get SPROM */
+       err = bcma_sprom_get(bus);
+       if (err) {
+               pr_err("Failed to get SPROM: %d\n", err);
+               return -ENOENT;
+       }
+
        /* Register found cores */
        bcma_register_cores(bus);
 
@@ -151,13 +161,11 @@ int bcma_bus_register(struct bcma_bus *bus)
 
        return 0;
 }
-EXPORT_SYMBOL_GPL(bcma_bus_register);
 
 void bcma_bus_unregister(struct bcma_bus *bus)
 {
        bcma_unregister_cores(bus);
 }
-EXPORT_SYMBOL_GPL(bcma_bus_unregister);
 
 int __bcma_driver_register(struct bcma_driver *drv, struct module *owner)
 {
diff --git a/drivers/bcma/sprom.c b/drivers/bcma/sprom.c
new file mode 100644 (file)
index 0000000..ffbb0e3
--- /dev/null
@@ -0,0 +1,162 @@
+/*
+ * Broadcom specific AMBA
+ * SPROM reading
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include "bcma_private.h"
+
+#include <linux/bcma/bcma.h>
+#include <linux/bcma/bcma_regs.h>
+#include <linux/pci.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+
+#define SPOFF(offset)  ((offset) / sizeof(u16))
+
+/**************************************************
+ * R/W ops.
+ **************************************************/
+
+static void bcma_sprom_read(struct bcma_bus *bus, u16 *sprom)
+{
+       int i;
+       for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
+               sprom[i] = bcma_read16(bus->drv_cc.core,
+                                      BCMA_CC_SPROM + (i * 2));
+}
+
+/**************************************************
+ * Validation.
+ **************************************************/
+
+static inline u8 bcma_crc8(u8 crc, u8 data)
+{
+       /* Polynomial:   x^8 + x^7 + x^6 + x^4 + x^2 + 1   */
+       static const u8 t[] = {
+               0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
+               0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
+               0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
+               0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
+               0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
+               0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
+               0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
+               0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
+               0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
+               0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
+               0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
+               0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
+               0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
+               0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
+               0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
+               0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
+               0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
+               0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
+               0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
+               0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
+               0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
+               0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
+               0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
+               0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
+               0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
+               0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
+               0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
+               0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
+               0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
+               0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
+               0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
+               0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
+       };
+       return t[crc ^ data];
+}
+
+static u8 bcma_sprom_crc(const u16 *sprom)
+{
+       int word;
+       u8 crc = 0xFF;
+
+       for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
+               crc = bcma_crc8(crc, sprom[word] & 0x00FF);
+               crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
+       }
+       crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
+       crc ^= 0xFF;
+
+       return crc;
+}
+
+static int bcma_sprom_check_crc(const u16 *sprom)
+{
+       u8 crc;
+       u8 expected_crc;
+       u16 tmp;
+
+       crc = bcma_sprom_crc(sprom);
+       tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
+       expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
+       if (crc != expected_crc)
+               return -EPROTO;
+
+       return 0;
+}
+
+static int bcma_sprom_valid(const u16 *sprom)
+{
+       u16 revision;
+       int err;
+
+       err = bcma_sprom_check_crc(sprom);
+       if (err)
+               return err;
+
+       revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
+       if (revision != 8) {
+               pr_err("Unsupported SPROM revision: %d\n", revision);
+               return -ENOENT;
+       }
+
+       return 0;
+}
+
+/**************************************************
+ * SPROM extraction.
+ **************************************************/
+
+static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
+{
+       u16 v;
+       int i;
+
+       for (i = 0; i < 3; i++) {
+               v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
+               *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
+       }
+}
+
+int bcma_sprom_get(struct bcma_bus *bus)
+{
+       u16 *sprom;
+       int err = 0;
+
+       if (!bus->drv_cc.core)
+               return -EOPNOTSUPP;
+
+       sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
+                       GFP_KERNEL);
+       if (!sprom)
+               return -ENOMEM;
+
+       bcma_sprom_read(bus, sprom);
+
+       err = bcma_sprom_valid(sprom);
+       if (err)
+               goto out;
+
+       bcma_sprom_extract_r8(bus, sprom);
+
+out:
+       kfree(sprom);
+       return err;
+}
index a69331e..91f7e6a 100644 (file)
@@ -2335,7 +2335,7 @@ static struct ssb_driver b44_ssb_driver = {
        .resume         = b44_resume,
 };
 
-static inline int b44_pci_init(void)
+static inline int __init b44_pci_init(void)
 {
        int err = 0;
 #ifdef CONFIG_B44_PCI
@@ -2344,7 +2344,7 @@ static inline int b44_pci_init(void)
        return err;
 }
 
-static inline void b44_pci_exit(void)
+static inline void __exit b44_pci_exit(void)
 {
 #ifdef CONFIG_B44_PCI
        ssb_pcihost_unregister(&b44_pci_driver);
index 7cf4317..17c4b56 100644 (file)
@@ -161,6 +161,7 @@ struct ath_common {
        const struct ath_bus_ops *bus_ops;
 
        bool btcoex_enabled;
+       bool disable_ani;
 };
 
 struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
index ea99827..ba682a0 100644 (file)
@@ -167,8 +167,8 @@ static int ath_ahb_probe(struct platform_device *pdev)
                 * driver for it
                 */
                if (to_platform_device(sc->dev)->id == 0 &&
-                   (bcfg->config->flags & (BD_WLAN0|BD_WLAN1)) ==
-                    (BD_WLAN1|BD_WLAN0))
+                   (bcfg->config->flags & (BD_WLAN0 | BD_WLAN1)) ==
+                    (BD_WLAN1 | BD_WLAN0))
                        __set_bit(ATH_STAT_2G_DISABLED, sc->status);
        }
 
@@ -219,6 +219,7 @@ static int ath_ahb_remove(struct platform_device *pdev)
 
        ath5k_deinit_softc(sc);
        platform_set_drvdata(pdev, NULL);
+       ieee80211_free_hw(hw);
 
        return 0;
 }
index f915f40..a08f173 100644 (file)
@@ -642,7 +642,7 @@ ath5k_ani_init(struct ath5k_hw *ah, enum ath5k_ani_mode mode)
        /* initial values for our ani parameters */
        if (mode == ATH5K_ANI_MODE_OFF) {
                ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "ANI off\n");
-       } else if  (mode == ATH5K_ANI_MODE_MANUAL_LOW) {
+       } else if (mode == ATH5K_ANI_MODE_MANUAL_LOW) {
                ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI,
                        "ANI manual low -> high sensitivity\n");
                ath5k_ani_set_noise_immunity_level(ah, 0);
index bb50700..b1de4a0 100644 (file)
 #include "../ath.h"
 
 /* PCI IDs */
-#define PCI_DEVICE_ID_ATHEROS_AR5210           0x0007 /* AR5210 */
-#define PCI_DEVICE_ID_ATHEROS_AR5311           0x0011 /* AR5311 */
-#define PCI_DEVICE_ID_ATHEROS_AR5211           0x0012 /* AR5211 */
-#define PCI_DEVICE_ID_ATHEROS_AR5212           0x0013 /* AR5212 */
-#define PCI_DEVICE_ID_3COM_3CRDAG675           0x0013 /* 3CRDAG675 (Atheros AR5212) */
-#define PCI_DEVICE_ID_3COM_2_3CRPAG175                 0x0013 /* 3CRPAG175 (Atheros AR5212) */
-#define PCI_DEVICE_ID_ATHEROS_AR5210_AP        0x0207 /* AR5210 (Early) */
+#define PCI_DEVICE_ID_ATHEROS_AR5210           0x0007 /* AR5210 */
+#define PCI_DEVICE_ID_ATHEROS_AR5311           0x0011 /* AR5311 */
+#define PCI_DEVICE_ID_ATHEROS_AR5211           0x0012 /* AR5211 */
+#define PCI_DEVICE_ID_ATHEROS_AR5212           0x0013 /* AR5212 */
+#define PCI_DEVICE_ID_3COM_3CRDAG675           0x0013 /* 3CRDAG675 (Atheros AR5212) */
+#define PCI_DEVICE_ID_3COM_2_3CRPAG175         0x0013 /* 3CRPAG175 (Atheros AR5212) */
+#define PCI_DEVICE_ID_ATHEROS_AR5210_AP                0x0207 /* AR5210 (Early) */
 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM       0x1014 /* AR5212 (IBM MiniPCI) */
-#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT   0x1107 /* AR5210 (no eeprom) */
-#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT   0x1113 /* AR5212 (no eeprom) */
-#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT   0x1112 /* AR5211 (no eeprom) */
-#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA      0xf013 /* AR5212 (emulation board) */
-#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY    0xff12 /* AR5211 (emulation board) */
-#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B   0xf11b /* AR5211 (emulation board) */
-#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2      0x0052 /* AR5312 WMAC (AP31) */
-#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7      0x0057 /* AR5312 WMAC (AP30-040) */
-#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8      0x0058 /* AR5312 WMAC (AP43-030) */
-#define PCI_DEVICE_ID_ATHEROS_AR5212_0014      0x0014 /* AR5212 compatible */
-#define PCI_DEVICE_ID_ATHEROS_AR5212_0015      0x0015 /* AR5212 compatible */
-#define PCI_DEVICE_ID_ATHEROS_AR5212_0016      0x0016 /* AR5212 compatible */
-#define PCI_DEVICE_ID_ATHEROS_AR5212_0017      0x0017 /* AR5212 compatible */
-#define PCI_DEVICE_ID_ATHEROS_AR5212_0018      0x0018 /* AR5212 compatible */
-#define PCI_DEVICE_ID_ATHEROS_AR5212_0019      0x0019 /* AR5212 compatible */
-#define PCI_DEVICE_ID_ATHEROS_AR2413           0x001a /* AR2413 (Griffin-lite) */
-#define PCI_DEVICE_ID_ATHEROS_AR5413           0x001b /* AR5413 (Eagle) */
-#define PCI_DEVICE_ID_ATHEROS_AR5424           0x001c /* AR5424 (Condor PCI-E) */
-#define PCI_DEVICE_ID_ATHEROS_AR5416           0x0023 /* AR5416 */
-#define PCI_DEVICE_ID_ATHEROS_AR5418           0x0024 /* AR5418 */
+#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT   0x1107 /* AR5210 (no eeprom) */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT   0x1113 /* AR5212 (no eeprom) */
+#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT   0x1112 /* AR5211 (no eeprom) */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA      0xf013 /* AR5212 (emulation board) */
+#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY    0xff12 /* AR5211 (emulation board) */
+#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B   0xf11b /* AR5211 (emulation board) */
+#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2      0x0052 /* AR5312 WMAC (AP31) */
+#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7      0x0057 /* AR5312 WMAC (AP30-040) */
+#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8      0x0058 /* AR5312 WMAC (AP43-030) */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_0014      0x0014 /* AR5212 compatible */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_0015      0x0015 /* AR5212 compatible */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_0016      0x0016 /* AR5212 compatible */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_0017      0x0017 /* AR5212 compatible */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_0018      0x0018 /* AR5212 compatible */
+#define PCI_DEVICE_ID_ATHEROS_AR5212_0019      0x0019 /* AR5212 compatible */
+#define PCI_DEVICE_ID_ATHEROS_AR2413           0x001a /* AR2413 (Griffin-lite) */
+#define PCI_DEVICE_ID_ATHEROS_AR5413           0x001b /* AR5413 (Eagle) */
+#define PCI_DEVICE_ID_ATHEROS_AR5424           0x001c /* AR5424 (Condor PCI-E) */
+#define PCI_DEVICE_ID_ATHEROS_AR5416           0x0023 /* AR5416 */
+#define PCI_DEVICE_ID_ATHEROS_AR5418           0x0024 /* AR5418 */
 
 /****************************\
   GENERIC DRIVER DEFINITIONS
 \****************************/
 
-#define ATH5K_PRINTF(fmt, ...)   printk("%s: " fmt, __func__, ##__VA_ARGS__)
+#define ATH5K_PRINTF(fmt, ...) \
+       printk(KERN_WARNING "%s: " fmt, __func__, ##__VA_ARGS__)
 
 #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
        printk(_level "ath5k %s: " _fmt, \
@@ -361,7 +362,7 @@ struct ath5k_srev_name {
 /*
  * Some of this information is based on Documentation from:
  *
- * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG 
+ * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG
  *
  * Modulation for Atheros' eXtended Range - range enhancing extension that is
  * supposed to double the distance an Atheros client device can keep a
@@ -374,7 +375,7 @@ struct ath5k_srev_name {
  * they are exclusive.
  *
  */
-#define MODULATION_XR          0x00000200
+#define MODULATION_XR          0x00000200
 /*
  * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
  * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
@@ -495,9 +496,9 @@ enum ath5k_tx_queue {
  */
 enum ath5k_tx_queue_subtype {
        AR5K_WME_AC_BK = 0,     /*Background traffic*/
-       AR5K_WME_AC_BE,         /*Best-effort (normal) traffic)*/
-       AR5K_WME_AC_VI,         /*Video traffic*/
-       AR5K_WME_AC_VO,         /*Voice traffic*/
+       AR5K_WME_AC_BE,         /*Best-effort (normal) traffic)*/
+       AR5K_WME_AC_VI,         /*Video traffic*/
+       AR5K_WME_AC_VO,         /*Voice traffic*/
 };
 
 /*
@@ -616,8 +617,8 @@ struct ath5k_rx_status {
 #define AR5K_RXERR_FIFO                0x04
 #define AR5K_RXERR_DECRYPT     0x08
 #define AR5K_RXERR_MIC         0x10
-#define AR5K_RXKEYIX_INVALID   ((u8) - 1)
-#define AR5K_TXKEYIX_INVALID   ((u32) - 1)
+#define AR5K_RXKEYIX_INVALID   ((u8) -1)
+#define AR5K_TXKEYIX_INVALID   ((u32) -1)
 
 
 /**************************\
@@ -678,12 +679,13 @@ struct ath5k_gain {
 #define        CHANNEL_DYN     0x0400  /* Dynamic CCK-OFDM channel (for g operation) */
 #define        CHANNEL_XR      0x0800  /* XR channel */
 
-#define        CHANNEL_A       (CHANNEL_5GHZ|CHANNEL_OFDM)
-#define        CHANNEL_B       (CHANNEL_2GHZ|CHANNEL_CCK)
-#define        CHANNEL_G       (CHANNEL_2GHZ|CHANNEL_OFDM)
-#define        CHANNEL_X       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
+#define        CHANNEL_A       (CHANNEL_5GHZ | CHANNEL_OFDM)
+#define        CHANNEL_B       (CHANNEL_2GHZ | CHANNEL_CCK)
+#define        CHANNEL_G       (CHANNEL_2GHZ | CHANNEL_OFDM)
+#define        CHANNEL_X       (CHANNEL_5GHZ | CHANNEL_OFDM | CHANNEL_XR)
 
-#define        CHANNEL_ALL     (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ)
+#define        CHANNEL_ALL     (CHANNEL_OFDM | CHANNEL_CCK | \
+                        CHANNEL_2GHZ | CHANNEL_5GHZ)
 
 #define CHANNEL_MODES          CHANNEL_ALL
 
@@ -767,6 +769,7 @@ struct ath5k_athchan_2ghz {
  */
 
 #define AR5K_KEYCACHE_SIZE     8
+extern int ath5k_modparam_nohwcrypt;
 
 /***********************\
  HW RELATED DEFINITIONS
@@ -775,11 +778,11 @@ struct ath5k_athchan_2ghz {
 /*
  * Misc definitions
  */
-#define        AR5K_RSSI_EP_MULTIPLIER (1<<7)
+#define        AR5K_RSSI_EP_MULTIPLIER (1 << 7)
 
 #define AR5K_ASSERT_ENTRY(_e, _s) do {         \
        if (_e >= _s)                           \
-               return (false);                 \
+               return false;                   \
 } while (0)
 
 /*
@@ -790,47 +793,47 @@ struct ath5k_athchan_2ghz {
  * enum ath5k_int - Hardware interrupt masks helpers
  *
  * @AR5K_INT_RX: mask to identify received frame interrupts, of type
- *     AR5K_ISR_RXOK or AR5K_ISR_RXERR
+ *     AR5K_ISR_RXOK or AR5K_ISR_RXERR
  * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
  * @AR5K_INT_RXNOFRM: No frame received (?)
  * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
- *     Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
- *     LinkPtr is NULL. For more details, refer to:
- *     http://www.freepatentsonline.com/20030225739.html
+ *     Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
+ *     LinkPtr is NULL. For more details, refer to:
+ *     http://www.freepatentsonline.com/20030225739.html
  * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
- *     Note that Rx overrun is not always fatal, on some chips we can continue
- *     operation without reseting the card, that's why int_fatal is not
- *     common for all chips.
+ *     Note that Rx overrun is not always fatal, on some chips we can continue
+ *     operation without reseting the card, that's why int_fatal is not
+ *     common for all chips.
  * @AR5K_INT_TX: mask to identify received frame interrupts, of type
- *     AR5K_ISR_TXOK or AR5K_ISR_TXERR
+ *     AR5K_ISR_TXOK or AR5K_ISR_TXERR
  * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
  * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
- *     We currently do increments on interrupt by
- *     (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
+ *     We currently do increments on interrupt by
+ *     (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
  * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
  *     one of the PHY error counters reached the maximum value and should be
  *     read and cleared.
  * @AR5K_INT_RXPHY: RX PHY Error
  * @AR5K_INT_RXKCM: RX Key cache miss
  * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
- *     beacon that must be handled in software. The alternative is if you
- *     have VEOL support, in that case you let the hardware deal with things.
+ *     beacon that must be handled in software. The alternative is if you
+ *     have VEOL support, in that case you let the hardware deal with things.
  * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
- *     beacons from the AP have associated with, we should probably try to
- *     reassociate. When in IBSS mode this might mean we have not received
- *     any beacons from any local stations. Note that every station in an
- *     IBSS schedules to send beacons at the Target Beacon Transmission Time
- *     (TBTT) with a random backoff.
+ *     beacons from the AP have associated with, we should probably try to
+ *     reassociate. When in IBSS mode this might mean we have not received
+ *     any beacons from any local stations. Note that every station in an
+ *     IBSS schedules to send beacons at the Target Beacon Transmission Time
+ *     (TBTT) with a random backoff.
  * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
  * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
- *     until properly handled
+ *     until properly handled
  * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
- *     errors. These types of errors we can enable seem to be of type
- *     AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
+ *     errors. These types of errors we can enable seem to be of type
+ *     AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
  * @AR5K_INT_GLOBAL: Used to clear and set the IER
  * @AR5K_INT_NOCARD: signals the card has been removed
  * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
- *     bit value
+ *     bit value
  *
  * These are mapped to take advantage of some common bits
  * between the MACs, to be able to set intr properties
@@ -967,9 +970,9 @@ enum ath5k_capability_type {
        AR5K_CAP_MCAST_KEYSRCH          = 14,   /* Supports multicast key search */
        AR5K_CAP_TSF_ADJUST             = 15,   /* Supports beacon tsf adjust */
        AR5K_CAP_XR                     = 16,   /* Supports XR mode */
-       AR5K_CAP_WME_TKIPMIC            = 17,   /* Supports TKIP MIC when using WMM */
-       AR5K_CAP_CHAN_HALFRATE          = 18,   /* Supports half rate channels */
-       AR5K_CAP_CHAN_QUARTERRATE       = 19,   /* Supports quarter rate channels */
+       AR5K_CAP_WME_TKIPMIC            = 17,   /* Supports TKIP MIC when using WMM */
+       AR5K_CAP_CHAN_HALFRATE          = 18,   /* Supports half rate channels */
+       AR5K_CAP_CHAN_QUARTERRATE       = 19,   /* Supports quarter rate channels */
        AR5K_CAP_RFSILENT               = 20,   /* Supports RFsilent */
 };
 
@@ -1009,8 +1012,7 @@ struct ath5k_capabilities {
 
 /* size of noise floor history (keep it a power of two) */
 #define ATH5K_NF_CAL_HIST_MAX  8
-struct ath5k_nfcal_hist
-{
+struct ath5k_nfcal_hist {
        s16 index;                              /* current index into nfval */
        s16 nfval[ATH5K_NF_CAL_HIST_MAX];       /* last few noise floors */
 };
@@ -1180,8 +1182,8 @@ void ath5k_sysfs_unregister(struct ath5k_softc *sc);
 struct ath5k_buf;
 struct ath5k_txq;
 
-void set_beacon_filter(struct ieee80211_hw *hw, bool enable);
-bool ath_any_vif_assoc(struct ath5k_softc *sc);
+void ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable);
+bool ath5k_any_vif_assoc(struct ath5k_softc *sc);
 void ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
                    struct ath5k_txq *txq);
 int ath5k_init_hw(struct ath5k_softc *sc);
@@ -1253,7 +1255,7 @@ int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
                int len, struct ieee80211_rate *rate, bool shortpre);
 unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah);
 unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah);
-extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
+int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
 /* RX filter control*/
 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
@@ -1361,12 +1363,12 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
 
 static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
 {
-        return &ah->common;
+       return &ah->common;
 }
 
 static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
 {
-        return &(ath5k_hw_common(ah)->regulatory);
+       return &(ath5k_hw_common(ah)->regulatory);
 }
 
 #ifdef CONFIG_ATHEROS_AR231X
@@ -1377,7 +1379,7 @@ static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg)
        /* On AR2315 and AR2317 the PCI clock domain registers
         * are outside of the WMAC register space */
        if (unlikely((reg >= 0x4000) && (reg < 0x5000) &&
-               (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6)))
+           (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6)))
                return AR5K_AR2315_PCI_BASE + reg;
 
        return ah->ah_iobase + reg;
index 1588401..d6fbb57 100644 (file)
@@ -104,6 +104,7 @@ static int ath5k_hw_post(struct ath5k_hw *ah)
  */
 int ath5k_hw_init(struct ath5k_softc *sc)
 {
+       static const u8 zero_mac[ETH_ALEN] = { };
        struct ath5k_hw *ah = sc->ah;
        struct ath_common *common = ath5k_hw_common(ah);
        struct pci_dev *pdev = sc->pdev;
@@ -191,7 +192,7 @@ int ath5k_hw_init(struct ath5k_softc *sc)
                break;
        case AR5K_SREV_RAD_5424:
                if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
-               ah->ah_mac_version == AR5K_SREV_AR2417){
+                   ah->ah_mac_version == AR5K_SREV_AR2417) {
                        ah->ah_radio = AR5K_RF2425;
                        ah->ah_single_chip = true;
                } else {
@@ -210,28 +211,28 @@ int ath5k_hw_init(struct ath5k_softc *sc)
                        ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
                                                                CHANNEL_2GHZ);
                } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
-               ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
-               ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
+                          ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
+                          ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
                        ah->ah_radio = AR5K_RF2425;
                        ah->ah_single_chip = true;
                        ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
                } else if (srev == AR5K_SREV_AR5213A &&
-               ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
+                          ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
                        ah->ah_radio = AR5K_RF5112;
                        ah->ah_single_chip = false;
                        ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
                } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4) ||
-                       ah->ah_mac_version == (AR5K_SREV_AR2315_R6 >> 4)) {
+                          ah->ah_mac_version == (AR5K_SREV_AR2315_R6 >> 4)) {
                        ah->ah_radio = AR5K_RF2316;
                        ah->ah_single_chip = true;
                        ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
                } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
-               ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
+                          ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
                        ah->ah_radio = AR5K_RF5413;
                        ah->ah_single_chip = true;
                        ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
                } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
-               ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
+                          ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
                        ah->ah_radio = AR5K_RF2413;
                        ah->ah_single_chip = true;
                        ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
@@ -244,8 +245,7 @@ int ath5k_hw_init(struct ath5k_softc *sc)
 
 
        /* Return on unsuported chips (unsupported eeprom etc) */
-       if ((srev >= AR5K_SREV_AR5416) &&
-       (srev < AR5K_SREV_AR2425)) {
+       if ((srev >= AR5K_SREV_AR5416) && (srev < AR5K_SREV_AR2425)) {
                ATH5K_ERR(sc, "Device not yet supported.\n");
                ret = -ENODEV;
                goto err;
@@ -334,7 +334,7 @@ int ath5k_hw_init(struct ath5k_softc *sc)
        }
 
        /* MAC address is cleared until add_interface */
-       ath5k_hw_set_lladdr(ah, (u8[ETH_ALEN]){});
+       ath5k_hw_set_lladdr(ah, zero_mac);
 
        /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
        memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
index b6c5d37..28113e0 100644 (file)
@@ -87,8 +87,6 @@ MODULE_LICENSE("Dual BSD/GPL");
 static int ath5k_init(struct ieee80211_hw *hw);
 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
                                                                bool skip_pcu);
-int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
-void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
 
 /* Known SREVs */
 static const struct ath5k_srev_name srev_names[] = {
@@ -816,8 +814,7 @@ ath5k_desc_alloc(struct ath5k_softc *sc)
 
        INIT_LIST_HEAD(&sc->txbuf);
        sc->txbuf_len = ATH_TXBUF;
-       for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
-                       da += sizeof(*ds)) {
+       for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
                bf->desc = ds;
                bf->daddr = da;
                list_add_tail(&bf->list, &sc->txbuf);
@@ -983,7 +980,7 @@ ath5k_beaconq_config(struct ath5k_softc *sc)
                goto err;
 
        if (sc->opmode == NL80211_IFTYPE_AP ||
-               sc->opmode == NL80211_IFTYPE_MESH_POINT) {
+           sc->opmode == NL80211_IFTYPE_MESH_POINT) {
                /*
                 * Always burst out beacon and CAB traffic
                 * (aifs = cwmin = cwmax = 0)
@@ -1263,16 +1260,15 @@ ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
  */
 static int ath5k_common_padpos(struct sk_buff *skb)
 {
-       struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
+       struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
        __le16 frame_control = hdr->frame_control;
        int padpos = 24;
 
-       if (ieee80211_has_a4(frame_control)) {
+       if (ieee80211_has_a4(frame_control))
                padpos += ETH_ALEN;
-       }
-       if (ieee80211_is_data_qos(frame_control)) {
+
+       if (ieee80211_is_data_qos(frame_control))
                padpos += IEEE80211_QOS_CTL_LEN;
-       }
 
        return padpos;
 }
@@ -1286,13 +1282,13 @@ static int ath5k_add_padding(struct sk_buff *skb)
        int padpos = ath5k_common_padpos(skb);
        int padsize = padpos & 3;
 
-       if (padsize && skb->len>padpos) {
+       if (padsize && skb->len > padpos) {
 
                if (skb_headroom(skb) < padsize)
                        return -1;
 
                skb_push(skb, padsize);
-               memmove(skb->data, skb->data+padsize, padpos);
+               memmove(skb->data, skb->data + padsize, padpos);
                return padsize;
        }
 
@@ -1317,7 +1313,7 @@ static int ath5k_remove_padding(struct sk_buff *skb)
        int padpos = ath5k_common_padpos(skb);
        int padsize = padpos & 3;
 
-       if (padsize && skb->len>=padpos+padsize) {
+       if (padsize && skb->len >= padpos + padsize) {
                memmove(skb->data + padsize, skb->data, padpos);
                skb_pull(skb, padsize);
                return padsize;
@@ -1451,10 +1447,11 @@ ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
 static void
 ath5k_set_current_imask(struct ath5k_softc *sc)
 {
-       enum ath5k_int imask = sc->imask;
+       enum ath5k_int imask;
        unsigned long flags;
 
        spin_lock_irqsave(&sc->irqlock, flags);
+       imask = sc->imask;
        if (sc->rx_pending)
                imask &= ~AR5K_INT_RX_ALL;
        if (sc->tx_pending)
@@ -1712,7 +1709,7 @@ ath5k_tasklet_tx(unsigned long data)
        int i;
        struct ath5k_softc *sc = (void *)data;
 
-       for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
+       for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
                if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
                        ath5k_tx_processq(sc, &sc->txqs[i]);
 
@@ -1903,7 +1900,7 @@ ath5k_beacon_send(struct ath5k_softc *sc)
        avf = (void *)vif->drv_priv;
        bf = avf->bbuf;
        if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
-                       sc->opmode == NL80211_IFTYPE_MONITOR)) {
+                    sc->opmode == NL80211_IFTYPE_MONITOR)) {
                ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
                return;
        }
@@ -1920,7 +1917,7 @@ ath5k_beacon_send(struct ath5k_softc *sc)
 
        /* refresh the beacon for AP or MESH mode */
        if (sc->opmode == NL80211_IFTYPE_AP ||
-                       sc->opmode == NL80211_IFTYPE_MESH_POINT)
+           sc->opmode == NL80211_IFTYPE_MESH_POINT)
                ath5k_beacon_update(sc->hw, vif);
 
        trace_ath5k_tx(sc, bf->skb, &sc->txqs[sc->bhalq]);
@@ -1979,7 +1976,7 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
        hw_tsf = ath5k_hw_get_tsf64(ah);
        hw_tu = TSF_TO_TU(hw_tsf);
 
-#define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
+#define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
        /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
         * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
         * configuration we need to make sure it is bigger than that. */
@@ -2161,7 +2158,7 @@ ath5k_schedule_tx(struct ath5k_softc *sc)
        tasklet_schedule(&sc->txtq);
 }
 
-irqreturn_t
+static irqreturn_t
 ath5k_intr(int irq, void *dev_id)
 {
        struct ath5k_softc *sc = dev_id;
@@ -2201,13 +2198,12 @@ ath5k_intr(int irq, void *dev_id)
                                ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
                                          "rx overrun, resetting\n");
                                ieee80211_queue_work(sc->hw, &sc->reset_work);
-                       }
-                       else
+                       } else
                                ath5k_schedule_rx(sc);
                } else {
-                       if (status & AR5K_INT_SWBA) {
+                       if (status & AR5K_INT_SWBA)
                                tasklet_hi_schedule(&sc->beacontq);
-                       }
+
                        if (status & AR5K_INT_RXEOL) {
                                /*
                                * NB: the hardware should re-read the link when
@@ -2359,7 +2355,7 @@ ath5k_tx_complete_poll_work(struct work_struct *work)
 * Initialization routines *
 \*************************/
 
-int
+int __devinit
 ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
 {
        struct ieee80211_hw *hw = sc->hw;
@@ -2489,7 +2485,7 @@ ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
                /* Multi chip radio (RF5111 - RF2111) ->
                 * report both 2GHz/5GHz radios */
                else if (sc->ah->ah_radio_5ghz_revision &&
-                               sc->ah->ah_radio_2ghz_revision){
+                               sc->ah->ah_radio_2ghz_revision) {
                        ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
                                ath5k_chip_name(AR5K_VERSION_RAD,
                                        sc->ah->ah_radio_5ghz_revision),
@@ -2615,7 +2611,7 @@ done:
        return ret;
 }
 
-static void stop_tasklets(struct ath5k_softc *sc)
+static void ath5k_stop_tasklets(struct ath5k_softc *sc)
 {
        sc->rx_pending = false;
        sc->tx_pending = false;
@@ -2669,7 +2665,7 @@ ath5k_stop_hw(struct ath5k_softc *sc)
        mmiowb();
        mutex_unlock(&sc->lock);
 
-       stop_tasklets(sc);
+       ath5k_stop_tasklets(sc);
 
        cancel_delayed_work_sync(&sc->tx_complete_work);
 
@@ -2697,7 +2693,7 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
 
        ath5k_hw_set_imr(ah, 0);
        synchronize_irq(sc->irq);
-       stop_tasklets(sc);
+       ath5k_stop_tasklets(sc);
 
        /* Save ani mode and disable ANI during
         * reset. If we don't we might get false
@@ -2714,8 +2710,7 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
 
        fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
 
-       ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, fast,
-                                                               skip_pcu);
+       ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, fast, skip_pcu);
        if (ret) {
                ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
                goto err;
@@ -2773,7 +2768,7 @@ static void ath5k_reset_work(struct work_struct *work)
        mutex_unlock(&sc->lock);
 }
 
-static int
+static int __devinit
 ath5k_init(struct ieee80211_hw *hw)
 {
 
@@ -2962,11 +2957,12 @@ ath5k_deinit_softc(struct ath5k_softc *sc)
         * state and potentially want to use them.
         */
        ath5k_hw_deinit(sc->ah);
+       kfree(sc->ah);
        free_irq(sc->irq, sc);
 }
 
 bool
-ath_any_vif_assoc(struct ath5k_softc *sc)
+ath5k_any_vif_assoc(struct ath5k_softc *sc)
 {
        struct ath5k_vif_iter_data iter_data;
        iter_data.hw_macaddr = NULL;
@@ -2980,7 +2976,7 @@ ath_any_vif_assoc(struct ath5k_softc *sc)
 }
 
 void
-set_beacon_filter(struct ieee80211_hw *hw, bool enable)
+ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
 {
        struct ath5k_softc *sc = hw->priv;
        struct ath5k_hw *ah = sc->ah;
index b294f33..e71494e 100644 (file)
@@ -96,8 +96,7 @@ struct ath5k_txq {
 /*
  * State for LED triggers
  */
-struct ath5k_led
-{
+struct ath5k_led {
        char name[ATH5K_LED_MAX_NAME_LEN + 1];  /* name of the LED in sysfs */
        struct ath5k_softc *sc;                 /* driver state */
        struct led_classdev led_dev;            /* led classdev */
@@ -154,9 +153,9 @@ struct ath5k_statistics {
 };
 
 #if CHAN_DEBUG
-#define ATH_CHAN_MAX   (26+26+26+200+200)
+#define ATH_CHAN_MAX   (26 + 26 + 26 + 200 + 200)
 #else
-#define ATH_CHAN_MAX   (14+14+14+252+20)
+#define ATH_CHAN_MAX   (14 + 14 + 14 + 252 + 20)
 #endif
 
 struct ath5k_vif {
@@ -251,7 +250,7 @@ struct ath5k_softc {
        unsigned int            nexttbtt;       /* next beacon time in TU */
        struct ath5k_txq        *cabq;          /* content after beacon */
 
-       int                     power_level;    /* Requested tx power in dbm */
+       int                     power_level;    /* Requested tx power in dbm */
        bool                    assoc;          /* associate state */
        bool                    enable_beacon;  /* true if beacons are on */
 
index 0bf7313..ae1112b 100644 (file)
@@ -205,35 +205,35 @@ static ssize_t read_file_beacon(struct file *file, char __user *user_buf,
        u64 tsf;
 
        v = ath5k_hw_reg_read(sc->ah, AR5K_BEACON);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                "%-24s0x%08x\tintval: %d\tTIM: 0x%x\n",
                "AR5K_BEACON", v, v & AR5K_BEACON_PERIOD,
                (v & AR5K_BEACON_TIM) >> AR5K_BEACON_TIM_S);
 
-       len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "%-24s0x%08x\n",
                "AR5K_LAST_TSTP", ath5k_hw_reg_read(sc->ah, AR5K_LAST_TSTP));
 
-       len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\n\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "%-24s0x%08x\n\n",
                "AR5K_BEACON_CNT", ath5k_hw_reg_read(sc->ah, AR5K_BEACON_CNT));
 
        v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER0);
-       len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "%-24s0x%08x\tTU: %08x\n",
                "AR5K_TIMER0 (TBTT)", v, v);
 
        v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER1);
-       len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "%-24s0x%08x\tTU: %08x\n",
                "AR5K_TIMER1 (DMA)", v, v >> 3);
 
        v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER2);
-       len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "%-24s0x%08x\tTU: %08x\n",
                "AR5K_TIMER2 (SWBA)", v, v >> 3);
 
        v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER3);
-       len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "%-24s0x%08x\tTU: %08x\n",
                "AR5K_TIMER3 (ATIM)", v, v);
 
        tsf = ath5k_hw_get_tsf64(sc->ah);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                "TSF\t\t0x%016llx\tTU: %08x\n",
                (unsigned long long)tsf, TSF_TO_TU(tsf));
 
@@ -323,16 +323,16 @@ static ssize_t read_file_debug(struct file *file, char __user *user_buf,
        unsigned int len = 0;
        unsigned int i;
 
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                "DEBUG LEVEL: 0x%08x\n\n", sc->debug.level);
 
        for (i = 0; i < ARRAY_SIZE(dbg_info) - 1; i++) {
-               len += snprintf(buf+len, sizeof(buf)-len,
+               len += snprintf(buf + len, sizeof(buf) - len,
                        "%10s %c 0x%08x - %s\n", dbg_info[i].name,
                        sc->debug.level & dbg_info[i].level ? '+' : ' ',
                        dbg_info[i].level, dbg_info[i].desc);
        }
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                "%10s %c 0x%08x - %s\n", dbg_info[i].name,
                sc->debug.level == dbg_info[i].level ? '+' : ' ',
                dbg_info[i].level, dbg_info[i].desc);
@@ -384,60 +384,60 @@ static ssize_t read_file_antenna(struct file *file, char __user *user_buf,
        unsigned int i;
        unsigned int v;
 
-       len += snprintf(buf+len, sizeof(buf)-len, "antenna mode\t%d\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "antenna mode\t%d\n",
                sc->ah->ah_ant_mode);
-       len += snprintf(buf+len, sizeof(buf)-len, "default antenna\t%d\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "default antenna\t%d\n",
                sc->ah->ah_def_ant);
-       len += snprintf(buf+len, sizeof(buf)-len, "tx antenna\t%d\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "tx antenna\t%d\n",
                sc->ah->ah_tx_ant);
 
-       len += snprintf(buf+len, sizeof(buf)-len, "\nANTENNA\t\tRX\tTX\n");
+       len += snprintf(buf + len, sizeof(buf) - len, "\nANTENNA\t\tRX\tTX\n");
        for (i = 1; i < ARRAY_SIZE(sc->stats.antenna_rx); i++) {
-               len += snprintf(buf+len, sizeof(buf)-len,
+               len += snprintf(buf + len, sizeof(buf) - len,
                        "[antenna %d]\t%d\t%d\n",
                        i, sc->stats.antenna_rx[i], sc->stats.antenna_tx[i]);
        }
-       len += snprintf(buf+len, sizeof(buf)-len, "[invalid]\t%d\t%d\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "[invalid]\t%d\t%d\n",
                        sc->stats.antenna_rx[0], sc->stats.antenna_tx[0]);
 
        v = ath5k_hw_reg_read(sc->ah, AR5K_DEFAULT_ANTENNA);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "\nAR5K_DEFAULT_ANTENNA\t0x%08x\n", v);
 
        v = ath5k_hw_reg_read(sc->ah, AR5K_STA_ID1);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                "AR5K_STA_ID1_DEFAULT_ANTENNA\t%d\n",
                (v & AR5K_STA_ID1_DEFAULT_ANTENNA) != 0);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                "AR5K_STA_ID1_DESC_ANTENNA\t%d\n",
                (v & AR5K_STA_ID1_DESC_ANTENNA) != 0);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                "AR5K_STA_ID1_RTS_DEF_ANTENNA\t%d\n",
                (v & AR5K_STA_ID1_RTS_DEF_ANTENNA) != 0);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                "AR5K_STA_ID1_SELFGEN_DEF_ANT\t%d\n",
                (v & AR5K_STA_ID1_SELFGEN_DEF_ANT) != 0);
 
        v = ath5k_hw_reg_read(sc->ah, AR5K_PHY_AGCCTL);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                "\nAR5K_PHY_AGCCTL_OFDM_DIV_DIS\t%d\n",
                (v & AR5K_PHY_AGCCTL_OFDM_DIV_DIS) != 0);
 
        v = ath5k_hw_reg_read(sc->ah, AR5K_PHY_RESTART);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                "AR5K_PHY_RESTART_DIV_GC\t\t%x\n",
                (v & AR5K_PHY_RESTART_DIV_GC) >> AR5K_PHY_RESTART_DIV_GC_S);
 
        v = ath5k_hw_reg_read(sc->ah, AR5K_PHY_FAST_ANT_DIV);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                "AR5K_PHY_FAST_ANT_DIV_EN\t%d\n",
                (v & AR5K_PHY_FAST_ANT_DIV_EN) != 0);
 
        v = ath5k_hw_reg_read(sc->ah, AR5K_PHY_ANT_SWITCH_TABLE_0);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "\nAR5K_PHY_ANT_SWITCH_TABLE_0\t0x%08x\n", v);
        v = ath5k_hw_reg_read(sc->ah, AR5K_PHY_ANT_SWITCH_TABLE_1);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "AR5K_PHY_ANT_SWITCH_TABLE_1\t0x%08x\n", v);
 
        if (len > sizeof(buf))
@@ -494,36 +494,36 @@ static ssize_t read_file_misc(struct file *file, char __user *user_buf,
        unsigned int len = 0;
        u32 filt = ath5k_hw_get_rx_filter(sc->ah);
 
-       len += snprintf(buf+len, sizeof(buf)-len, "bssid-mask: %pM\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "bssid-mask: %pM\n",
                        sc->bssidmask);
-       len += snprintf(buf+len, sizeof(buf)-len, "filter-flags: 0x%x ",
+       len += snprintf(buf + len, sizeof(buf) - len, "filter-flags: 0x%x ",
                        filt);
        if (filt & AR5K_RX_FILTER_UCAST)
-               len += snprintf(buf+len, sizeof(buf)-len, " UCAST");
+               len += snprintf(buf + len, sizeof(buf) - len, " UCAST");
        if (filt & AR5K_RX_FILTER_MCAST)
-               len += snprintf(buf+len, sizeof(buf)-len, " MCAST");
+               len += snprintf(buf + len, sizeof(buf) - len, " MCAST");
        if (filt & AR5K_RX_FILTER_BCAST)
-               len += snprintf(buf+len, sizeof(buf)-len, " BCAST");
+               len += snprintf(buf + len, sizeof(buf) - len, " BCAST");
        if (filt & AR5K_RX_FILTER_CONTROL)
-               len += snprintf(buf+len, sizeof(buf)-len, " CONTROL");
+               len += snprintf(buf + len, sizeof(buf) - len, " CONTROL");
        if (filt & AR5K_RX_FILTER_BEACON)
-               len += snprintf(buf+len, sizeof(buf)-len, " BEACON");
+               len += snprintf(buf + len, sizeof(buf) - len, " BEACON");
        if (filt & AR5K_RX_FILTER_PROM)
-               len += snprintf(buf+len, sizeof(buf)-len, " PROM");
+               len += snprintf(buf + len, sizeof(buf) - len, " PROM");
        if (filt & AR5K_RX_FILTER_XRPOLL)
-               len += snprintf(buf+len, sizeof(buf)-len, " XRPOLL");
+               len += snprintf(buf + len, sizeof(buf) - len, " XRPOLL");
        if (filt & AR5K_RX_FILTER_PROBEREQ)
-               len += snprintf(buf+len, sizeof(buf)-len, " PROBEREQ");
+               len += snprintf(buf + len, sizeof(buf) - len, " PROBEREQ");
        if (filt & AR5K_RX_FILTER_PHYERR_5212)
-               len += snprintf(buf+len, sizeof(buf)-len, " PHYERR-5212");
+               len += snprintf(buf + len, sizeof(buf) - len, " PHYERR-5212");
        if (filt & AR5K_RX_FILTER_RADARERR_5212)
-               len += snprintf(buf+len, sizeof(buf)-len, " RADARERR-5212");
+               len += snprintf(buf + len, sizeof(buf) - len, " RADARERR-5212");
        if (filt & AR5K_RX_FILTER_PHYERR_5211)
-               snprintf(buf+len, sizeof(buf)-len, " PHYERR-5211");
+               snprintf(buf + len, sizeof(buf) - len, " PHYERR-5211");
        if (filt & AR5K_RX_FILTER_RADARERR_5211)
-               len += snprintf(buf+len, sizeof(buf)-len, " RADARERR-5211");
+               len += snprintf(buf + len, sizeof(buf) - len, " RADARERR-5211");
 
-       len += snprintf(buf+len, sizeof(buf)-len, "\nopmode: %s (%d)\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "\nopmode: %s (%d)\n",
                        ath_opmode_to_string(sc->opmode), sc->opmode);
 
        if (len > sizeof(buf))
@@ -550,65 +550,65 @@ static ssize_t read_file_frameerrors(struct file *file, char __user *user_buf,
        unsigned int len = 0;
        int i;
 
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "RX\n---------------------\n");
-       len += snprintf(buf+len, sizeof(buf)-len, "CRC\t%u\t(%u%%)\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "CRC\t%u\t(%u%%)\n",
                        st->rxerr_crc,
                        st->rx_all_count > 0 ?
-                               st->rxerr_crc*100/st->rx_all_count : 0);
-       len += snprintf(buf+len, sizeof(buf)-len, "PHY\t%u\t(%u%%)\n",
+                               st->rxerr_crc * 100 / st->rx_all_count : 0);
+       len += snprintf(buf + len, sizeof(buf) - len, "PHY\t%u\t(%u%%)\n",
                        st->rxerr_phy,
                        st->rx_all_count > 0 ?
-                               st->rxerr_phy*100/st->rx_all_count : 0);
+                               st->rxerr_phy * 100 / st->rx_all_count : 0);
        for (i = 0; i < 32; i++) {
                if (st->rxerr_phy_code[i])
-                       len += snprintf(buf+len, sizeof(buf)-len,
+                       len += snprintf(buf + len, sizeof(buf) - len,
                                " phy_err[%u]\t%u\n",
                                i, st->rxerr_phy_code[i]);
        }
 
-       len += snprintf(buf+len, sizeof(buf)-len, "FIFO\t%u\t(%u%%)\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "FIFO\t%u\t(%u%%)\n",
                        st->rxerr_fifo,
                        st->rx_all_count > 0 ?
-                               st->rxerr_fifo*100/st->rx_all_count : 0);
-       len += snprintf(buf+len, sizeof(buf)-len, "decrypt\t%u\t(%u%%)\n",
+                               st->rxerr_fifo * 100 / st->rx_all_count : 0);
+       len += snprintf(buf + len, sizeof(buf) - len, "decrypt\t%u\t(%u%%)\n",
                        st->rxerr_decrypt,
                        st->rx_all_count > 0 ?
-                               st->rxerr_decrypt*100/st->rx_all_count : 0);
-       len += snprintf(buf+len, sizeof(buf)-len, "MIC\t%u\t(%u%%)\n",
+                               st->rxerr_decrypt * 100 / st->rx_all_count : 0);
+       len += snprintf(buf + len, sizeof(buf) - len, "MIC\t%u\t(%u%%)\n",
                        st->rxerr_mic,
                        st->rx_all_count > 0 ?
-                               st->rxerr_mic*100/st->rx_all_count : 0);
-       len += snprintf(buf+len, sizeof(buf)-len, "process\t%u\t(%u%%)\n",
+                               st->rxerr_mic * 100 / st->rx_all_count : 0);
+       len += snprintf(buf + len, sizeof(buf) - len, "process\t%u\t(%u%%)\n",
                        st->rxerr_proc,
                        st->rx_all_count > 0 ?
-                               st->rxerr_proc*100/st->rx_all_count : 0);
-       len += snprintf(buf+len, sizeof(buf)-len, "jumbo\t%u\t(%u%%)\n",
+                               st->rxerr_proc * 100 / st->rx_all_count : 0);
+       len += snprintf(buf + len, sizeof(buf) - len, "jumbo\t%u\t(%u%%)\n",
                        st->rxerr_jumbo,
                        st->rx_all_count > 0 ?
-                               st->rxerr_jumbo*100/st->rx_all_count : 0);
-       len += snprintf(buf+len, sizeof(buf)-len, "[RX all\t%u]\n",
+                               st->rxerr_jumbo * 100 / st->rx_all_count : 0);
+       len += snprintf(buf + len, sizeof(buf) - len, "[RX all\t%u]\n",
                        st->rx_all_count);
-       len += snprintf(buf+len, sizeof(buf)-len, "RX-all-bytes\t%u\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "RX-all-bytes\t%u\n",
                        st->rx_bytes_count);
 
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "\nTX\n---------------------\n");
-       len += snprintf(buf+len, sizeof(buf)-len, "retry\t%u\t(%u%%)\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "retry\t%u\t(%u%%)\n",
                        st->txerr_retry,
                        st->tx_all_count > 0 ?
-                               st->txerr_retry*100/st->tx_all_count : 0);
-       len += snprintf(buf+len, sizeof(buf)-len, "FIFO\t%u\t(%u%%)\n",
+                               st->txerr_retry * 100 / st->tx_all_count : 0);
+       len += snprintf(buf + len, sizeof(buf) - len, "FIFO\t%u\t(%u%%)\n",
                        st->txerr_fifo,
                        st->tx_all_count > 0 ?
-                               st->txerr_fifo*100/st->tx_all_count : 0);
-       len += snprintf(buf+len, sizeof(buf)-len, "filter\t%u\t(%u%%)\n",
+                               st->txerr_fifo * 100 / st->tx_all_count : 0);
+       len += snprintf(buf + len, sizeof(buf) - len, "filter\t%u\t(%u%%)\n",
                        st->txerr_filt,
                        st->tx_all_count > 0 ?
-                               st->txerr_filt*100/st->tx_all_count : 0);
-       len += snprintf(buf+len, sizeof(buf)-len, "[TX all\t%u]\n",
+                               st->txerr_filt * 100 / st->tx_all_count : 0);
+       len += snprintf(buf + len, sizeof(buf) - len, "[TX all\t%u]\n",
                        st->tx_all_count);
-       len += snprintf(buf+len, sizeof(buf)-len, "TX-all-bytes\t%u\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "TX-all-bytes\t%u\n",
                        st->tx_bytes_count);
 
        if (len > sizeof(buf))
@@ -667,89 +667,93 @@ static ssize_t read_file_ani(struct file *file, char __user *user_buf,
        char buf[700];
        unsigned int len = 0;
 
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "HW has PHY error counters:\t%s\n",
                        sc->ah->ah_capabilities.cap_has_phyerr_counters ?
                        "yes" : "no");
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "HW max spur immunity level:\t%d\n",
                        as->max_spur_level);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                "\nANI state\n--------------------------------------------\n");
-       len += snprintf(buf+len, sizeof(buf)-len, "operating mode:\t\t\t");
+       len += snprintf(buf + len, sizeof(buf) - len, "operating mode:\t\t\t");
        switch (as->ani_mode) {
        case ATH5K_ANI_MODE_OFF:
-               len += snprintf(buf+len, sizeof(buf)-len, "OFF\n");
+               len += snprintf(buf + len, sizeof(buf) - len, "OFF\n");
                break;
        case ATH5K_ANI_MODE_MANUAL_LOW:
-               len += snprintf(buf+len, sizeof(buf)-len,
+               len += snprintf(buf + len, sizeof(buf) - len,
                        "MANUAL LOW\n");
                break;
        case ATH5K_ANI_MODE_MANUAL_HIGH:
-               len += snprintf(buf+len, sizeof(buf)-len,
+               len += snprintf(buf + len, sizeof(buf) - len,
                        "MANUAL HIGH\n");
                break;
        case ATH5K_ANI_MODE_AUTO:
-               len += snprintf(buf+len, sizeof(buf)-len, "AUTO\n");
+               len += snprintf(buf + len, sizeof(buf) - len, "AUTO\n");
                break;
        default:
-               len += snprintf(buf+len, sizeof(buf)-len,
+               len += snprintf(buf + len, sizeof(buf) - len,
                        "??? (not good)\n");
                break;
        }
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "noise immunity level:\t\t%d\n",
                        as->noise_imm_level);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "spur immunity level:\t\t%d\n",
                        as->spur_level);
-       len += snprintf(buf+len, sizeof(buf)-len, "firstep level:\t\t\t%d\n",
+       len += snprintf(buf + len, sizeof(buf) - len,
+                       "firstep level:\t\t\t%d\n",
                        as->firstep_level);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "OFDM weak signal detection:\t%s\n",
                        as->ofdm_weak_sig ? "on" : "off");
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "CCK weak signal detection:\t%s\n",
                        as->cck_weak_sig ? "on" : "off");
 
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "\nMIB INTERRUPTS:\t\t%u\n",
                        st->mib_intr);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "beacon RSSI average:\t%d\n",
                        (int)ewma_read(&sc->ah->ah_beacon_rssi_avg));
 
 #define CC_PRINT(_struct, _field) \
        _struct._field, \
        _struct.cycles > 0 ? \
-       _struct._field*100/_struct.cycles : 0
+       _struct._field * 100 / _struct.cycles : 0
 
-       len += snprintf(buf+len, sizeof(buf)-len, "profcnt tx\t\t%u\t(%d%%)\n",
+       len += snprintf(buf + len, sizeof(buf) - len,
+                       "profcnt tx\t\t%u\t(%d%%)\n",
                        CC_PRINT(as->last_cc, tx_frame));
-       len += snprintf(buf+len, sizeof(buf)-len, "profcnt rx\t\t%u\t(%d%%)\n",
+       len += snprintf(buf + len, sizeof(buf) - len,
+                       "profcnt rx\t\t%u\t(%d%%)\n",
                        CC_PRINT(as->last_cc, rx_frame));
-       len += snprintf(buf+len, sizeof(buf)-len, "profcnt busy\t\t%u\t(%d%%)\n",
+       len += snprintf(buf + len, sizeof(buf) - len,
+                       "profcnt busy\t\t%u\t(%d%%)\n",
                        CC_PRINT(as->last_cc, rx_busy));
 #undef CC_PRINT
-       len += snprintf(buf+len, sizeof(buf)-len, "profcnt cycles\t\t%u\n",
+       len += snprintf(buf + len, sizeof(buf) - len, "profcnt cycles\t\t%u\n",
                        as->last_cc.cycles);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "listen time\t\t%d\tlast: %d\n",
                        as->listen_time, as->last_listen);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "OFDM errors\t\t%u\tlast: %u\tsum: %u\n",
                        as->ofdm_errors, as->last_ofdm_errors,
                        as->sum_ofdm_errors);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "CCK errors\t\t%u\tlast: %u\tsum: %u\n",
                        as->cck_errors, as->last_cck_errors,
                        as->sum_cck_errors);
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "AR5K_PHYERR_CNT1\t%x\t(=%d)\n",
                        ath5k_hw_reg_read(sc->ah, AR5K_PHYERR_CNT1),
                        ATH5K_ANI_OFDM_TRIG_HIGH - (ATH5K_PHYERR_CNT_MAX -
                        ath5k_hw_reg_read(sc->ah, AR5K_PHYERR_CNT1)));
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "AR5K_PHYERR_CNT2\t%x\t(=%d)\n",
                        ath5k_hw_reg_read(sc->ah, AR5K_PHYERR_CNT2),
                        ATH5K_ANI_CCK_TRIG_HIGH - (ATH5K_PHYERR_CNT_MAX -
@@ -827,13 +831,13 @@ static ssize_t read_file_queue(struct file *file, char __user *user_buf,
        struct ath5k_buf *bf, *bf0;
        int i, n;
 
-       len += snprintf(buf+len, sizeof(buf)-len,
+       len += snprintf(buf + len, sizeof(buf) - len,
                        "available txbuffers: %d\n", sc->txbuf_len);
 
        for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
                txq = &sc->txqs[i];
 
-               len += snprintf(buf+len, sizeof(buf)-len,
+               len += snprintf(buf + len, sizeof(buf) - len,
                        "%02d: %ssetup\n", i, txq->setup ? "" : "not ");
 
                if (!txq->setup)
@@ -845,9 +849,9 @@ static ssize_t read_file_queue(struct file *file, char __user *user_buf,
                        n++;
                spin_unlock_bh(&txq->lock);
 
-               len += snprintf(buf+len, sizeof(buf)-len,
+               len += snprintf(buf + len, sizeof(buf) - len,
                                "  len: %d bufs: %d\n", txq->txq_len, n);
-               len += snprintf(buf+len, sizeof(buf)-len,
+               len += snprintf(buf + len, sizeof(buf) - len,
                                "  stuck: %d\n", txq->txq_stuck);
        }
 
@@ -894,7 +898,7 @@ ath5k_debug_init_device(struct ath5k_softc *sc)
 
        phydir = debugfs_create_dir("ath5k", sc->hw->wiphy->debugfsdir);
        if (!phydir)
-           return;
+               return;
 
        debugfs_create_file("debug", S_IWUSR | S_IRUSR, phydir, sc,
                            &fops_debug);
index 21091c2..02e2e3f 100644 (file)
@@ -258,7 +258,7 @@ static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
                /* For 2413+ order PCU to drop packets using
                 * QUIET mechanism */
                if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) &&
-               pending){
+                   pending) {
                        /* Set periodicity and duration */
                        ath5k_hw_reg_write(ah,
                                AR5K_REG_SM(100, AR5K_QUIET_CTL2_QT_PER)|
index 392771f..f97a540 100644 (file)
@@ -223,14 +223,14 @@ static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
        ah->ah_ant_ctl[mode][AR5K_ANT_CTL] =
            (ee->ee_ant_control[mode][0] << 4);
        ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] =
-            ee->ee_ant_control[mode][1]        |
-           (ee->ee_ant_control[mode][2] << 6)  |
+            ee->ee_ant_control[mode][1]        |
+           (ee->ee_ant_control[mode][2] << 6)  |
            (ee->ee_ant_control[mode][3] << 12) |
            (ee->ee_ant_control[mode][4] << 18) |
            (ee->ee_ant_control[mode][5] << 24);
        ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] =
-            ee->ee_ant_control[mode][6]        |
-           (ee->ee_ant_control[mode][7] << 6)  |
+            ee->ee_ant_control[mode][6]        |
+           (ee->ee_ant_control[mode][7] << 6)  |
            (ee->ee_ant_control[mode][8] << 12) |
            (ee->ee_ant_control[mode][9] << 18) |
            (ee->ee_ant_control[mode][10] << 24);
@@ -255,7 +255,7 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
        ee->ee_n_piers[mode] = 0;
        AR5K_EEPROM_READ(o++, val);
        ee->ee_adc_desired_size[mode]   = (s8)((val >> 8) & 0xff);
-       switch(mode) {
+       switch (mode) {
        case AR5K_EEPROM_MODE_11A:
                ee->ee_ob[mode][3]      = (val >> 5) & 0x7;
                ee->ee_db[mode][3]      = (val >> 2) & 0x7;
@@ -349,7 +349,7 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
        /* Note: >= v5 have bg freq piers on another location
         * so these freq piers are ignored for >= v5 (should be 0xff
         * anyway) */
-       switch(mode) {
+       switch (mode) {
        case AR5K_EEPROM_MODE_11A:
                if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1)
                        break;
@@ -422,7 +422,7 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
        if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
                goto done;
 
-       switch (mode){
+       switch (mode) {
        case AR5K_EEPROM_MODE_11A:
                ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
 
@@ -436,7 +436,7 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
                ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
                ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
 
-               if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2)
+               if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >= 2)
                        ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
                break;
        case AR5K_EEPROM_MODE_11G:
@@ -516,7 +516,7 @@ ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max,
        u16 val;
 
        ee->ee_n_piers[mode] = 0;
-       while(i < max) {
+       while (i < max) {
                AR5K_EEPROM_READ(o++, val);
 
                freq1 = val & 0xff;
@@ -602,7 +602,7 @@ ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
        struct ath5k_chan_pcal_info *pcal;
 
-       switch(mode) {
+       switch (mode) {
        case AR5K_EEPROM_MODE_11B:
                pcal = ee->ee_pwr_cal_b;
                break;
@@ -644,10 +644,12 @@ ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
 static inline void
 ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
 {
-       static const u16 intercepts3[] =
-               { 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
-       static const u16 intercepts3_2[] =
-               { 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
+       static const u16 intercepts3[] = {
+               0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100
+       };
+       static const u16 intercepts3_2[] = {
+               0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100
+       };
        const u16 *ip;
        int i;
 
@@ -796,7 +798,7 @@ ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
        u16 val;
 
        offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
-       switch(mode) {
+       switch (mode) {
        case AR5K_EEPROM_MODE_11A:
                if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
                        return 0;
@@ -1163,7 +1165,7 @@ ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
 {
        u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
 
-       switch(mode) {
+       switch (mode) {
        case AR5K_EEPROM_MODE_11G:
                if (AR5K_EEPROM_HDR_11B(ee->ee_header))
                        offset += ath5k_pdgains_size_2413(ee,
@@ -1620,8 +1622,8 @@ ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
                offset += AR5K_EEPROM_GROUPS_START(ee->ee_version);
 
        rep = ee->ee_ctl_pwr;
-       for(i = 0; i < ee->ee_ctls; i++) {
-               switch(ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
+       for (i = 0; i < ee->ee_ctls; i++) {
+               switch (ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
                case AR5K_CTL_11A:
                case AR5K_CTL_TURBO:
                        ctl_mode = AR5K_EEPROM_MODE_11A;
index 6511c27..6d440e0 100644 (file)
 #define AR5K_EEPROM_CCK_OFDM_DELTA     15
 #define AR5K_EEPROM_N_IQ_CAL           2
 /* 5GHz/2GHz */
-enum ath5k_eeprom_freq_bands{
+enum ath5k_eeprom_freq_bands {
        AR5K_EEPROM_BAND_5GHZ = 0,
        AR5K_EEPROM_BAND_2GHZ = 1,
        AR5K_EEPROM_N_FREQ_BANDS,
index e49340d..4bfdc2e 100644 (file)
@@ -113,8 +113,8 @@ static const struct ath5k_ini ar5210_ini[] = {
        { AR5K_PHY(28), 0x0000000f },
        { AR5K_PHY(29), 0x00000080 },
        { AR5K_PHY(30), 0x00000004 },
-       { AR5K_PHY(31), 0x00000018 },   /* 0x987c */
-       { AR5K_PHY(64), 0x00000000 },   /* 0x9900 */
+       { AR5K_PHY(31), 0x00000018 },   /* 0x987c */
+       { AR5K_PHY(64), 0x00000000 },   /* 0x9900 */
        { AR5K_PHY(65), 0x00000000 },
        { AR5K_PHY(66), 0x00000000 },
        { AR5K_PHY(67), 0x00800000 },
@@ -549,7 +549,7 @@ static const struct ath5k_ini ar5212_ini_common_start[] = {
        { AR5K_DIAG_SW_5211,    0x00000000 },
        { AR5K_ADDAC_TEST,      0x00000000 },
        { AR5K_DEFAULT_ANTENNA, 0x00000000 },
-       { AR5K_FRAME_CTL_QOSM,  0x000fc78f },
+       { AR5K_FRAME_CTL_QOSM,  0x000fc78f },
        { AR5K_XRMODE,          0x2a82301a },
        { AR5K_XRDELAY,         0x05dc01e0 },
        { AR5K_XRTIMEOUT,       0x1f402710 },
@@ -760,9 +760,9 @@ static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
 
 static const struct ath5k_ini rf5111_ini_common_end[] = {
        { AR5K_DCU_FP,          0x00000000 },
-       { AR5K_PHY_AGC,         0x00000000 },
-       { AR5K_PHY_ADC_CTL,     0x00022ffe },
-       { 0x983c,               0x00020100 },
+       { AR5K_PHY_AGC,         0x00000000 },
+       { AR5K_PHY_ADC_CTL,     0x00022ffe },
+       { 0x983c,               0x00020100 },
        { AR5K_PHY_GAIN_OFFSET, 0x1284613c },
        { AR5K_PHY_PAPD_PROBE,  0x00004883 },
        { 0x9940,               0x00000004 },
index 576edf2..127bfbd 100644 (file)
 #include "ath5k.h"
 #include "base.h"
 
-#define ATH_SDEVICE(subv,subd) \
+#define ATH_SDEVICE(subv, subd) \
        .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
        .subvendor = (subv), .subdevice = (subd)
 
-#define ATH_LED(pin,polarity) .driver_data = (((pin) << 8) | (polarity))
+#define ATH_LED(pin, polarity) .driver_data = (((pin) << 8) | (polarity))
 #define ATH_PIN(data) ((data) >> 8)
 #define ATH_POLARITY(data) ((data) & 0xff)
 
 /* Devices we match on for LED config info (typically laptops) */
-static const struct pci_device_id ath5k_led_devices[] = {
+static DEFINE_PCI_DEVICE_TABLE(ath5k_led_devices) = {
        /* AR5211 */
        { PCI_VDEVICE(ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5211), ATH_LED(0, 0) },
        /* HP Compaq nc6xx, nc4000, nx6000 */
@@ -157,7 +157,7 @@ void ath5k_unregister_leds(struct ath5k_softc *sc)
        ath5k_unregister_led(&sc->tx_led);
 }
 
-int ath5k_init_leds(struct ath5k_softc *sc)
+int __devinit ath5k_init_leds(struct ath5k_softc *sc)
 {
        int ret = 0;
        struct ieee80211_hw *hw = sc->hw;
index 807bd64..4939082 100644 (file)
@@ -46,8 +46,6 @@
 #include "base.h"
 #include "reg.h"
 
-extern int ath5k_modparam_nohwcrypt;
-
 /********************\
 * Mac80211 functions *
 \********************/
@@ -296,10 +294,10 @@ ath5k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
                if (bss_conf->assoc)
                        sc->assoc = bss_conf->assoc;
                else
-                       sc->assoc = ath_any_vif_assoc(sc);
+                       sc->assoc = ath5k_any_vif_assoc(sc);
 
                if (sc->opmode == NL80211_IFTYPE_STATION)
-                       set_beacon_filter(hw, sc->assoc);
+                       ath5k_set_beacon_filter(hw, sc->assoc);
                ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
                        AR5K_LED_ASSOC : AR5K_LED_INIT);
                if (bss_conf->assoc) {
index f2c0c23..cd60f0a 100644 (file)
@@ -234,7 +234,7 @@ ath5k_pci_probe(struct pci_dev *pdev,
 
        mem = pci_iomap(pdev, 0, 0);
        if (!mem) {
-               dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
+               dev_err(&pdev->dev, "cannot remap PCI memory region\n");
                ret = -EIO;
                goto err_reg;
        }
index 712a9ac..aecd724 100644 (file)
@@ -534,9 +534,9 @@ u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
 
        local_irq_restore(flags);
 
-       WARN_ON( i == ATH5K_MAX_TSF_READ );
+       WARN_ON(i == ATH5K_MAX_TSF_READ);
 
-       return (((u64)tsf_upper1 << 32) | tsf_lower);
+       return ((u64)tsf_upper1 << 32) | tsf_lower;
 }
 
 /**
index 5544191..7e28676 100644 (file)
@@ -173,7 +173,7 @@ static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
                data = ath5k_hw_bitswap(val, num_bits);
 
        for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
-       position = 0, entry++) {
+            position = 0, entry++) {
 
                last_bit = (position + bits_left > 8) ? 8 :
                                        position + bits_left;
@@ -472,7 +472,7 @@ static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
                level[0] = 0;
                level[1] = (step == 63) ? 50 : step + 4;
                level[2] = (step != 63) ? 64 : level[0];
-               level[3] = level[2] + 50 ;
+               level[3] = level[2] + 50;
 
                ah->ah_gain.g_high = level[3] -
                        (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
@@ -549,7 +549,7 @@ static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
 
                for (ah->ah_gain.g_target = ah->ah_gain.g_current;
                                ah->ah_gain.g_target <= ah->ah_gain.g_low &&
-                               ah->ah_gain.g_step_idx < go->go_steps_count-1;
+                               ah->ah_gain.g_step_idx < go->go_steps_count - 1;
                                g_step = &go->go_step[ah->ah_gain.g_step_idx])
                        ah->ah_gain.g_target -= 2 *
                            (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
@@ -614,7 +614,7 @@ enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
                        ath5k_hw_rf_gainf_corr(ah);
                        ah->ah_gain.g_current =
                                ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
-                               (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
+                               (ah->ah_gain.g_current - ah->ah_gain.g_f_corr) :
                                0;
                }
 
@@ -1331,7 +1331,7 @@ void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
 {
        struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
-       hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1);
+       hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX - 1);
        hist->nfval[hist->index] = noise_floor;
 }
 
@@ -1344,10 +1344,10 @@ static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
        memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
        for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
                for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
-                       if (sort[j] > sort[j-1]) {
+                       if (sort[j] > sort[j - 1]) {
                                tmp = sort[j];
-                               sort[j] = sort[j-1];
-                               sort[j-1] = tmp;
+                               sort[j] = sort[j - 1];
+                               sort[j - 1] = tmp;
                        }
                }
        }
@@ -1355,7 +1355,7 @@ static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
                ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
                        "cal %d:%d\n", i, sort[i]);
        }
-       return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2];
+       return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2];
 }
 
 /*
@@ -2080,7 +2080,7 @@ ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
         * always 1 instead of 1.25, 1.75 etc). We scale up by 100
         * to have some accuracy both for 0.5 and 0.25 steps.
         */
-       ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
+       ratio = ((100 * y_right - 100 * y_left) / (x_right - x_left));
 
        /* Now scale down to be in range */
        result = y_left + (ratio * (target - x_left) / 100);
@@ -2159,7 +2159,7 @@ ath5k_create_power_curve(s16 pmin, s16 pmax,
                        u8 *vpd_table, u8 type)
 {
        u8 idx[2] = { 0, 1 };
-       s16 pwr_i = 2*pmin;
+       s16 pwr_i = 2 * pmin;
        int i;
 
        if (num_points < 2)
@@ -2437,7 +2437,7 @@ ath5k_get_max_ctl_power(struct ath5k_hw *ah,
        }
 
        if (edge_pwr)
-               ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
+               ah->ah_txpower.txp_max_pwr = 4 * min(edge_pwr, max_chan_pwr);
 }
 
 
@@ -2456,7 +2456,7 @@ static void
 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
                                                        s16 *table_max)
 {
-       u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
+       u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
        u8      *pcdac_tmp = ah->ah_txpower.tmpL[0];
        u8      pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
        s16     min_pwr, max_pwr;
@@ -2475,8 +2475,8 @@ ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
 
        /* Copy values from pcdac_tmp */
        pwr_idx = min_pwr;
-       for (i = 0 ; pwr_idx <= max_pwr &&
-       pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
+       for (i = 0; pwr_idx <= max_pwr &&
+                   pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
                pcdac_out[pcdac_i++] = pcdac_tmp[i];
                pwr_idx++;
        }
@@ -2502,7 +2502,7 @@ static void
 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
                                                s16 *table_max, u8 pdcurves)
 {
-       u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
+       u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
        u8      *pcdac_low_pwr;
        u8      *pcdac_high_pwr;
        u8      *pcdac_tmp;
@@ -2552,7 +2552,7 @@ ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
        }
 
        /* This is used when setting tx power*/
-       ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
+       ah->ah_txpower.txp_min_idx = min_pwr_idx / 2;
 
        /* Fill Power to PCDAC table backwards */
        pwr = max_pwr_idx;
@@ -2561,10 +2561,10 @@ ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
                 * edge flag and set pcdac_tmp to lower
                 * power curve.*/
                if (edge_flag == 0x40 &&
-               (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
+               (2 * pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
                        edge_flag = 0x00;
                        pcdac_tmp = pcdac_low_pwr;
-                       pwr = mid_pwr_idx/2;
+                       pwr = mid_pwr_idx / 2;
                }
 
                /* Don't go below 1, extrapolate below if we have
@@ -2596,7 +2596,7 @@ ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
 static void
 ath5k_write_pcdac_table(struct ath5k_hw *ah)
 {
-       u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
+       u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
        int     i;
 
        /*
@@ -2604,8 +2604,8 @@ ath5k_write_pcdac_table(struct ath5k_hw *ah)
         */
        for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
                ath5k_hw_reg_write(ah,
-                       (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
-                       (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
+                       (((pcdac_out[2 * i + 0] << 8 | 0xff) & 0xffff) << 0) |
+                       (((pcdac_out[2 * i + 1] << 8 | 0xff) & 0xffff) << 16),
                        AR5K_PHY_PCDAC_TXPOWER(i));
        }
 }
@@ -2789,10 +2789,10 @@ ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
         */
        for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
                ath5k_hw_reg_write(ah,
-                       ((pdadc_out[4*i + 0] & 0xff) << 0) |
-                       ((pdadc_out[4*i + 1] & 0xff) << 8) |
-                       ((pdadc_out[4*i + 2] & 0xff) << 16) |
-                       ((pdadc_out[4*i + 3] & 0xff) << 24),
+                       ((pdadc_out[4 * i + 0] & 0xff) << 0) |
+                       ((pdadc_out[4 * i + 1] & 0xff) << 8) |
+                       ((pdadc_out[4 * i + 2] & 0xff) << 16) |
+                       ((pdadc_out[4 * i + 3] & 0xff) << 24),
                        AR5K_PHY_PDADC_TXPOWER(i));
        }
 }
index d12b827..994d29a 100644 (file)
@@ -72,7 +72,7 @@
 #define        AR5K_CFG_SWRD           0x00000004      /* Byte-swap RX descriptor */
 #define        AR5K_CFG_SWRB           0x00000008      /* Byte-swap RX buffer */
 #define        AR5K_CFG_SWRG           0x00000010      /* Byte-swap Register access */
-#define AR5K_CFG_IBSS          0x00000020      /* 0-BSS, 1-IBSS [5211+] */
+#define AR5K_CFG_IBSS          0x00000020      /* 0-BSS, 1-IBSS [5211+] */
 #define AR5K_CFG_PHY_OK                0x00000100      /* [5211+] */
 #define AR5K_CFG_EEBS          0x00000200      /* EEPROM is busy */
 #define        AR5K_CFG_CLKGD          0x00000400      /* Clock gated (Disable dynamic clock) */
 #define AR5K_ISR_BRSSI         0x00020000      /* Beacon rssi below threshold (?) */
 #define AR5K_ISR_BMISS         0x00040000      /* Beacon missed */
 #define AR5K_ISR_HIUERR                0x00080000      /* Host Interface Unit error [5211+] */
-#define AR5K_ISR_BNR           0x00100000      /* Beacon not ready [5211+] */
+#define AR5K_ISR_BNR           0x00100000      /* Beacon not ready [5211+] */
 #define AR5K_ISR_MCABT         0x00100000      /* Master Cycle Abort [5210] */
 #define AR5K_ISR_RXCHIRP       0x00200000      /* CHIRP Received [5212+] */
 #define AR5K_ISR_SSERR         0x00200000      /* Signaled System Error [5210] */
 #define AR5K_IMR_BRSSI         0x00020000      /* Beacon rssi below threshold (?) */
 #define AR5K_IMR_BMISS         0x00040000      /* Beacon missed*/
 #define AR5K_IMR_HIUERR                0x00080000      /* Host Interface Unit error [5211+] */
-#define AR5K_IMR_BNR           0x00100000      /* Beacon not ready [5211+] */
+#define AR5K_IMR_BNR           0x00100000      /* Beacon not ready [5211+] */
 #define AR5K_IMR_MCABT         0x00100000      /* Master Cycle Abort [5210] */
 #define AR5K_IMR_RXCHIRP       0x00200000      /* CHIRP Received [5212+]*/
 #define AR5K_IMR_SSERR         0x00200000      /* Signaled System Error [5210] */
 #define AR5K_RX_FILTER_5211    0x803c                  /* Register Address [5211+] */
 #define AR5K_RX_FILTER         (ah->ah_version == AR5K_AR5210 ? \
                                AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211)
-#define        AR5K_RX_FILTER_UCAST    0x00000001      /* Don't filter unicast frames */
-#define        AR5K_RX_FILTER_MCAST    0x00000002      /* Don't filter multicast frames */
-#define        AR5K_RX_FILTER_BCAST    0x00000004      /* Don't filter broadcast frames */
-#define        AR5K_RX_FILTER_CONTROL  0x00000008      /* Don't filter control frames */
-#define        AR5K_RX_FILTER_BEACON   0x00000010      /* Don't filter beacon frames */
-#define        AR5K_RX_FILTER_PROM     0x00000020      /* Set promiscuous mode */
-#define        AR5K_RX_FILTER_XRPOLL   0x00000040      /* Don't filter XR poll frame [5212+] */
+#define        AR5K_RX_FILTER_UCAST    0x00000001      /* Don't filter unicast frames */
+#define        AR5K_RX_FILTER_MCAST    0x00000002      /* Don't filter multicast frames */
+#define        AR5K_RX_FILTER_BCAST    0x00000004      /* Don't filter broadcast frames */
+#define        AR5K_RX_FILTER_CONTROL  0x00000008      /* Don't filter control frames */
+#define        AR5K_RX_FILTER_BEACON   0x00000010      /* Don't filter beacon frames */
+#define        AR5K_RX_FILTER_PROM     0x00000020      /* Set promiscuous mode */
+#define        AR5K_RX_FILTER_XRPOLL   0x00000040      /* Don't filter XR poll frame [5212+] */
 #define        AR5K_RX_FILTER_PROBEREQ 0x00000080      /* Don't filter probe requests [5212+] */
 #define        AR5K_RX_FILTER_PHYERR_5212      0x00000100      /* Don't filter phy errors [5212+] */
-#define        AR5K_RX_FILTER_RADARERR_5212    0x00000200      /* Don't filter phy radar errors [5212+] */
+#define        AR5K_RX_FILTER_RADARERR_5212    0x00000200      /* Don't filter phy radar errors [5212+] */
 #define AR5K_RX_FILTER_PHYERR_5211     0x00000040      /* [5211] */
 #define AR5K_RX_FILTER_RADARERR_5211   0x00000080      /* [5211] */
 #define AR5K_RX_FILTER_PHYERR  \
  * ADDAC test register [5211+]
  */
 #define AR5K_ADDAC_TEST                        0x8054                  /* Register Address */
-#define AR5K_ADDAC_TEST_TXCONT                 0x00000001      /* Test continuous tx */
+#define AR5K_ADDAC_TEST_TXCONT         0x00000001      /* Test continuous tx */
 #define AR5K_ADDAC_TEST_TST_MODE       0x00000002      /* Test mode */
 #define AR5K_ADDAC_TEST_LOOP_EN                0x00000004      /* Enable loop */
 #define AR5K_ADDAC_TEST_LOOP_LEN       0x00000008      /* Loop length (field) */
 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S       24
 
 /* Low thresholds */
-#define AR5K_PHY_WEAK_OFDM_LOW_THR             0x986c
+#define AR5K_PHY_WEAK_OFDM_LOW_THR             0x986c
 #define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN  0x00000001
 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT    0x00003f00
 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S  8
 #define        AR5K_PHY_FRAME_CTL_ILLLEN_ERR   0x08000000      /* Illegal length */
 #define        AR5K_PHY_FRAME_CTL_SERVICE_ERR  0x20000000
 #define        AR5K_PHY_FRAME_CTL_TXURN_ERR    0x40000000      /* TX underrun */
-#define AR5K_PHY_FRAME_CTL_INI         AR5K_PHY_FRAME_CTL_SERVICE_ERR | \
-                       AR5K_PHY_FRAME_CTL_TXURN_ERR | \
-                       AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \
-                       AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \
-                       AR5K_PHY_FRAME_CTL_PARITY_ERR | \
-                       AR5K_PHY_FRAME_CTL_TIMING_ERR
+#define AR5K_PHY_FRAME_CTL_INI \
+                       (AR5K_PHY_FRAME_CTL_SERVICE_ERR | \
+                        AR5K_PHY_FRAME_CTL_TXURN_ERR | \
+                        AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \
+                        AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \
+                        AR5K_PHY_FRAME_CTL_PARITY_ERR | \
+                        AR5K_PHY_FRAME_CTL_TIMING_ERR)
 
 /*
  * PHY Tx Power adjustment register [5212A+]
 #define        AR5K_PHY_RADAR                  0x9954
 #define        AR5K_PHY_RADAR_ENABLE           0x00000001
 #define        AR5K_PHY_RADAR_DISABLE          0x00000000
-#define AR5K_PHY_RADAR_INBANDTHR       0x0000003e      /* Inband threshold
+#define AR5K_PHY_RADAR_INBANDTHR       0x0000003e      /* Inband threshold
                                                        5-bits, units unknown {0..31}
                                                        (? MHz ?) */
 #define AR5K_PHY_RADAR_INBANDTHR_S     1
 
-#define AR5K_PHY_RADAR_PRSSI_THR       0x00000fc0      /* Pulse RSSI/SNR threshold
+#define AR5K_PHY_RADAR_PRSSI_THR       0x00000fc0      /* Pulse RSSI/SNR threshold
                                                        6-bits, dBm range {0..63}
                                                        in dBm units. */
 #define AR5K_PHY_RADAR_PRSSI_THR_S     6
 
-#define AR5K_PHY_RADAR_PHEIGHT_THR     0x0003f000      /* Pulse height threshold
+#define AR5K_PHY_RADAR_PHEIGHT_THR     0x0003f000      /* Pulse height threshold
                                                        6-bits, dBm range {0..63}
                                                        in dBm units. */
 #define AR5K_PHY_RADAR_PHEIGHT_THR_S   12
 
-#define AR5K_PHY_RADAR_RSSI_THR        0x00fc0000      /* Radar RSSI/SNR threshold.
+#define AR5K_PHY_RADAR_RSSI_THR                0x00fc0000      /* Radar RSSI/SNR threshold.
                                                        6-bits, dBm range {0..63}
                                                        in dBm units. */
 #define AR5K_PHY_RADAR_RSSI_THR_S      18
index 126a4ea..19aefdb 100644 (file)
@@ -25,7 +25,7 @@
 
 #include <asm/unaligned.h>
 
-#include <linux/pci.h>                 /* To determine if a card is pci-e */
+#include <linux/pci.h>         /* To determine if a card is pci-e */
 #include <linux/log2.h>
 #include <linux/platform_device.h>
 #include "ath5k.h"
@@ -142,10 +142,10 @@ static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
 
        /* Set 32MHz USEC counter */
        if ((ah->ah_radio == AR5K_RF5112) ||
-               (ah->ah_radio == AR5K_RF5413) ||
-               (ah->ah_radio == AR5K_RF2316) ||
-               (ah->ah_radio == AR5K_RF2317))
-       /* Remain on 40MHz clock ? */
+           (ah->ah_radio == AR5K_RF5413) ||
+           (ah->ah_radio == AR5K_RF2316) ||
+           (ah->ah_radio == AR5K_RF2317))
+               /* Remain on 40MHz clock ? */
                sclock = 40 - 1;
        else
                sclock = 32 - 1;
@@ -375,19 +375,19 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
 static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
 {
        u32 mask = flags ? flags : ~0U;
-       volatile u32 *reg;
+       u32 __iomem *reg;
        u32 regval;
        u32 val = 0;
 
        /* ah->ah_mac_srev is not available at this point yet */
        if (ah->ah_sc->devid >= AR5K_SREV_AR2315_R6) {
-               reg = (u32 *) AR5K_AR2315_RESET;
+               reg = (u32 __iomem *) AR5K_AR2315_RESET;
                if (mask & AR5K_RESET_CTL_PCU)
                        val |= AR5K_AR2315_RESET_WMAC;
                if (mask & AR5K_RESET_CTL_BASEBAND)
                        val |= AR5K_AR2315_RESET_BB_WARM;
        } else {
-               reg = (u32 *) AR5K_AR5312_RESET;
+               reg = (u32 __iomem *) AR5K_AR5312_RESET;
                if (to_platform_device(ah->ah_sc->dev)->id == 0) {
                        if (mask & AR5K_RESET_CTL_PCU)
                                val |= AR5K_AR5312_RESET_WMAC0;
index 16b67e8..5d11c23 100644 (file)
@@ -254,7 +254,7 @@ static const struct ath5k_ini_rfbuffer rfb_5111[] = {
 
 /* RFX112 (Derby 1) */
 
-/* BANK 6                              len  pos col */
+/* BANK 6                              len  pos col */
 #define        AR5K_RF5112_OB_2GHZ             { 3, 269, 0 }
 #define        AR5K_RF5112_DB_2GHZ             { 3, 272, 0 }
 
@@ -495,7 +495,7 @@ static const struct ath5k_ini_rfbuffer rfb_5112a[] = {
 /* BANK 2                              len  pos col */
 #define AR5K_RF2413_RF_TURBO           { 1, 1,   2 }
 
-/* BANK 6                              len  pos col */
+/* BANK 6                              len  pos col */
 #define        AR5K_RF2413_OB_2GHZ             { 3, 168, 0 }
 #define        AR5K_RF2413_DB_2GHZ             { 3, 165, 0 }
 
index 1354d8c..70c9a45 100644 (file)
@@ -452,7 +452,7 @@ static const struct ath5k_ini_rfgain rfgain_2425[] = {
 
 /* Check if our current measurement is inside our
  * current variable attenuation window */
-#define AR5K_GAIN_CHECK_ADJUST(_g)             \
+#define AR5K_GAIN_CHECK_ADJUST(_g)             \
        ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high)
 
 struct ath5k_gain_opt_step {
index a073cdc..d8ad0e4 100644 (file)
@@ -12,7 +12,7 @@ static ssize_t ath5k_attr_show_##name(struct device *dev,             \
 {                                                                      \
        struct ieee80211_hw *hw = dev_get_drvdata(dev);                 \
        struct ath5k_softc *sc = hw->priv;                              \
-       return snprintf(buf, PAGE_SIZE, "%d\n", get);                   \
+       return snprintf(buf, PAGE_SIZE, "%d\n", get);                   \
 }                                                                      \
                                                                        \
 static ssize_t ath5k_attr_store_##name(struct device *dev,             \
@@ -21,9 +21,11 @@ static ssize_t ath5k_attr_store_##name(struct device *dev,           \
 {                                                                      \
        struct ieee80211_hw *hw = dev_get_drvdata(dev);                 \
        struct ath5k_softc *sc = hw->priv;                              \
-       int val;                                                        \
+       int val, ret;                                                   \
                                                                        \
-       val = (int)simple_strtoul(buf, NULL, 10);                       \
+       ret = kstrtoint(buf, 10, &val);                                 \
+       if (ret < 0)                                                    \
+               return ret;                                             \
        set(sc->ah, val);                                               \
        return count;                                                   \
 }                                                                      \
@@ -37,7 +39,7 @@ static ssize_t ath5k_attr_show_##name(struct device *dev,             \
 {                                                                      \
        struct ieee80211_hw *hw = dev_get_drvdata(dev);                 \
        struct ath5k_softc *sc = hw->priv;                              \
-       return snprintf(buf, PAGE_SIZE, "%d\n", get);                   \
+       return snprintf(buf, PAGE_SIZE, "%d\n", get);                   \
 }                                                                      \
 static DEVICE_ATTR(name, S_IRUGO, ath5k_attr_show_##name, NULL)
 
index 2de68ad..235e076 100644 (file)
@@ -12,9 +12,6 @@ static inline void trace_ ## name(proto) {}
 
 struct sk_buff;
 
-#define PRIV_ENTRY  __field(struct ath5k_softc *, priv)
-#define PRIV_ASSIGN __entry->priv = priv
-
 #undef TRACE_SYSTEM
 #define TRACE_SYSTEM ath5k
 
@@ -22,12 +19,12 @@ TRACE_EVENT(ath5k_rx,
        TP_PROTO(struct ath5k_softc *priv, struct sk_buff *skb),
        TP_ARGS(priv, skb),
        TP_STRUCT__entry(
-               PRIV_ENTRY
+               __field(struct ath5k_softc *, priv)
                __field(unsigned long, skbaddr)
                __dynamic_array(u8, frame, skb->len)
        ),
        TP_fast_assign(
-               PRIV_ASSIGN;
+               __entry->priv = priv;
                __entry->skbaddr = (unsigned long) skb;
                memcpy(__get_dynamic_array(frame), skb->data, skb->len);
        ),
@@ -43,14 +40,14 @@ TRACE_EVENT(ath5k_tx,
        TP_ARGS(priv, skb, q),
 
        TP_STRUCT__entry(
-               PRIV_ENTRY
+               __field(struct ath5k_softc *, priv)
                __field(unsigned long, skbaddr)
                __field(u8, qnum)
                __dynamic_array(u8, frame, skb->len)
        ),
 
        TP_fast_assign(
-               PRIV_ASSIGN;
+               __entry->priv = priv;
                __entry->skbaddr = (unsigned long) skb;
                __entry->qnum = (u8) q->qnum;
                memcpy(__get_dynamic_array(frame), skb->data, skb->len);
@@ -69,7 +66,7 @@ TRACE_EVENT(ath5k_tx_complete,
        TP_ARGS(priv, skb, q, ts),
 
        TP_STRUCT__entry(
-               PRIV_ENTRY
+               __field(struct ath5k_softc *, priv)
                __field(unsigned long, skbaddr)
                __field(u8, qnum)
                __field(u8, ts_status)
@@ -78,7 +75,7 @@ TRACE_EVENT(ath5k_tx_complete,
        ),
 
        TP_fast_assign(
-               PRIV_ASSIGN;
+               __entry->priv = priv;
                __entry->skbaddr = (unsigned long) skb;
                __entry->qnum = (u8) q->qnum;
                __entry->ts_status = ts->ts_status;
index 5b49cd0..0b36fcf 100644 (file)
@@ -27,6 +27,10 @@ static const struct platform_device_id ath9k_platform_id_table[] = {
                .driver_data = AR5416_AR9100_DEVID,
        },
        {
+               .name = "ar933x_wmac",
+               .driver_data = AR9300_DEVID_AR9330,
+       },
+       {
                .name = "ar934x_wmac",
                .driver_data = AR9300_DEVID_AR9340,
        },
index 077e8a6..45b262f 100644 (file)
@@ -28,11 +28,6 @@ static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
        ((struct ath_desc*) ds)->ds_link = ds_link;
 }
 
-static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
-{
-       *ds_link = &((struct ath_desc *)ds)->ds_link;
-}
-
 static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
 {
        u32 isr = 0;
@@ -437,7 +432,6 @@ void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
 
        ops->rx_enable = ar9002_hw_rx_enable;
        ops->set_desc_link = ar9002_hw_set_desc_link;
-       ops->get_desc_link = ar9002_hw_get_desc_link;
        ops->get_isr = ar9002_hw_get_isr;
        ops->fill_txdesc = ar9002_hw_fill_txdesc;
        ops->proc_txdesc = ar9002_hw_proc_txdesc;
index e8ac70d..2339728 100644 (file)
@@ -653,8 +653,8 @@ static const u32 ar9300_2p2_baseband_postamble[][5] = {
        {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
        {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
        {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
-       {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982},
-       {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
+       {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982},
+       {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
        {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
        {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
        {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000},
@@ -761,7 +761,7 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
        {0x0000a3ec, 0x20202020},
        {0x0000a3f0, 0x00000000},
        {0x0000a3f4, 0x00000246},
-       {0x0000a3f8, 0x0cdbd380},
+       {0x0000a3f8, 0x0c9bd380},
        {0x0000a3fc, 0x000f0f01},
        {0x0000a400, 0x8fa91f01},
        {0x0000a404, 0x00000000},
@@ -780,7 +780,7 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
        {0x0000a43c, 0x00100000},
        {0x0000a440, 0x00000000},
        {0x0000a444, 0x00000000},
-       {0x0000a448, 0x06000080},
+       {0x0000a448, 0x05000080},
        {0x0000a44c, 0x00000001},
        {0x0000a450, 0x00010000},
        {0x0000a458, 0x00000000},
@@ -1500,8 +1500,6 @@ static const u32 ar9300_2p2_mac_core[][2] = {
        {0x0000816c, 0x00000000},
        {0x000081c0, 0x00000000},
        {0x000081c4, 0x33332210},
-       {0x000081c8, 0x00000000},
-       {0x000081cc, 0x00000000},
        {0x000081ec, 0x00000000},
        {0x000081f0, 0x00000000},
        {0x000081f4, 0x00000000},
index ff8150e..1d09f22 100644 (file)
@@ -1461,7 +1461,7 @@ static const struct ar9300_eeprom ar9300_h112 = {
                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
                { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 
-               { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+               { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 
@@ -2616,7 +2616,7 @@ static const struct ar9300_eeprom ar9300_h116 = {
                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 
-                { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 
@@ -3324,6 +3324,8 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
        read = ar9300_read_eeprom;
        if (AR_SREV_9485(ah))
                cptr = AR9300_BASE_ADDR_4K;
+       else if (AR_SREV_9330(ah))
+               cptr = AR9300_BASE_ADDR_512;
        else
                cptr = AR9300_BASE_ADDR;
        ath_dbg(common, ATH_DBG_EEPROM,
@@ -3442,7 +3444,7 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
 {
        int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
 
-       if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
+       if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
                REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
        else {
                REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
@@ -3523,7 +3525,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
                }
        }
 
-       if (AR_SREV_9485(ah)) {
+       if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
                value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
                /*
                 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
@@ -3710,7 +3712,7 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
                ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
 
        if (internal_regulator) {
-               if (AR_SREV_9485(ah)) {
+               if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
                        int reg_pmu_set;
 
                        reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
@@ -3718,9 +3720,24 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
                        if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
                                return;
 
-                       reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
-                                     (2 << 14) | (6 << 17) | (1 << 20) |
-                                     (3 << 24) | (1 << 28);
+                       if (AR_SREV_9330(ah)) {
+                               if (ah->is_clk_25mhz) {
+                                       reg_pmu_set = (3 << 1) | (8 << 4) |
+                                                     (3 << 8) | (1 << 14) |
+                                                     (6 << 17) | (1 << 20) |
+                                                     (3 << 24);
+                               } else {
+                                       reg_pmu_set = (4 << 1)  | (7 << 4) |
+                                                     (3 << 8)  | (1 << 14) |
+                                                     (6 << 17) | (1 << 20) |
+                                                     (3 << 24);
+                               }
+                       } else {
+                               reg_pmu_set = (5 << 1) | (7 << 4) |
+                                             (1 << 8) | (2 << 14) |
+                                             (6 << 17) | (1 << 20) |
+                                             (3 << 24) | (1 << 28);
+                       }
 
                        REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
                        if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
@@ -3751,7 +3768,7 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
                                           AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
                }
        } else {
-               if (AR_SREV_9485(ah)) {
+               if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
                        REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
                        while (REG_READ_FIELD(ah, AR_PHY_PMU2,
                                              AR_PHY_PMU2_PGM))
@@ -3795,9 +3812,9 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
        ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
        ar9003_hw_drive_strength_apply(ah);
        ar9003_hw_atten_apply(ah, chan);
-       if (!AR_SREV_9340(ah))
+       if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
                ar9003_hw_internal_regulator_apply(ah);
-       if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
+       if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
                ar9003_hw_apply_tuning_caps(ah);
 }
 
index 392bf0f..8efdec2 100644 (file)
@@ -19,6 +19,8 @@
 #include "ar9003_2p2_initvals.h"
 #include "ar9485_initvals.h"
 #include "ar9340_initvals.h"
+#include "ar9330_1p1_initvals.h"
+#include "ar9330_1p2_initvals.h"
 
 /* General hardware code for the AR9003 hadware family */
 
  */
 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
 {
-       if (AR_SREV_9340(ah)) {
+       if (AR_SREV_9330_11(ah)) {
+               /* mac */
+               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+                               ar9331_1p1_mac_core,
+                               ARRAY_SIZE(ar9331_1p1_mac_core), 2);
+               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+                               ar9331_1p1_mac_postamble,
+                               ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
+
+               /* bb */
+               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+                               ar9331_1p1_baseband_core,
+                               ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
+               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+                               ar9331_1p1_baseband_postamble,
+                               ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
+
+               /* radio */
+               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+                               ar9331_1p1_radio_core,
+                               ARRAY_SIZE(ar9331_1p1_radio_core), 2);
+               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
+
+               /* soc */
+               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+                               ar9331_1p1_soc_preamble,
+                               ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
+               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+                               ar9331_1p1_soc_postamble,
+                               ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
+
+               /* rx/tx gain */
+               INIT_INI_ARRAY(&ah->iniModesRxGain,
+                               ar9331_common_rx_gain_1p1,
+                               ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
+               INIT_INI_ARRAY(&ah->iniModesTxGain,
+                       ar9331_modes_lowest_ob_db_tx_gain_1p1,
+                       ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
+                       5);
+
+               /* additional clock settings */
+               if (ah->is_clk_25mhz)
+                       INIT_INI_ARRAY(&ah->iniModesAdditional,
+                                       ar9331_1p1_xtal_25M,
+                                       ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
+               else
+                       INIT_INI_ARRAY(&ah->iniModesAdditional,
+                                       ar9331_1p1_xtal_40M,
+                                       ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
+       } else if (AR_SREV_9330_12(ah)) {
+               /* mac */
+               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+                               ar9331_1p2_mac_core,
+                               ARRAY_SIZE(ar9331_1p2_mac_core), 2);
+               INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+                               ar9331_1p2_mac_postamble,
+                               ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
+
+               /* bb */
+               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+                               ar9331_1p2_baseband_core,
+                               ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
+               INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+                               ar9331_1p2_baseband_postamble,
+                               ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
+
+               /* radio */
+               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+                               ar9331_1p2_radio_core,
+                               ARRAY_SIZE(ar9331_1p2_radio_core), 2);
+               INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
+
+               /* soc */
+               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+                               ar9331_1p2_soc_preamble,
+                               ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
+               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+               INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+                               ar9331_1p2_soc_postamble,
+                               ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
+
+               /* rx/tx gain */
+               INIT_INI_ARRAY(&ah->iniModesRxGain,
+                               ar9331_common_rx_gain_1p2,
+                               ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
+               INIT_INI_ARRAY(&ah->iniModesTxGain,
+                       ar9331_modes_lowest_ob_db_tx_gain_1p2,
+                       ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
+                       5);
+
+               /* additional clock settings */
+               if (ah->is_clk_25mhz)
+                       INIT_INI_ARRAY(&ah->iniModesAdditional,
+                                       ar9331_1p2_xtal_25M,
+                                       ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
+               else
+                       INIT_INI_ARRAY(&ah->iniModesAdditional,
+                                       ar9331_1p2_xtal_40M,
+                                       ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
+       } else if (AR_SREV_9340(ah)) {
                /* mac */
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
@@ -220,7 +328,17 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
        switch (ar9003_hw_get_tx_gain_idx(ah)) {
        case 0:
        default:
-               if (AR_SREV_9340(ah))
+               if (AR_SREV_9330_12(ah))
+                       INIT_INI_ARRAY(&ah->iniModesTxGain,
+                               ar9331_modes_lowest_ob_db_tx_gain_1p2,
+                               ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
+                               5);
+               else if (AR_SREV_9330_11(ah))
+                       INIT_INI_ARRAY(&ah->iniModesTxGain,
+                               ar9331_modes_lowest_ob_db_tx_gain_1p1,
+                               ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
+                               5);
+               else if (AR_SREV_9340(ah))
                        INIT_INI_ARRAY(&ah->iniModesTxGain,
                                        ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
                                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
@@ -237,7 +355,17 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
                                       5);
                break;
        case 1:
-               if (AR_SREV_9340(ah))
+               if (AR_SREV_9330_12(ah))
+                       INIT_INI_ARRAY(&ah->iniModesTxGain,
+                               ar9331_modes_high_ob_db_tx_gain_1p2,
+                               ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
+                               5);
+               else if (AR_SREV_9330_11(ah))
+                       INIT_INI_ARRAY(&ah->iniModesTxGain,
+                               ar9331_modes_high_ob_db_tx_gain_1p1,
+                               ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
+                               5);
+               else if (AR_SREV_9340(ah))
                        INIT_INI_ARRAY(&ah->iniModesTxGain,
                                        ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
                                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
@@ -254,7 +382,17 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
                                       5);
                break;
        case 2:
-               if (AR_SREV_9340(ah))
+               if (AR_SREV_9330_12(ah))
+                       INIT_INI_ARRAY(&ah->iniModesTxGain,
+                               ar9331_modes_low_ob_db_tx_gain_1p2,
+                               ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
+                               5);
+               else if (AR_SREV_9330_11(ah))
+                       INIT_INI_ARRAY(&ah->iniModesTxGain,
+                               ar9331_modes_low_ob_db_tx_gain_1p1,
+                               ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
+                               5);
+               else if (AR_SREV_9340(ah))
                        INIT_INI_ARRAY(&ah->iniModesTxGain,
                                        ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
                                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
@@ -271,7 +409,17 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
                                       5);
                break;
        case 3:
-               if (AR_SREV_9340(ah))
+               if (AR_SREV_9330_12(ah))
+                       INIT_INI_ARRAY(&ah->iniModesTxGain,
+                               ar9331_modes_high_power_tx_gain_1p2,
+                               ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
+                               5);
+               else if (AR_SREV_9330_11(ah))
+                       INIT_INI_ARRAY(&ah->iniModesTxGain,
+                               ar9331_modes_high_power_tx_gain_1p1,
+                               ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
+                               5);
+               else if (AR_SREV_9340(ah))
                        INIT_INI_ARRAY(&ah->iniModesTxGain,
                                        ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
                                       ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
@@ -295,7 +443,17 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
        switch (ar9003_hw_get_rx_gain_idx(ah)) {
        case 0:
        default:
-               if (AR_SREV_9340(ah))
+               if (AR_SREV_9330_12(ah))
+                       INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                       ar9331_common_rx_gain_1p2,
+                                       ARRAY_SIZE(ar9331_common_rx_gain_1p2),
+                                       2);
+               else if (AR_SREV_9330_11(ah))
+                       INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                       ar9331_common_rx_gain_1p1,
+                                       ARRAY_SIZE(ar9331_common_rx_gain_1p1),
+                                       2);
+               else if (AR_SREV_9340(ah))
                        INIT_INI_ARRAY(&ah->iniModesRxGain,
                                       ar9340Common_rx_gain_table_1p0,
                                       ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
@@ -312,7 +470,17 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
                                       2);
                break;
        case 1:
-               if (AR_SREV_9340(ah))
+               if (AR_SREV_9330_12(ah))
+                       INIT_INI_ARRAY(&ah->iniModesRxGain,
+                               ar9331_common_wo_xlna_rx_gain_1p2,
+                               ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
+                               2);
+               else if (AR_SREV_9330_11(ah))
+                       INIT_INI_ARRAY(&ah->iniModesRxGain,
+                               ar9331_common_wo_xlna_rx_gain_1p1,
+                               ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
+                               2);
+               else if (AR_SREV_9340(ah))
                        INIT_INI_ARRAY(&ah->iniModesRxGain,
                                       ar9340Common_wo_xlna_rx_gain_table_1p0,
                                       ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
index 10d71f7..575e185 100644 (file)
@@ -43,13 +43,6 @@ static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
        ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
 }
 
-static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link)
-{
-       struct ar9003_txc *ads = ds;
-
-       *ds_link = &ads->link;
-}
-
 static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
 {
        u32 isr = 0;
@@ -236,6 +229,7 @@ static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
 static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
                                 struct ath_tx_status *ts)
 {
+       struct ar9003_txc *txc = (struct ar9003_txc *) ds;
        struct ar9003_txs *ads;
        u32 status;
 
@@ -245,7 +239,11 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
        if ((status & AR_TxDone) == 0)
                return -EINPROGRESS;
 
-       ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
+       ts->qid = MS(ads->ds_info, AR_TxQcuNum);
+       if (!txc || (MS(txc->info, AR_TxQcuNum) == ts->qid))
+               ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
+       else
+               return -ENOENT;
 
        if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
            (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
@@ -261,7 +259,6 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
        ts->ts_seqnum = MS(status, AR_SeqNum);
        ts->tid = MS(status, AR_TxTid);
 
-       ts->qid = MS(ads->ds_info, AR_TxQcuNum);
        ts->desc_id = MS(ads->status1, AR_TxDescId);
        ts->ts_tstamp = ads->status4;
        ts->ts_status = 0;
@@ -498,7 +495,6 @@ void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
 
        ops->rx_enable = ar9003_hw_rx_enable;
        ops->set_desc_link = ar9003_hw_set_desc_link;
-       ops->get_desc_link = ar9003_hw_get_desc_link;
        ops->get_isr = ar9003_hw_get_isr;
        ops->fill_txdesc = ar9003_hw_fill_txdesc;
        ops->proc_txdesc = ar9003_hw_proc_txdesc;
index e4d6a87..f80d1d6 100644 (file)
@@ -21,6 +21,36 @@ void ar9003_paprd_enable(struct ath_hw *ah, bool val)
 {
        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
        struct ath9k_channel *chan = ah->curchan;
+       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+       /*
+        * 3 bits for modalHeader5G.papdRateMaskHt20
+        * is used for sub-band disabling of PAPRD.
+        * 5G band is divided into 3 sub-bands -- upper,
+        * middle, lower.
+        * if bit 30 of modalHeader5G.papdRateMaskHt20 is set
+        * -- disable PAPRD for upper band 5GHz
+        * if bit 29 of modalHeader5G.papdRateMaskHt20 is set
+        * -- disable PAPRD for middle band 5GHz
+        * if bit 28 of modalHeader5G.papdRateMaskHt20 is set
+        * -- disable PAPRD for lower band 5GHz
+        */
+
+       if (IS_CHAN_5GHZ(chan)) {
+               if (chan->channel >= UPPER_5G_SUB_BAND_START) {
+                       if (le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20)
+                                                                 & BIT(30))
+                               val = false;
+               } else if (chan->channel >= MID_5G_SUB_BAND_START) {
+                       if (le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20)
+                                                                 & BIT(29))
+                               val = false;
+               } else {
+                       if (le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20)
+                                                                 & BIT(28))
+                               val = false;
+               }
+       }
 
        if (val) {
                ah->paprd_table_write_done = true;
@@ -46,11 +76,10 @@ EXPORT_SYMBOL(ar9003_paprd_enable);
 
 static int ar9003_get_training_power_2g(struct ath_hw *ah)
 {
-       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
-       struct ar9300_modal_eep_header *hdr = &eep->modalHeader2G;
+       struct ath9k_channel *chan = ah->curchan;
        unsigned int power, scale, delta;
 
-       scale = MS(le32_to_cpu(hdr->papdRateMaskHt20), AR9300_PAPRD_SCALE_1);
+       scale = ar9003_get_paprd_scale_factor(ah, chan);
        power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
                               AR_PHY_POWERTX_RATE5_POWERTXHT20_0);
 
@@ -67,20 +96,10 @@ static int ar9003_get_training_power_2g(struct ath_hw *ah)
 static int ar9003_get_training_power_5g(struct ath_hw *ah)
 {
        struct ath_common *common = ath9k_hw_common(ah);
-       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
-       struct ar9300_modal_eep_header *hdr = &eep->modalHeader5G;
        struct ath9k_channel *chan = ah->curchan;
        unsigned int power, scale, delta;
 
-       if (chan->channel >= 5700)
-               scale = MS(le32_to_cpu(hdr->papdRateMaskHt20),
-                          AR9300_PAPRD_SCALE_1);
-       else if (chan->channel >= 5400)
-               scale = MS(le32_to_cpu(hdr->papdRateMaskHt40),
-                          AR9300_PAPRD_SCALE_2);
-       else
-               scale = MS(le32_to_cpu(hdr->papdRateMaskHt40),
-                          AR9300_PAPRD_SCALE_1);
+       scale = ar9003_get_paprd_scale_factor(ah, chan);
 
        if (IS_CHAN_HT40(chan))
                power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE8,
@@ -94,7 +113,23 @@ static int ar9003_get_training_power_5g(struct ath_hw *ah)
        if (delta > scale)
                return -1;
 
-       power += 2 * get_streams(common->tx_chainmask);
+       switch (get_streams(common->tx_chainmask)) {
+       case 1:
+               delta = 6;
+               break;
+       case 2:
+               delta = 4;
+               break;
+       case 3:
+               delta = 2;
+               break;
+       default:
+               delta = 0;
+               ath_dbg(common, ATH_DBG_CALIBRATE,
+               "Invalid tx-chainmask: %u\n", common->tx_chainmask);
+       }
+
+       power += delta;
        return power;
 }
 
@@ -119,15 +154,16 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
        else
                training_power = ar9003_get_training_power_5g(ah);
 
+       ath_dbg(common, ATH_DBG_CALIBRATE,
+               "Training power: %d, Target power: %d\n",
+               training_power, ah->paprd_target_power);
+
        if (training_power < 0) {
                ath_dbg(common, ATH_DBG_CALIBRATE,
                        "PAPRD target power delta out of range");
                return -ERANGE;
        }
        ah->paprd_training_power = training_power;
-       ath_dbg(common, ATH_DBG_CALIBRATE,
-               "Training power: %d, Target power: %d\n",
-               ah->paprd_training_power, ah->paprd_target_power);
 
        REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK,
                      ah->paprd_ratemask);
@@ -230,7 +266,7 @@ static void ar9003_paprd_get_gain_table(struct ath_hw *ah)
        memset(entry, 0, sizeof(ah->paprd_gain_table_entries));
        memset(index, 0, sizeof(ah->paprd_gain_table_index));
 
-       for (i = 0; i < 32; i++) {
+       for (i = 0; i < PAPRD_GAIN_TABLE_ENTRIES; i++) {
                entry[i] = REG_READ(ah, reg);
                index[i] = (entry[i] >> 24) & 0xff;
                reg += 4;
@@ -240,13 +276,13 @@ static void ar9003_paprd_get_gain_table(struct ath_hw *ah)
 static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain,
                                            int target_power)
 {
-       int olpc_gain_delta = 0;
+       int olpc_gain_delta = 0, cl_gain_mod;
        int alpha_therm, alpha_volt;
        int therm_cal_value, volt_cal_value;
        int therm_value, volt_value;
        int thermal_gain_corr, voltage_gain_corr;
        int desired_scale, desired_gain = 0;
-       u32 reg;
+       u32 reg_olpc  = 0, reg_cl_gain  = 0;
 
        REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
                    AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE);
@@ -265,15 +301,29 @@ static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain,
        volt_value = REG_READ_FIELD(ah, AR_PHY_BB_THERM_ADC_4,
                                    AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE);
 
-       if (chain == 0)
-               reg = AR_PHY_TPC_11_B0;
-       else if (chain == 1)
-               reg = AR_PHY_TPC_11_B1;
-       else
-               reg = AR_PHY_TPC_11_B2;
+       switch (chain) {
+       case 0:
+               reg_olpc = AR_PHY_TPC_11_B0;
+               reg_cl_gain = AR_PHY_CL_TAB_0;
+               break;
+       case 1:
+               reg_olpc = AR_PHY_TPC_11_B1;
+               reg_cl_gain = AR_PHY_CL_TAB_1;
+               break;
+       case 2:
+               reg_olpc = AR_PHY_TPC_11_B2;
+               reg_cl_gain = AR_PHY_CL_TAB_2;
+               break;
+       default:
+               ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
+               "Invalid chainmask: %d\n", chain);
+               break;
+       }
 
-       olpc_gain_delta = REG_READ_FIELD(ah, reg,
+       olpc_gain_delta = REG_READ_FIELD(ah, reg_olpc,
                                         AR_PHY_TPC_11_OLPC_GAIN_DELTA);
+       cl_gain_mod = REG_READ_FIELD(ah, reg_cl_gain,
+                                        AR_PHY_CL_TAB_CL_GAIN_MOD);
 
        if (olpc_gain_delta >= 128)
                olpc_gain_delta = olpc_gain_delta - 256;
@@ -283,7 +333,7 @@ static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain,
        voltage_gain_corr = (alpha_volt * (volt_value - volt_cal_value) +
                             (128 / 2)) / 128;
        desired_gain = target_power - olpc_gain_delta - thermal_gain_corr -
-           voltage_gain_corr + desired_scale;
+           voltage_gain_corr + desired_scale + cl_gain_mod;
 
        return desired_gain;
 }
@@ -721,7 +771,7 @@ int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain)
        desired_gain = ar9003_get_desired_gain(ah, chain, train_power);
 
        gain_index = 0;
-       for (i = 0; i < 32; i++) {
+       for (i = 0; i < PAPRD_GAIN_TABLE_ENTRIES; i++) {
                if (ah->paprd_gain_table_index[i] >= desired_gain)
                        break;
                gain_index++;
@@ -795,7 +845,26 @@ EXPORT_SYMBOL(ar9003_paprd_init_table);
 
 bool ar9003_paprd_is_done(struct ath_hw *ah)
 {
-       return !!REG_READ_FIELD(ah, AR_PHY_PAPRD_TRAINER_STAT1,
+       int paprd_done, agc2_pwr;
+       paprd_done = REG_READ_FIELD(ah, AR_PHY_PAPRD_TRAINER_STAT1,
                                AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE);
+
+       if (paprd_done == 0x1) {
+               agc2_pwr = REG_READ_FIELD(ah, AR_PHY_PAPRD_TRAINER_STAT1,
+                               AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR);
+
+               ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
+                       "AGC2_PWR = 0x%x training done = 0x%x\n",
+                       agc2_pwr, paprd_done);
+       /*
+        * agc2_pwr range should not be less than 'IDEAL_AGC2_PWR_CHANGE'
+        * when the training is completely done, otherwise retraining is
+        * done to make sure the value is in ideal range
+        */
+               if (agc2_pwr <= PAPRD_IDEAL_AGC2_PWR_RANGE)
+                       paprd_done = 0;
+       }
+
+       return !!paprd_done;
 }
 EXPORT_SYMBOL(ar9003_paprd_is_done);
index 892c48b..1baca8e 100644 (file)
@@ -75,7 +75,19 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
        freq = centers.synth_center;
 
        if (freq < 4800) {     /* 2 GHz, fractional mode */
-               if (AR_SREV_9485(ah)) {
+               if (AR_SREV_9330(ah)) {
+                       u32 chan_frac;
+                       u32 div;
+
+                       if (ah->is_clk_25mhz)
+                               div = 75;
+                       else
+                               div = 120;
+
+                       channelSel = (freq * 4) / div;
+                       chan_frac = (((freq * 4) % div) * 0x20000) / div;
+                       channelSel = (channelSel << 17) | chan_frac;
+               } else if (AR_SREV_9485(ah)) {
                        u32 chan_frac;
 
                        /*
@@ -104,7 +116,7 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
                        u32 chan_frac;
 
                        channelSel = (freq * 2) / 75;
-                       chan_frac = ((freq % 75) * 0x20000) / 75;
+                       chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
                        channelSel = (channelSel << 17) | chan_frac;
                } else {
                        channelSel = CHANSEL_5G(freq);
@@ -168,7 +180,7 @@ static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
         * is out-of-band and can be ignored.
         */
 
-       if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) {
+       if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) {
                spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
                                                         IS_CHAN_2GHZ(chan));
                if (spur_fbin_ptr[0] == 0) /* No spur */
@@ -193,7 +205,7 @@ static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
 
        for (i = 0; i < max_spur_cnts; i++) {
                negative = 0;
-               if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
+               if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
                        cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
                                        IS_CHAN_2GHZ(chan)) - synth_freq;
                else
@@ -659,6 +671,9 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
                REG_WRITE_ARRAY(&ah->iniModesAdditional,
                                modesIndex, regWrites);
 
+       if (AR_SREV_9300(ah))
+               REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites);
+
        if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
                REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
 
@@ -1074,7 +1089,10 @@ static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
 {
        ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
        ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
-       ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
+       if (AR_SREV_9330(ah))
+               ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
+       else
+               ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
        ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
        ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
        ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
@@ -1196,8 +1214,17 @@ static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
                                 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
        antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
                                  AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
-       antconf->lna1_lna2_delta = -9;
-       antconf->div_group = 2;
+
+       if (AR_SREV_9330_11(ah)) {
+               antconf->lna1_lna2_delta = -9;
+               antconf->div_group = 1;
+       } else if (AR_SREV_9485(ah)) {
+               antconf->lna1_lna2_delta = -9;
+               antconf->div_group = 2;
+       } else {
+               antconf->lna1_lna2_delta = -3;
+               antconf->div_group = 0;
+       }
 }
 
 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
index 443090d..6de3f0b 100644 (file)
 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ     -95
 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ     -100
 
+#define AR_PHY_CCA_NOM_VAL_9330_2GHZ          -118
+
 /*
  * AGC Field Definitions
  */
 #define AR_PHY_65NM_CH2_RXTX1       0x16900
 #define AR_PHY_65NM_CH2_RXTX2       0x16904
 
-#define AR_CH0_TOP2 (AR_SREV_9485(ah) ? 0x00016284 : 0x0001628c)
+#define AR_CH0_TOP2            (AR_SREV_9300(ah) ? 0x1628c : 0x16284)
 #define AR_CH0_TOP2_XPABIASLVL         0xf000
 #define AR_CH0_TOP2_XPABIASLVL_S       12
 
-#define AR_CH0_XTAL            (AR_SREV_9485(ah) ? 0x16290 : 0x16294)
+#define AR_CH0_XTAL            (AR_SREV_9300(ah) ? 0x16294 : 0x16290)
 #define AR_CH0_XTAL_CAPINDAC   0x7f000000
 #define AR_CH0_XTAL_CAPINDAC_S 24
 #define AR_CH0_XTAL_CAPOUTDAC  0x00fe0000
 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5     0x3F00
 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S   8
 
+#define AR_PHY_CL_TAB_CL_GAIN_MOD              0x1f
+#define AR_PHY_CL_TAB_CL_GAIN_MOD_S            0
+
 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
 
 #endif  /* AR9003_PHY_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h b/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
new file mode 100644 (file)
index 0000000..f11d9b2
--- /dev/null
@@ -0,0 +1,1147 @@
+/*
+ * Copyright (c) 2011 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef INITVALS_9330_1P1_H
+#define INITVALS_9330_1P1_H
+
+static const u32 ar9331_1p1_baseband_postamble[][5] = {
+       /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
+       {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
+       {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
+       {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
+       {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
+       {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
+       {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
+       {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
+       {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
+       {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
+       {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
+       {0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e},
+       {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
+       {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
+       {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
+       {0x00009e2c, 0x0000001c, 0x0000001c, 0x00003221, 0x00003221},
+       {0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222},
+       {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
+       {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
+       {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
+       {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0},
+       {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
+       {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
+       {0x0000a234, 0x00000fff, 0x00000fff, 0x10000fff, 0x00000fff},
+       {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
+       {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
+       {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
+       {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
+       {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
+       {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
+       {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
+       {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
+       {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
+       {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981},
+       {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
+       {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
+       {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+};
+
+static const u32 ar9331_modes_lowest_ob_db_tx_gain_1p1[][5] = {
+       /*   Addr     5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
+       {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
+       {0x0000a2dc, 0xffff2a52, 0xffff2a52, 0xffff2a52, 0xffff2a52},
+       {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
+       {0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000},
+       {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000},
+       {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0},
+       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
+       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
+       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
+       {0x0000a52c, 0x41023e85, 0x41023e85, 0x2d000a20, 0x2d000a20},
+       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000a22, 0x31000a22},
+       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000a24, 0x35000a24},
+       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000a43, 0x38000a43},
+       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3b000e42, 0x3b000e42},
+       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x3f000e44, 0x3f000e44},
+       {0x0000a544, 0x6502feca, 0x6502feca, 0x42000e64, 0x42000e64},
+       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46000e66, 0x46000e66},
+       {0x0000a54c, 0x7203feca, 0x7203feca, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+       {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+       {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+       {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
+       {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
+       {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
+       {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
+       {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
+       {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
+       {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
+       {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
+       {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
+       {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
+       {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
+       {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
+       {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
+       {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
+       {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
+       {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
+       {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
+       {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
+       {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
+       {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
+       {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
+       {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
+       {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
+       {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
+       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
+       {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
+       {0x0000a620, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802},
+       {0x0000a624, 0x03010a03, 0x03010a03, 0x03010a03, 0x03010a03},
+       {0x0000a628, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x0000a62c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x0000a630, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x0000a634, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x0000a638, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x0000a63c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x00016044, 0x034922db, 0x034922db, 0x034922db, 0x034922db},
+       {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
+};
+
+static const u32 ar9331_modes_high_ob_db_tx_gain_1p1[][5] = {
+       /*   Addr     5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
+       {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
+       {0x0000a2dc, 0xffaa9a52, 0xffaa9a52, 0xffaa9a52, 0xffaa9a52},
+       {0x0000a2e0, 0xffb31c84, 0xffb31c84, 0xffb31c84, 0xffb31c84},
+       {0x0000a2e4, 0xff43e000, 0xff43e000, 0xff43e000, 0xff43e000},
+       {0x0000a2e8, 0xfffc0000, 0xfffc0000, 0xfffc0000, 0xfffc0000},
+       {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
+       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
+       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
+       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
+       {0x0000a52c, 0x41023e85, 0x41023e85, 0x3d001620, 0x3d001620},
+       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x3f001621, 0x3f001621},
+       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x42001640, 0x42001640},
+       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x44001641, 0x44001641},
+       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x46001642, 0x46001642},
+       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49001644, 0x49001644},
+       {0x0000a544, 0x6502feca, 0x6502feca, 0x4c001a81, 0x4c001a81},
+       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4f001a83, 0x4f001a83},
+       {0x0000a54c, 0x7203feca, 0x7203feca, 0x52001c84, 0x52001c84},
+       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001ce3, 0x55001ce3},
+       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x59001ce5, 0x59001ce5},
+       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5d001ce9, 0x5d001ce9},
+       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x64001eec, 0x64001eec},
+       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x64001eec, 0x64001eec},
+       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x64001eec, 0x64001eec},
+       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x64001eec, 0x64001eec},
+       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x64001eec, 0x64001eec},
+       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x64001eec, 0x64001eec},
+       {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x64001eec, 0x64001eec},
+       {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x64001eec, 0x64001eec},
+       {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x64001eec, 0x64001eec},
+       {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+       {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+       {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+       {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
+       {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
+       {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
+       {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
+       {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
+       {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
+       {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
+       {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
+       {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
+       {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
+       {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
+       {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
+       {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
+       {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
+       {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
+       {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
+       {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
+       {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
+       {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
+       {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
+       {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
+       {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
+       {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
+       {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
+       {0x0000a618, 0x02008501, 0x02008501, 0x02008501, 0x02008501},
+       {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
+       {0x0000a620, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802},
+       {0x0000a624, 0x0280ca03, 0x0280ca03, 0x0280ca03, 0x0280ca03},
+       {0x0000a628, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x0000a62c, 0x04015005, 0x04015005, 0x04015005, 0x04015005},
+       {0x0000a630, 0x04015005, 0x04015005, 0x04015005, 0x04015005},
+       {0x0000a634, 0x04015005, 0x04015005, 0x04015005, 0x04015005},
+       {0x0000a638, 0x04015005, 0x04015005, 0x04015005, 0x04015005},
+       {0x0000a63c, 0x04015005, 0x04015005, 0x04015005, 0x04015005},
+};
+
+static const u32 ar9331_modes_low_ob_db_tx_gain_1p1[][5] = {
+       /*   Addr     5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
+       {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
+       {0x0000a2dc, 0xffff2a52, 0xffff2a52, 0xffff2a52, 0xffff2a52},
+       {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
+       {0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000},
+       {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000},
+       {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0},
+       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
+       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
+       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
+       {0x0000a52c, 0x41023e85, 0x41023e85, 0x2d000a20, 0x2d000a20},
+       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000a22, 0x31000a22},
+       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000a24, 0x35000a24},
+       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000a43, 0x38000a43},
+       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3b000e42, 0x3b000e42},
+       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x3f000e44, 0x3f000e44},
+       {0x0000a544, 0x6502feca, 0x6502feca, 0x42000e64, 0x42000e64},
+       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46000e66, 0x46000e66},
+       {0x0000a54c, 0x7203feca, 0x7203feca, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+       {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+       {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+       {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
+       {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
+       {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
+       {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
+       {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
+       {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
+       {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
+       {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
+       {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
+       {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
+       {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
+       {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
+       {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
+       {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
+       {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
+       {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
+       {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
+       {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
+       {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
+       {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
+       {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
+       {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
+       {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
+       {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
+       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
+       {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
+       {0x0000a620, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802},
+       {0x0000a624, 0x03010a03, 0x03010a03, 0x03010a03, 0x03010a03},
+       {0x0000a628, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x0000a62c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x0000a630, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x0000a634, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x0000a638, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x0000a63c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x00016044, 0x034922db, 0x034922db, 0x034922db, 0x034922db},
+       {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
+};
+
+static const u32 ar9331_1p1_baseband_core_txfir_coeff_japan_2484[][2] = {
+       /* Addr      allmodes  */
+       {0x0000a398, 0x00000000},
+       {0x0000a39c, 0x6f7f0301},
+       {0x0000a3a0, 0xca9228ee},
+};
+
+static const u32 ar9331_1p1_xtal_25M[][2] = {
+       /* Addr      allmodes  */
+       {0x00007038, 0x000002f8},
+       {0x00008244, 0x0010f3d7},
+       {0x0000824c, 0x0001e7ae},
+       {0x0001609c, 0x0f508f29},
+};
+
+static const u32 ar9331_1p1_radio_core[][2] = {
+       /* Addr      allmodes  */
+       {0x00016000, 0x36db6db6},
+       {0x00016004, 0x6db6db40},
+       {0x00016008, 0x73800000},
+       {0x0001600c, 0x00000000},
+       {0x00016040, 0x7f80fff8},
+       {0x00016044, 0x03db62db},
+       {0x00016048, 0x6c924268},
+       {0x0001604c, 0x000f0278},
+       {0x00016050, 0x4db6db8c},
+       {0x00016054, 0x6db60000},
+       {0x00016080, 0x00080000},
+       {0x00016084, 0x0e48048c},
+       {0x00016088, 0x14214514},
+       {0x0001608c, 0x119f081c},
+       {0x00016090, 0x24926490},
+       {0x00016098, 0xd411eb84},
+       {0x000160a0, 0xc2108ffe},
+       {0x000160a4, 0x812fc370},
+       {0x000160a8, 0x423c8000},
+       {0x000160ac, 0x24651800},
+       {0x000160b0, 0x03284f3e},
+       {0x000160b4, 0x92480040},
+       {0x000160c0, 0x006db6db},
+       {0x000160c4, 0x0186db60},
+       {0x000160c8, 0x6db6db6c},
+       {0x000160cc, 0x6de6c300},
+       {0x000160d0, 0x14500820},
+       {0x00016100, 0x04cb0001},
+       {0x00016104, 0xfff80015},
+       {0x00016108, 0x00080010},
+       {0x0001610c, 0x00170000},
+       {0x00016140, 0x10804000},
+       {0x00016144, 0x01884080},
+       {0x00016148, 0x000080c0},
+       {0x00016280, 0x01000015},
+       {0x00016284, 0x14d20000},
+       {0x00016288, 0x00318000},
+       {0x0001628c, 0x50000000},
+       {0x00016290, 0x4b96210f},
+       {0x00016380, 0x00000000},
+       {0x00016384, 0x00000000},
+       {0x00016388, 0x00800700},
+       {0x0001638c, 0x00800700},
+       {0x00016390, 0x00800700},
+       {0x00016394, 0x00000000},
+       {0x00016398, 0x00000000},
+       {0x0001639c, 0x00000000},
+       {0x000163a0, 0x00000001},
+       {0x000163a4, 0x00000001},
+       {0x000163a8, 0x00000000},
+       {0x000163ac, 0x00000000},
+       {0x000163b0, 0x00000000},
+       {0x000163b4, 0x00000000},
+       {0x000163b8, 0x00000000},
+       {0x000163bc, 0x00000000},
+       {0x000163c0, 0x000000a0},
+       {0x000163c4, 0x000c0000},
+       {0x000163c8, 0x14021402},
+       {0x000163cc, 0x00001402},
+       {0x000163d0, 0x00000000},
+       {0x000163d4, 0x00000000},
+};
+
+static const u32 ar9331_1p1_soc_postamble[][5] = {
+       /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
+       {0x00007010, 0x00000022, 0x00000022, 0x00000022, 0x00000022},
+};
+
+static const u32 ar9331_common_wo_xlna_rx_gain_1p1[][2] = {
+       /* Addr      allmodes  */
+       {0x0000a000, 0x00060005},
+       {0x0000a004, 0x00810080},
+       {0x0000a008, 0x00830082},
+       {0x0000a00c, 0x00850084},
+       {0x0000a010, 0x01820181},
+       {0x0000a014, 0x01840183},
+       {0x0000a018, 0x01880185},
+       {0x0000a01c, 0x018a0189},
+       {0x0000a020, 0x02850284},
+       {0x0000a024, 0x02890288},
+       {0x0000a028, 0x028b028a},
+       {0x0000a02c, 0x03850384},
+       {0x0000a030, 0x03890388},
+       {0x0000a034, 0x038b038a},
+       {0x0000a038, 0x038d038c},
+       {0x0000a03c, 0x03910390},
+       {0x0000a040, 0x03930392},
+       {0x0000a044, 0x03950394},
+       {0x0000a048, 0x00000396},
+       {0x0000a04c, 0x00000000},
+       {0x0000a050, 0x00000000},
+       {0x0000a054, 0x00000000},
+       {0x0000a058, 0x00000000},
+       {0x0000a05c, 0x00000000},
+       {0x0000a060, 0x00000000},
+       {0x0000a064, 0x00000000},
+       {0x0000a068, 0x00000000},
+       {0x0000a06c, 0x00000000},
+       {0x0000a070, 0x00000000},
+       {0x0000a074, 0x00000000},
+       {0x0000a078, 0x00000000},
+       {0x0000a07c, 0x00000000},
+       {0x0000a080, 0x28282828},
+       {0x0000a084, 0x28282828},
+       {0x0000a088, 0x28282828},
+       {0x0000a08c, 0x28282828},
+       {0x0000a090, 0x28282828},
+       {0x0000a094, 0x24242428},
+       {0x0000a098, 0x171e1e1e},
+       {0x0000a09c, 0x02020b0b},
+       {0x0000a0a0, 0x02020202},
+       {0x0000a0a4, 0x00000000},
+       {0x0000a0a8, 0x00000000},
+       {0x0000a0ac, 0x00000000},
+       {0x0000a0b0, 0x00000000},
+       {0x0000a0b4, 0x00000000},
+       {0x0000a0b8, 0x00000000},
+       {0x0000a0bc, 0x00000000},
+       {0x0000a0c0, 0x22072208},
+       {0x0000a0c4, 0x22052206},
+       {0x0000a0c8, 0x22032204},
+       {0x0000a0cc, 0x22012202},
+       {0x0000a0d0, 0x221f2200},
+       {0x0000a0d4, 0x221d221e},
+       {0x0000a0d8, 0x33023303},
+       {0x0000a0dc, 0x33003301},
+       {0x0000a0e0, 0x331e331f},
+       {0x0000a0e4, 0x4402331d},
+       {0x0000a0e8, 0x44004401},
+       {0x0000a0ec, 0x441e441f},
+       {0x0000a0f0, 0x55025503},
+       {0x0000a0f4, 0x55005501},
+       {0x0000a0f8, 0x551e551f},
+       {0x0000a0fc, 0x6602551d},
+       {0x0000a100, 0x66006601},
+       {0x0000a104, 0x661e661f},
+       {0x0000a108, 0x7703661d},
+       {0x0000a10c, 0x77017702},
+       {0x0000a110, 0x00007700},
+       {0x0000a114, 0x00000000},
+       {0x0000a118, 0x00000000},
+       {0x0000a11c, 0x00000000},
+       {0x0000a120, 0x00000000},
+       {0x0000a124, 0x00000000},
+       {0x0000a128, 0x00000000},
+       {0x0000a12c, 0x00000000},
+       {0x0000a130, 0x00000000},
+       {0x0000a134, 0x00000000},
+       {0x0000a138, 0x00000000},
+       {0x0000a13c, 0x00000000},
+       {0x0000a140, 0x001f0000},
+       {0x0000a144, 0x111f1100},
+       {0x0000a148, 0x111d111e},
+       {0x0000a14c, 0x111b111c},
+       {0x0000a150, 0x22032204},
+       {0x0000a154, 0x22012202},
+       {0x0000a158, 0x221f2200},
+       {0x0000a15c, 0x221d221e},
+       {0x0000a160, 0x33013302},
+       {0x0000a164, 0x331f3300},
+       {0x0000a168, 0x4402331e},
+       {0x0000a16c, 0x44004401},
+       {0x0000a170, 0x441e441f},
+       {0x0000a174, 0x55015502},
+       {0x0000a178, 0x551f5500},
+       {0x0000a17c, 0x6602551e},
+       {0x0000a180, 0x66006601},
+       {0x0000a184, 0x661e661f},
+       {0x0000a188, 0x7703661d},
+       {0x0000a18c, 0x77017702},
+       {0x0000a190, 0x00007700},
+       {0x0000a194, 0x00000000},
+       {0x0000a198, 0x00000000},
+       {0x0000a19c, 0x00000000},
+       {0x0000a1a0, 0x00000000},
+       {0x0000a1a4, 0x00000000},
+       {0x0000a1a8, 0x00000000},
+       {0x0000a1ac, 0x00000000},
+       {0x0000a1b0, 0x00000000},
+       {0x0000a1b4, 0x00000000},
+       {0x0000a1b8, 0x00000000},
+       {0x0000a1bc, 0x00000000},
+       {0x0000a1c0, 0x00000000},
+       {0x0000a1c4, 0x00000000},
+       {0x0000a1c8, 0x00000000},
+       {0x0000a1cc, 0x00000000},
+       {0x0000a1d0, 0x00000000},
+       {0x0000a1d4, 0x00000000},
+       {0x0000a1d8, 0x00000000},
+       {0x0000a1dc, 0x00000000},
+       {0x0000a1e0, 0x00000000},
+       {0x0000a1e4, 0x00000000},
+       {0x0000a1e8, 0x00000000},
+       {0x0000a1ec, 0x00000000},
+       {0x0000a1f0, 0x00000396},
+       {0x0000a1f4, 0x00000396},
+       {0x0000a1f8, 0x00000396},
+       {0x0000a1fc, 0x00000296},
+};
+
+static const u32 ar9331_1p1_baseband_core[][2] = {
+       /* Addr      allmodes  */
+       {0x00009800, 0xafe68e30},
+       {0x00009804, 0xfd14e000},
+       {0x00009808, 0x9c0a8f6b},
+       {0x0000980c, 0x04800000},
+       {0x00009814, 0x9280c00a},
+       {0x00009818, 0x00000000},
+       {0x0000981c, 0x00020028},
+       {0x00009834, 0x5f3ca3de},
+       {0x00009838, 0x0108ecff},
+       {0x0000983c, 0x14750600},
+       {0x00009880, 0x201fff00},
+       {0x00009884, 0x00001042},
+       {0x000098a4, 0x00200400},
+       {0x000098b0, 0x32840bbe},
+       {0x000098d0, 0x004b6a8e},
+       {0x000098d4, 0x00000820},
+       {0x000098dc, 0x00000000},
+       {0x000098f0, 0x00000000},
+       {0x000098f4, 0x00000000},
+       {0x00009c04, 0x00000000},
+       {0x00009c08, 0x03200000},
+       {0x00009c0c, 0x00000000},
+       {0x00009c10, 0x00000000},
+       {0x00009c14, 0x00046384},
+       {0x00009c18, 0x05b6b440},
+       {0x00009c1c, 0x00b6b440},
+       {0x00009d00, 0xc080a333},
+       {0x00009d04, 0x40206c10},
+       {0x00009d08, 0x009c4060},
+       {0x00009d0c, 0x1883800a},
+       {0x00009d10, 0x01834061},
+       {0x00009d14, 0x00c00400},
+       {0x00009d18, 0x00000000},
+       {0x00009e08, 0x0038233c},
+       {0x00009e24, 0x9927b515},
+       {0x00009e28, 0x12ef0200},
+       {0x00009e30, 0x06336f77},
+       {0x00009e34, 0x6af6532f},
+       {0x00009e38, 0x0cc80c00},
+       {0x00009e40, 0x0d261820},
+       {0x00009e4c, 0x00001004},
+       {0x00009e50, 0x00ff03f1},
+       {0x00009fc0, 0x803e4788},
+       {0x00009fc4, 0x0001efb5},
+       {0x00009fcc, 0x40000014},
+       {0x0000a20c, 0x00000000},
+       {0x0000a220, 0x00000000},
+       {0x0000a224, 0x00000000},
+       {0x0000a228, 0x10002310},
+       {0x0000a23c, 0x00000000},
+       {0x0000a244, 0x0c000000},
+       {0x0000a2a0, 0x00000001},
+       {0x0000a2c0, 0x00000001},
+       {0x0000a2c8, 0x00000000},
+       {0x0000a2cc, 0x18c43433},
+       {0x0000a2d4, 0x00000000},
+       {0x0000a2dc, 0x00000000},
+       {0x0000a2e0, 0x00000000},
+       {0x0000a2e4, 0x00000000},
+       {0x0000a2e8, 0x00000000},
+       {0x0000a2ec, 0x00000000},
+       {0x0000a2f0, 0x00000000},
+       {0x0000a2f4, 0x00000000},
+       {0x0000a2f8, 0x00000000},
+       {0x0000a344, 0x00000000},
+       {0x0000a34c, 0x00000000},
+       {0x0000a350, 0x0000a000},
+       {0x0000a364, 0x00000000},
+       {0x0000a370, 0x00000000},
+       {0x0000a390, 0x00000001},
+       {0x0000a394, 0x00000444},
+       {0x0000a398, 0x001f0e0f},
+       {0x0000a39c, 0x0075393f},
+       {0x0000a3a0, 0xb79f6427},
+       {0x0000a3a4, 0x00000000},
+       {0x0000a3a8, 0xaaaaaaaa},
+       {0x0000a3ac, 0x3c466478},
+       {0x0000a3c0, 0x20202020},
+       {0x0000a3c4, 0x22222220},
+       {0x0000a3c8, 0x20200020},
+       {0x0000a3cc, 0x20202020},
+       {0x0000a3d0, 0x20202020},
+       {0x0000a3d4, 0x20202020},
+       {0x0000a3d8, 0x20202020},
+       {0x0000a3dc, 0x20202020},
+       {0x0000a3e0, 0x20202020},
+       {0x0000a3e4, 0x20202020},
+       {0x0000a3e8, 0x20202020},
+       {0x0000a3ec, 0x20202020},
+       {0x0000a3f0, 0x00000000},
+       {0x0000a3f4, 0x00000006},
+       {0x0000a3f8, 0x0cdbd380},
+       {0x0000a3fc, 0x000f0f01},
+       {0x0000a400, 0x8fa91f01},
+       {0x0000a404, 0x00000000},
+       {0x0000a408, 0x0e79e5c6},
+       {0x0000a40c, 0x00820820},
+       {0x0000a414, 0x1ce739ce},
+       {0x0000a418, 0x2d001dce},
+       {0x0000a41c, 0x1ce739ce},
+       {0x0000a420, 0x000001ce},
+       {0x0000a424, 0x1ce739ce},
+       {0x0000a428, 0x000001ce},
+       {0x0000a42c, 0x1ce739ce},
+       {0x0000a430, 0x1ce739ce},
+       {0x0000a434, 0x00000000},
+       {0x0000a438, 0x00001801},
+       {0x0000a43c, 0x00000000},
+       {0x0000a440, 0x00000000},
+       {0x0000a444, 0x00000000},
+       {0x0000a448, 0x04000000},
+       {0x0000a44c, 0x00000001},
+       {0x0000a450, 0x00010000},
+       {0x0000a458, 0x00000000},
+       {0x0000a640, 0x00000000},
+       {0x0000a644, 0x3fad9d74},
+       {0x0000a648, 0x0048060a},
+       {0x0000a64c, 0x00003c37},
+       {0x0000a670, 0x03020100},
+       {0x0000a674, 0x09080504},
+       {0x0000a678, 0x0d0c0b0a},
+       {0x0000a67c, 0x13121110},
+       {0x0000a680, 0x31301514},
+       {0x0000a684, 0x35343332},
+       {0x0000a688, 0x00000036},
+       {0x0000a690, 0x00000838},
+       {0x0000a7c0, 0x00000000},
+       {0x0000a7c4, 0xfffffffc},
+       {0x0000a7c8, 0x00000000},
+       {0x0000a7cc, 0x00000000},
+       {0x0000a7d0, 0x00000000},
+       {0x0000a7d4, 0x00000004},
+       {0x0000a7dc, 0x00000001},
+};
+
+static const u32 ar9331_modes_high_power_tx_gain_1p1[][5] = {
+       /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
+       {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
+       {0x0000a2dc, 0xffff2a52, 0xffff2a52, 0xffff2a52, 0xffff2a52},
+       {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
+       {0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000},
+       {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000},
+       {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0},
+       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
+       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
+       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
+       {0x0000a52c, 0x41023e85, 0x41023e85, 0x2d000a20, 0x2d000a20},
+       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000a22, 0x31000a22},
+       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000a24, 0x35000a24},
+       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000a43, 0x38000a43},
+       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3b000e42, 0x3b000e42},
+       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x3f000e44, 0x3f000e44},
+       {0x0000a544, 0x6502feca, 0x6502feca, 0x42000e64, 0x42000e64},
+       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46000e66, 0x46000e66},
+       {0x0000a54c, 0x7203feca, 0x7203feca, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
+       {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+       {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+       {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+       {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
+       {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
+       {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
+       {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
+       {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
+       {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
+       {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
+       {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
+       {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
+       {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
+       {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
+       {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
+       {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
+       {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
+       {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
+       {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
+       {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
+       {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
+       {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
+       {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
+       {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
+       {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
+       {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
+       {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
+       {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
+       {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
+       {0x0000a620, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802},
+       {0x0000a624, 0x03010a03, 0x03010a03, 0x03010a03, 0x03010a03},
+       {0x0000a628, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x0000a62c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x0000a630, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x0000a634, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x0000a638, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x0000a63c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
+       {0x00016044, 0x034922db, 0x034922db, 0x034922db, 0x034922db},
+       {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
+};
+
+static const u32 ar9331_1p1_mac_postamble[][5] = {
+       /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
+       {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
+       {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
+       {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
+       {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
+       {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
+       {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
+       {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
+       {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
+};
+
+static const u32 ar9331_1p1_soc_preamble[][2] = {
+       /* Addr      allmodes  */
+       {0x00007020, 0x00000000},
+       {0x00007034, 0x00000002},
+       {0x00007038, 0x000002f8},
+};
+
+static const u32 ar9331_1p1_xtal_40M[][2] = {
+       /* Addr      allmodes  */
+       {0x00007038, 0x000004c2},
+       {0x00008244, 0x0010f400},
+       {0x0000824c, 0x0001e800},
+       {0x0001609c, 0x0b283f31},
+};
+
+static const u32 ar9331_1p1_mac_core[][2] = {
+       /* Addr      allmodes  */
+       {0x00000008, 0x00000000},
+       {0x00000030, 0x00020085},
+       {0x00000034, 0x00000005},
+       {0x00000040, 0x00000000},
+       {0x00000044, 0x00000000},
+       {0x00000048, 0x00000008},
+       {0x0000004c, 0x00000010},
+       {0x00000050, 0x00000000},
+       {0x00001040, 0x002ffc0f},
+       {0x00001044, 0x002ffc0f},
+       {0x00001048, 0x002ffc0f},
+       {0x0000104c, 0x002ffc0f},
+       {0x00001050, 0x002ffc0f},
+       {0x00001054, 0x002ffc0f},
+       {0x00001058, 0x002ffc0f},
+       {0x0000105c, 0x002ffc0f},
+       {0x00001060, 0x002ffc0f},
+       {0x00001064, 0x002ffc0f},
+       {0x000010f0, 0x00000100},
+       {0x00001270, 0x00000000},
+       {0x000012b0, 0x00000000},
+       {0x000012f0, 0x00000000},
+       {0x0000143c, 0x00000000},
+       {0x0000147c, 0x00000000},
+       {0x00008000, 0x00000000},
+       {0x00008004, 0x00000000},
+       {0x00008008, 0x00000000},
+       {0x0000800c, 0x00000000},
+       {0x00008018, 0x00000000},
+       {0x00008020, 0x00000000},
+       {0x00008038, 0x00000000},
+       {0x0000803c, 0x00000000},
+       {0x00008040, 0x00000000},
+       {0x00008044, 0x00000000},
+       {0x00008048, 0x00000000},
+       {0x0000804c, 0xffffffff},
+       {0x00008054, 0x00000000},
+       {0x00008058, 0x00000000},
+       {0x0000805c, 0x000fc78f},
+       {0x00008060, 0x0000000f},
+       {0x00008064, 0x00000000},
+       {0x00008070, 0x00000310},
+       {0x00008074, 0x00000020},
+       {0x00008078, 0x00000000},
+       {0x0000809c, 0x0000000f},
+       {0x000080a0, 0x00000000},
+       {0x000080a4, 0x02ff0000},
+       {0x000080a8, 0x0e070605},
+       {0x000080ac, 0x0000000d},
+       {0x000080b0, 0x00000000},
+       {0x000080b4, 0x00000000},
+       {0x000080b8, 0x00000000},
+       {0x000080bc, 0x00000000},
+       {0x000080c0, 0x2a800000},
+       {0x000080c4, 0x06900168},
+       {0x000080c8, 0x13881c20},
+       {0x000080cc, 0x01f40000},
+       {0x000080d0, 0x00252500},
+       {0x000080d4, 0x00a00000},
+       {0x000080d8, 0x00400000},
+       {0x000080dc, 0x00000000},
+       {0x000080e0, 0xffffffff},
+       {0x000080e4, 0x0000ffff},
+       {0x000080e8, 0x3f3f3f3f},
+       {0x000080ec, 0x00000000},
+       {0x000080f0, 0x00000000},
+       {0x000080f4, 0x00000000},
+       {0x000080fc, 0x00020000},
+       {0x00008100, 0x00000000},
+       {0x00008108, 0x00000052},
+       {0x0000810c, 0x00000000},
+       {0x00008110, 0x00000000},
+       {0x00008114, 0x000007ff},
+       {0x00008118, 0x000000aa},
+       {0x0000811c, 0x00003210},
+       {0x00008124, 0x00000000},
+       {0x00008128, 0x00000000},
+       {0x0000812c, 0x00000000},
+       {0x00008130, 0x00000000},
+       {0x00008134, 0x00000000},
+       {0x00008138, 0x00000000},
+       {0x0000813c, 0x0000ffff},
+       {0x00008144, 0xffffffff},
+       {0x00008168, 0x00000000},
+       {0x0000816c, 0x00000000},
+       {0x00008170, 0x18486200},
+       {0x00008174, 0x33332210},
+       {0x00008178, 0x00000000},
+       {0x0000817c, 0x00020000},
+       {0x000081c0, 0x00000000},
+       {0x000081c4, 0x33332210},
+       {0x000081c8, 0x00000000},
+       {0x000081cc, 0x00000000},
+       {0x000081d4, 0x00000000},
+       {0x000081ec, 0x00000000},
+       {0x000081f0, 0x00000000},
+       {0x000081f4, 0x00000000},
+       {0x000081f8, 0x00000000},
+       {0x000081fc, 0x00000000},
+       {0x00008240, 0x00100000},
+       {0x00008248, 0x00000800},
+       {0x00008250, 0x00000000},
+       {0x00008254, 0x00000000},
+       {0x00008258, 0x00000000},
+       {0x0000825c, 0x40000000},
+       {0x00008260, 0x00080922},
+       {0x00008264, 0x9d400010},
+       {0x00008268, 0xffffffff},
+       {0x0000826c, 0x0000ffff},
+       {0x00008270, 0x00000000},
+       {0x00008274, 0x40000000},
+       {0x00008278, 0x003e4180},
+       {0x0000827c, 0x00000004},
+       {0x00008284, 0x0000002c},
+       {0x00008288, 0x0000002c},
+       {0x0000828c, 0x000000ff},
+       {0x00008294, 0x00000000},
+       {0x00008298, 0x00000000},
+       {0x0000829c, 0x00000000},
+       {0x00008300, 0x00000140},
+       {0x00008314, 0x00000000},
+       {0x0000831c, 0x0000010d},
+       {0x00008328, 0x00000000},
+       {0x0000832c, 0x00000007},
+       {0x00008330, 0x00000302},
+       {0x00008334, 0x00000700},
+       {0x00008338, 0x00ff0000},
+       {0x0000833c, 0x02400000},
+       {0x00008340, 0x000107ff},
+       {0x00008344, 0xaa48105b},
+       {0x00008348, 0x008f0000},
+       {0x0000835c, 0x00000000},
+       {0x00008360, 0xffffffff},
+       {0x00008364, 0xffffffff},
+       {0x00008368, 0x00000000},
+       {0x00008370, 0x00000000},
+       {0x00008374, 0x000000ff},
+       {0x00008378, 0x00000000},
+       {0x0000837c, 0x00000000},
+       {0x00008380, 0xffffffff},
+       {0x00008384, 0xffffffff},
+       {0x00008390, 0xffffffff},
+       {0x00008394, 0xffffffff},
+       {0x00008398, 0x00000000},
+       {0x0000839c, 0x00000000},
+       {0x000083a0, 0x00000000},
+       {0x000083a4, 0x0000fa14},
+       {0x000083a8, 0x000f0c00},
+       {0x000083ac, 0x33332210},
+       {0x000083b0, 0x33332210},
+       {0x000083b4, 0x33332210},
+       {0x000083b8, 0x33332210},
+       {0x000083bc, 0x00000000},
+       {0x000083c0, 0x00000000},
+       {0x000083c4, 0x00000000},
+       {0x000083c8, 0x00000000},
+       {0x000083cc, 0x00000200},
+       {0x000083d0, 0x000301ff},
+};
+
+static const u32 ar9331_common_rx_gain_1p1[][2] = {
+       /* Addr      allmodes  */
+       {0x0000a000, 0x00010000},
+       {0x0000a004, 0x00030002},
+       {0x0000a008, 0x00050004},
+       {0x0000a00c, 0x00810080},
+       {0x0000a010, 0x00830082},
+       {0x0000a014, 0x01810180},
+       {0x0000a018, 0x01830182},
+       {0x0000a01c, 0x01850184},
+       {0x0000a020, 0x01890188},
+       {0x0000a024, 0x018b018a},
+       {0x0000a028, 0x018d018c},
+       {0x0000a02c, 0x01910190},
+       {0x0000a030, 0x01930192},
+       {0x0000a034, 0x01950194},
+       {0x0000a038, 0x038a0196},
+       {0x0000a03c, 0x038c038b},
+       {0x0000a040, 0x0390038d},
+       {0x0000a044, 0x03920391},
+       {0x0000a048, 0x03940393},
+       {0x0000a04c, 0x03960395},
+       {0x0000a050, 0x00000000},
+       {0x0000a054, 0x00000000},
+       {0x0000a058, 0x00000000},
+       {0x0000a05c, 0x00000000},
+       {0x0000a060, 0x00000000},
+       {0x0000a064, 0x00000000},
+       {0x0000a068, 0x00000000},
+       {0x0000a06c, 0x00000000},
+       {0x0000a070, 0x00000000},
+       {0x0000a074, 0x00000000},
+       {0x0000a078, 0x00000000},
+       {0x0000a07c, 0x00000000},
+       {0x0000a080, 0x22222229},
+       {0x0000a084, 0x1d1d1d1d},
+       {0x0000a088, 0x1d1d1d1d},
+       {0x0000a08c, 0x1d1d1d1d},
+       {0x0000a090, 0x171d1d1d},
+       {0x0000a094, 0x11111717},
+       {0x0000a098, 0x00030311},
+       {0x0000a09c, 0x00000000},
+       {0x0000a0a0, 0x00000000},
+       {0x0000a0a4, 0x00000000},
+       {0x0000a0a8, 0x00000000},
+       {0x0000a0ac, 0x00000000},
+       {0x0000a0b0, 0x00000000},
+       {0x0000a0b4, 0x00000000},
+       {0x0000a0b8, 0x00000000},
+       {0x0000a0bc, 0x00000000},
+       {0x0000a0c0, 0x001f0000},
+       {0x0000a0c4, 0x01000101},
+       {0x0000a0c8, 0x011e011f},
+       {0x0000a0cc, 0x011c011d},
+       {0x0000a0d0, 0x02030204},
+       {0x0000a0d4, 0x02010202},
+       {0x0000a0d8, 0x021f0200},
+       {0x0000a0dc, 0x0302021e},
+       {0x0000a0e0, 0x03000301},
+       {0x0000a0e4, 0x031e031f},
+       {0x0000a0e8, 0x0402031d},
+       {0x0000a0ec, 0x04000401},
+       {0x0000a0f0, 0x041e041f},
+       {0x0000a0f4, 0x0502041d},
+       {0x0000a0f8, 0x05000501},
+       {0x0000a0fc, 0x051e051f},
+       {0x0000a100, 0x06010602},
+       {0x0000a104, 0x061f0600},
+       {0x0000a108, 0x061d061e},
+       {0x0000a10c, 0x07020703},
+       {0x0000a110, 0x07000701},
+       {0x0000a114, 0x00000000},
+       {0x0000a118, 0x00000000},
+       {0x0000a11c, 0x00000000},
+       {0x0000a120, 0x00000000},
+       {0x0000a124, 0x00000000},
+       {0x0000a128, 0x00000000},
+       {0x0000a12c, 0x00000000},
+       {0x0000a130, 0x00000000},
+       {0x0000a134, 0x00000000},
+       {0x0000a138, 0x00000000},
+       {0x0000a13c, 0x00000000},
+       {0x0000a140, 0x001f0000},
+       {0x0000a144, 0x01000101},
+       {0x0000a148, 0x011e011f},
+       {0x0000a14c, 0x011c011d},
+       {0x0000a150, 0x02030204},
+       {0x0000a154, 0x02010202},
+       {0x0000a158, 0x021f0200},
+       {0x0000a15c, 0x0302021e},
+       {0x0000a160, 0x03000301},
+       {0x0000a164, 0x031e031f},
+       {0x0000a168, 0x0402031d},
+       {0x0000a16c, 0x04000401},
+       {0x0000a170, 0x041e041f},
+       {0x0000a174, 0x0502041d},
+       {0x0000a178, 0x05000501},
+       {0x0000a17c, 0x051e051f},
+       {0x0000a180, 0x06010602},
+       {0x0000a184, 0x061f0600},
+       {0x0000a188, 0x061d061e},
+       {0x0000a18c, 0x07020703},
+       {0x0000a190, 0x07000701},
+       {0x0000a194, 0x00000000},
+       {0x0000a198, 0x00000000},
+       {0x0000a19c, 0x00000000},
+       {0x0000a1a0, 0x00000000},
+       {0x0000a1a4, 0x00000000},
+       {0x0000a1a8, 0x00000000},
+       {0x0000a1ac, 0x00000000},
+       {0x0000a1b0, 0x00000000},
+       {0x0000a1b4, 0x00000000},
+       {0x0000a1b8, 0x00000000},
+       {0x0000a1bc, 0x00000000},
+       {0x0000a1c0, 0x00000000},
+       {0x0000a1c4, 0x00000000},
+       {0x0000a1c8, 0x00000000},
+       {0x0000a1cc, 0x00000000},
+       {0x0000a1d0, 0x00000000},
+       {0x0000a1d4, 0x00000000},
+       {0x0000a1d8, 0x00000000},
+       {0x0000a1dc, 0x00000000},
+       {0x0000a1e0, 0x00000000},
+       {0x0000a1e4, 0x00000000},
+       {0x0000a1e8, 0x00000000},
+       {0x0000a1ec, 0x00000000},
+       {0x0000a1f0, 0x00000396},
+       {0x0000a1f4, 0x00000396},
+       {0x0000a1f8, 0x00000396},
+       {0x0000a1fc, 0x00000196},
+};
+
+static const u32 ar9331_common_tx_gain_offset1_1[][1] = {
+       {0},
+       {3},
+       {0},
+       {0},
+};
+
+static const u32 ar9331_1p1_chansel_xtal_25M[] = {
+       0x0101479e,
+       0x0101d027,
+       0x010258af,
+       0x0102e138,
+       0x010369c0,
+       0x0103f249,
+       0x01047ad1,
+       0x0105035a,
+       0x01058be2,
+       0x0106146b,
+       0x01069cf3,
+       0x0107257c,
+       0x0107ae04,
+       0x0108f5b2,
+};
+
+static const u32 ar9331_1p1_chansel_xtal_40M[] = {
+       0x00a0ccbe,
+       0x00a12213,
+       0x00a17769,
+       0x00a1ccbe,
+       0x00a22213,
+       0x00a27769,
+       0x00a2ccbe,
+       0x00a32213,
+       0x00a37769,
+       0x00a3ccbe,
+       0x00a42213,
+       0x00a47769,
+       0x00a4ccbe,
+       0x00a5998b,
+};
+
+#endif /* INITVALS_9330_1P1_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
new file mode 100644 (file)
index 0000000..0e6ca08
--- /dev/null
@@ -0,0 +1,1080 @@
+/*
+ * Copyright (c) 2011 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef INITVALS_9330_1P2_H
+#define INITVALS_9330_1P2_H
+
+static const u32 ar9331_modes_lowest_ob_db_tx_gain_1p2[][5] = {
+       /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
+       {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
+       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
+       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
+       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
+       {0x0000a52c, 0x41023e85, 0x41023e85, 0x3f001620, 0x3f001620},
+       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x41001621, 0x41001621},
+       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x44001640, 0x44001640},
+       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x46001641, 0x46001641},
+       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x48001642, 0x48001642},
+       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x4b001644, 0x4b001644},
+       {0x0000a544, 0x6502feca, 0x6502feca, 0x4e001a81, 0x4e001a81},
+       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x51001a83, 0x51001a83},
+       {0x0000a54c, 0x7203feca, 0x7203feca, 0x54001c84, 0x54001c84},
+       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x57001ce3, 0x57001ce3},
+       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x5b001ce5, 0x5b001ce5},
+       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5f001ce9, 0x5f001ce9},
+       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x66001eec, 0x66001eec},
+       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x66001eec, 0x66001eec},
+       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+       {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+       {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+       {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
+       {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
+       {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
+       {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
+       {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
+       {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
+       {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
+       {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
+       {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
+       {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
+       {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
+       {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
+       {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
+       {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
+       {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
+       {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
+       {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
+       {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
+       {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
+       {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
+       {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
+       {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
+       {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
+       {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
+       {0x0000a618, 0x02008501, 0x02008501, 0x02008501, 0x02008501},
+       {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
+       {0x0000a620, 0x0300c802, 0x0300c802, 0x0300c802, 0x0300c802},
+       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x0300cc03, 0x0300cc03},
+       {0x0000a628, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
+       {0x0000a62c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
+       {0x0000a630, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
+       {0x0000a634, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
+       {0x0000a638, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
+       {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
+};
+
+static const u32 ar9331_1p2_baseband_postamble[][5] = {
+       /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
+       {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
+       {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
+       {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
+       {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
+       {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
+       {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
+       {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
+       {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
+       {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
+       {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
+       {0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e},
+       {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
+       {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
+       {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
+       {0x00009e2c, 0x0000001c, 0x0000001c, 0x00003221, 0x00003221},
+       {0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222},
+       {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
+       {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
+       {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
+       {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0},
+       {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
+       {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
+       {0x0000a234, 0x00000fff, 0x00000fff, 0x10000fff, 0x00000fff},
+       {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
+       {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
+       {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
+       {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
+       {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
+       {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
+       {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
+       {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
+       {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
+       {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981},
+       {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
+       {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
+       {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+};
+
+static const u32 ar9331_modes_high_ob_db_tx_gain_1p2[][5] = {
+       /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
+       {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
+       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
+       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
+       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
+       {0x0000a52c, 0x41023e85, 0x41023e85, 0x3f001620, 0x3f001620},
+       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x41001621, 0x41001621},
+       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x44001640, 0x44001640},
+       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x46001641, 0x46001641},
+       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x48001642, 0x48001642},
+       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x4b001644, 0x4b001644},
+       {0x0000a544, 0x6502feca, 0x6502feca, 0x4e001a81, 0x4e001a81},
+       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x51001a83, 0x51001a83},
+       {0x0000a54c, 0x7203feca, 0x7203feca, 0x54001c84, 0x54001c84},
+       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x57001ce3, 0x57001ce3},
+       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x5b001ce5, 0x5b001ce5},
+       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5f001ce9, 0x5f001ce9},
+       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x66001eec, 0x66001eec},
+       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x66001eec, 0x66001eec},
+       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+       {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+       {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+       {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
+       {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
+       {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
+       {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
+       {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
+       {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
+       {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
+       {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
+       {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
+       {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
+       {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
+       {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
+       {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
+       {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
+       {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
+       {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
+       {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
+       {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
+       {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
+       {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
+       {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
+       {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
+       {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
+       {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
+       {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+       {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
+       {0x0000a618, 0x02008501, 0x02008501, 0x02008501, 0x02008501},
+       {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
+       {0x0000a620, 0x0300c802, 0x0300c802, 0x0300c802, 0x0300c802},
+       {0x0000a624, 0x0300cc03, 0x0300cc03, 0x0300cc03, 0x0300cc03},
+       {0x0000a628, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
+       {0x0000a62c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
+       {0x0000a630, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
+       {0x0000a634, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
+       {0x0000a638, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
+       {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
+};
+
+static const u32 ar9331_modes_low_ob_db_tx_gain_1p2[][5] = {
+       /*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
+       {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
+       {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+       {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+       {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+       {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+       {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+       {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+       {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+       {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+       {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
+       {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
+       {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
+       {0x0000a52c, 0x41023e85, 0x41023e85, 0x3f001620, 0x3f001620},
+       {0x0000a530, 0x48023ec6, 0x48023ec6, 0x41001621, 0x41001621},
+       {0x0000a534, 0x4d023f01, 0x4d023f01, 0x44001640, 0x44001640},
+       {0x0000a538, 0x53023f4b, 0x53023f4b, 0x46001641, 0x46001641},
+       {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x48001642, 0x48001642},
+       {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x4b001644, 0x4b001644},
+       {0x0000a544, 0x6502feca, 0x6502feca, 0x4e001a81, 0x4e001a81},
+       {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x51001a83, 0x51001a83},
+       {0x0000a54c, 0x7203feca, 0x7203feca, 0x54001c84, 0x54001c84},
+       {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x57001ce3, 0x57001ce3},
+       {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x5b001ce5, 0x5b001ce5},
+       {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5f001ce9, 0x5f001ce9},
+       {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x66001eec, 0x66001eec},
+       {0x0000a560, 0x900fff0b, 0x900fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a564, 0x960fffcb, 0x960fffcb, 0x66001eec, 0x66001eec},
+       {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
+       {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},