ARM: tegra: soctherm: Enable THERMTRIP
Joshua Primero [Fri, 28 Sep 2012 20:51:52 +0000 (13:51 -0700)]
Exposed platform data to cause CPU/GPU/MEM/TSENSE shutdown based on
thresholds

Change-Id: I3f53ea6ef062d61c86915af03360f703f3ee6257
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/139828
(cherry picked from commit d5f29d91e4ed963c43bd61b0c8bbb31ccfbe2e75)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146682
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/board-dalmore-power.c
arch/arm/mach-tegra/board-pluto-power.c
arch/arm/mach-tegra/tegra11_soctherm.c
arch/arm/mach-tegra/tegra11_soctherm.h

index 7f71ec6..0ecad49 100644 (file)
@@ -1108,13 +1108,18 @@ int __init dalmore_edp_init(void)
 }
 
 static struct soctherm_platform_data dalmore_soctherm_data = {
-       .therm_trip = 90,
+       .thermtrip = {
+               [THERM_CPU] = 90,
+               [THERM_GPU] = 0, /* Not enabled */
+               [THERM_MEM] = 0, /* Not enabled */
+               [THERM_PLL] = 0, /* Not enabled */
+       },
+
        .hw_backstop = 60,
        .dividend = 1,
        .divisor = 2,
        .duration = 1,
        .step = 1,
-
        .sensor_data = {
                [TSENSE_CPU0] = {
                        .enable = true,
@@ -1124,6 +1129,7 @@ static struct soctherm_platform_data dalmore_soctherm_data = {
                        .tiddq = 1,
                        .ten_count = 1,
                        .tsample = 163,
+                       .pdiv = 10,
                },
                [TSENSE_CPU1] = {
                        .enable = true,
@@ -1133,6 +1139,7 @@ static struct soctherm_platform_data dalmore_soctherm_data = {
                        .tiddq = 1,
                        .ten_count = 1,
                        .tsample = 163,
+                       .pdiv = 10,
                },
                [TSENSE_CPU2] = {
                        .enable = true,
@@ -1141,7 +1148,8 @@ static struct soctherm_platform_data dalmore_soctherm_data = {
                        .tall = 16300,
                        .tiddq = 1,
                        .ten_count = 1,
-                       .tsample = 163
+                       .tsample = 163,
+                       .pdiv = 10,
                },
                [TSENSE_CPU3] = {
                        .enable = true,
@@ -1150,7 +1158,8 @@ static struct soctherm_platform_data dalmore_soctherm_data = {
                        .tall = 16300,
                        .tiddq = 1,
                        .ten_count = 1,
-                       .tsample = 163
+                       .tsample = 163,
+                       .pdiv = 10,
                },
                [TSENSE_MEM0] = {
                        .enable = true,
@@ -1159,7 +1168,8 @@ static struct soctherm_platform_data dalmore_soctherm_data = {
                        .tall = 16300,
                        .tiddq = 1,
                        .ten_count = 1,
-                       .tsample = 163
+                       .tsample = 163,
+                       .pdiv = 10,
                },
                [TSENSE_MEM1] = {
                        .enable = true,
@@ -1168,7 +1178,8 @@ static struct soctherm_platform_data dalmore_soctherm_data = {
                        .tall = 16300,
                        .tiddq = 1,
                        .ten_count = 1,
-                       .tsample = 163
+                       .tsample = 163,
+                       .pdiv = 10,
                },
                [TSENSE_GPU] = {
                        .enable = true,
@@ -1177,7 +1188,8 @@ static struct soctherm_platform_data dalmore_soctherm_data = {
                        .tall = 16300,
                        .tiddq = 1,
                        .ten_count = 1,
-                       .tsample = 163
+                       .tsample = 163,
+                       .pdiv = 10,
                },
                [TSENSE_PLLX] = {
                        .enable = true,
@@ -1186,7 +1198,8 @@ static struct soctherm_platform_data dalmore_soctherm_data = {
                        .tall = 16300,
                        .tiddq = 1,
                        .ten_count = 1,
-                       .tsample = 163
+                       .tsample = 163,
+                       .pdiv = 10,
                },
        },
 };
index 58934fc..05b07fe 100644 (file)
@@ -694,13 +694,18 @@ int __init pluto_edp_init(void)
 }
 
 static struct soctherm_platform_data pluto_soctherm_data = {
-       .therm_trip = 90,
+       .thermtrip = {
+               [THERM_CPU] = 90,
+               [THERM_GPU] = 0, /* Not enabled */
+               [THERM_MEM] = 0, /* Not enabled */
+               [THERM_PLL] = 0, /* Not enabled */
+       },
+
        .hw_backstop = 60,
        .dividend = 1,
        .divisor = 2,
        .duration = 1,
        .step = 1,
-
        .sensor_data = {
                [TSENSE_CPU0] = {
                        .enable = true,
@@ -710,6 +715,7 @@ static struct soctherm_platform_data pluto_soctherm_data = {
                        .tiddq = 1,
                        .ten_count = 1,
                        .tsample = 163,
+                       .pdiv = 10,
                },
                [TSENSE_CPU1] = {
                        .enable = true,
@@ -719,6 +725,7 @@ static struct soctherm_platform_data pluto_soctherm_data = {
                        .tiddq = 1,
                        .ten_count = 1,
                        .tsample = 163,
+                       .pdiv = 10,
                },
                [TSENSE_CPU2] = {
                        .enable = true,
@@ -727,7 +734,8 @@ static struct soctherm_platform_data pluto_soctherm_data = {
                        .tall = 16300,
                        .tiddq = 1,
                        .ten_count = 1,
-                       .tsample = 163
+                       .tsample = 163,
+                       .pdiv = 10,
                },
                [TSENSE_CPU3] = {
                        .enable = true,
@@ -736,7 +744,8 @@ static struct soctherm_platform_data pluto_soctherm_data = {
                        .tall = 16300,
                        .tiddq = 1,
                        .ten_count = 1,
-                       .tsample = 163
+                       .tsample = 163,
+                       .pdiv = 10,
                },
                [TSENSE_MEM0] = {
                        .enable = true,
@@ -745,7 +754,8 @@ static struct soctherm_platform_data pluto_soctherm_data = {
                        .tall = 16300,
                        .tiddq = 1,
                        .ten_count = 1,
-                       .tsample = 163
+                       .tsample = 163,
+                       .pdiv = 10,
                },
                [TSENSE_MEM1] = {
                        .enable = true,
@@ -754,7 +764,8 @@ static struct soctherm_platform_data pluto_soctherm_data = {
                        .tall = 16300,
                        .tiddq = 1,
                        .ten_count = 1,
-                       .tsample = 163
+                       .tsample = 163,
+                       .pdiv = 10,
                },
                [TSENSE_GPU] = {
                        .enable = true,
@@ -763,7 +774,8 @@ static struct soctherm_platform_data pluto_soctherm_data = {
                        .tall = 16300,
                        .tiddq = 1,
                        .ten_count = 1,
-                       .tsample = 163
+                       .tsample = 163,
+                       .pdiv = 10,
                },
                [TSENSE_PLLX] = {
                        .enable = true,
@@ -772,7 +784,8 @@ static struct soctherm_platform_data pluto_soctherm_data = {
                        .tall = 16300,
                        .tiddq = 1,
                        .ten_count = 1,
-                       .tsample = 163
+                       .tsample = 163,
+                       .pdiv = 10,
                },
        },
 };
index d08082e..6ad627c 100644 (file)
 
 #define THERMTRIP                      0x80
 #define THERMTRIP_ANY_EN_SHIFT         28
-
-#define THERMTRIP                      0x80
-#define THERMTRIP_ANY_EN_SHIFT         28
 #define THERMTRIP_ANY_EN_MASK          0x1
+#define THERMTRIP_MEM_EN_SHIFT         27
+#define THERMTRIP_MEM_EN_MASK          0x1
+#define THERMTRIP_GPU_EN_SHIFT         26
+#define THERMTRIP_GPU_EN_MASK          0x1
 #define THERMTRIP_CPU_EN_SHIFT         25
 #define THERMTRIP_CPU_EN_MASK          0x1
+#define THERMTRIP_TSENSE_EN_SHIFT      24
+#define THERMTRIP_TSENSE_EN_MASK       0x1
+#define THERMTRIP_GPUMEM_THRESH_SHIFT  16
+#define THERMTRIP_GPUMEM_THRESH_MASK   0xff
 #define THERMTRIP_CPU_THRESH_SHIFT     8
 #define THERMTRIP_CPU_THRESH_MASK      0xff
+#define THERMTRIP_TSENSE_THRESH_SHIFT  0
+#define THERMTRIP_TSENSE_THRESH_MASK   0xff
 
 #define TS_CPU0_CONFIG0                                0xc0
 #define TS_CPU0_CONFIG0_TALL_SHIFT             8
        (((r)&(_name##_MASK<<_name##_SHIFT))>>_name##_SHIFT)
 
 static void __iomem *reg_soctherm_base = IO_ADDRESS(TEGRA_SOCTHERM_BASE);
+static void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+
+#define pmc_writel(value, reg) __raw_writel(value, (u32)pmc_base + (reg))
+#define pmc_readl(reg) __raw_readl((u32)pmc_base + (reg))
 
 #define soctherm_writel(value, reg) \
        __raw_writel(value, (u32)reg_soctherm_base + (reg))
@@ -243,6 +254,7 @@ static inline long temp_translate(int readback)
        return (abs * 1000 + lsb * 500) * (sign * -2 + 1);
 }
 
+#if 0
 static int soctherm_set_limits(void *data,
        long lo_limit_milli,
        long hi_limit_milli)
@@ -257,6 +269,7 @@ static int soctherm_set_limits(void *data,
 
        return 0;
 }
+#endif
 
 #ifdef CONFIG_THERMAL
 static int soctherm_bind(struct thermal_zone_device *thz,
@@ -351,6 +364,12 @@ int __init tegra11_soctherm_init(struct soctherm_platform_data *data)
 {
        int err, i;
        u32 r;
+       char name[64];
+
+       /* Can only thermtrip with either GPU or MEM but not both */
+       if (data->thermtrip[THERM_GPU] && data->thermtrip[THERM_MEM])
+               return -EINVAL;
+
 
        memcpy(&plat_data, data, sizeof(struct soctherm_platform_data));
 
@@ -358,10 +377,11 @@ int __init tegra11_soctherm_init(struct soctherm_platform_data *data)
        for (i = 0; i < TSENSE_SIZE; i++) {
                if (plat_data.sensor_data[i].enable) {
                        soctherm_tsense_program(i, &plat_data.sensor_data[i]);
+                       sprintf(name, "%s-tsensor", sensor_names[i]);
 #ifdef CONFIG_THERMAL
                        /* Create a thermal zone device for each sensor */
                        thermal_zone_device_register(
-                                       sensor_names[i],
+                                       name,
                                        0,
                                        0,
                                        (void *)i,
@@ -374,6 +394,15 @@ int __init tegra11_soctherm_init(struct soctherm_platform_data *data)
                }
        }
 
+       /* Pdiv */
+       r = soctherm_readl(TS_PDIV);
+       r = REG_SET(r, TS_PDIV_CPU, data->sensor_data[TSENSE_CPU0].pdiv);
+       r = REG_SET(r, TS_PDIV_GPU, data->sensor_data[TSENSE_GPU].pdiv);
+       r = REG_SET(r, TS_PDIV_CPU, data->sensor_data[TSENSE_MEM0].pdiv);
+       r = REG_SET(r, TS_PDIV_CPU, data->sensor_data[TSENSE_PLLX].pdiv);
+       soctherm_writel(r, TS_PDIV);
+
+
        /* Enable Level 0 */
        r = soctherm_readl(CTL_LVL0_CPU0);
        r = REG_SET(r, CTL_LVL0_CPU0_EN, 1);
@@ -390,26 +419,25 @@ int __init tegra11_soctherm_init(struct soctherm_platform_data *data)
 #endif
 
        /* Thermtrip */
-       r = soctherm_readl(THERMTRIP);
-       r = REG_SET(r, THERMTRIP_CPU_THRESH, data->therm_trip);
-       r = REG_SET(r, THERMTRIP_CPU_EN, 1);
+       r = REG_SET(0, THERMTRIP_CPU_EN, !!data->thermtrip[THERM_CPU]);
+       r = REG_SET(r, THERMTRIP_GPU_EN, !!data->thermtrip[THERM_GPU]);
+       r = REG_SET(r, THERMTRIP_MEM_EN, !!data->thermtrip[THERM_MEM]);
+       r = REG_SET(r, THERMTRIP_TSENSE_EN, !!data->thermtrip[THERM_PLL]);
+       r = REG_SET(r, THERMTRIP_CPU_THRESH, data->thermtrip[THERM_CPU]);
+       r = REG_SET(r, THERMTRIP_GPUMEM_THRESH, data->thermtrip[THERM_GPU] |
+                                               data->thermtrip[THERM_MEM]);
+       r = REG_SET(r, THERMTRIP_TSENSE_THRESH, data->thermtrip[THERM_PLL]);
        soctherm_writel(r, THERMTRIP);
 
-       /* Pdiv */
-       r = soctherm_readl(TS_PDIV);
-       r = REG_SET(r, TS_PDIV_CPU, 10);
-       r = REG_SET(r, TS_PDIV_GPU, 10);
-       r = REG_SET(r, TS_PDIV_MEM, 10);
-       r = REG_SET(r, TS_PDIV_PLLX, 10);
-       soctherm_writel(r, TS_PDIV);
+       /* Enable PMC to shutdown */
+       r = pmc_readl(0x1b0);
+       r |= 0x2;
+       pmc_writel(r, 0x1b0);
 
-       err = request_irq(INT_THERMAL, soctherm_isr,
-                               0, "soctherm", NULL);
+       err = request_irq(INT_THERMAL, soctherm_isr, 0, "soctherm", NULL);
        if (err < 0)
                return -1;
 
-       soctherm_set_limits(NULL, 20000, 38000);
-
        return 0;
 }
 
@@ -527,6 +555,13 @@ static int regs_show(struct seq_file *s, void *data)
        r = soctherm_readl(PSKIP_STATUS);
        seq_printf(s, "PSKIP: 0x%x\n", r);
 
+       r = soctherm_readl(THERMTRIP);
+       seq_printf(s, "THERMTRIP: 0x%x\n", r);
+       state = REG_GET(r, THERMTRIP_CPU_THRESH);
+       seq_printf(s, "THERMTRIP_CPU_THRESH: %d ", state);
+       state = REG_GET(r, THERMTRIP_CPU_EN);
+       seq_printf(s, "%d\n", state);
+
        return 0;
 }
 
index dee321d..06691ed 100644 (file)
@@ -65,10 +65,11 @@ struct soctherm_sensor {
        int tsample;
        s16 therm_a;
        s16 therm_b;
+       u8 pdiv;
 };
 
 struct soctherm_platform_data {
-       int therm_trip; /* in celcius */
+       s8 thermtrip[THERM_SIZE];
 
        int hw_backstop; /* in celcius */
        int dividend;