arm: tegra: pl310: Enable dynamic clock gating and standy.
Krishna Reddy [Mon, 14 May 2012 10:20:55 +0000 (15:20 +0530)]
Bug 947861

Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/100462
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Change-Id: I9770a96622e37176322c2941e665e5e677a5c8ed

arch/arm/mach-tegra/common.c

index e81c7d9..d2f33c7 100644 (file)
@@ -424,6 +424,7 @@ void tegra_init_cache(bool init)
 #endif
 #endif
 
+       writel(0x3, p + L2X0_POWER_CTRL);
        cache_type = readl(p + L2X0_CACHE_TYPE);
        aux_ctrl = (cache_type & 0x700) << (17-8);
        aux_ctrl |= 0x7C400001;