Merge branch 'for-davem' of ssh://master.kernel.org/pub/scm/linux/kernel/git/linville...
David S. Miller [Fri, 4 Mar 2011 20:48:25 +0000 (12:48 -0800)]
374 files changed:
.gitignore
Documentation/DocBook/filesystems.tmpl
Documentation/hwmon/jc42
Documentation/hwmon/k10temp
Documentation/kernel-parameters.txt
Documentation/networking/00-INDEX
Documentation/networking/dns_resolver.txt
MAINTAINERS
Makefile
arch/alpha/Kconfig
arch/alpha/kernel/irq.c
arch/alpha/kernel/irq_alpha.c
arch/alpha/kernel/irq_i8259.c
arch/alpha/kernel/irq_impl.h
arch/alpha/kernel/irq_pyxis.c
arch/alpha/kernel/irq_srm.c
arch/alpha/kernel/sys_alcor.c
arch/alpha/kernel/sys_cabriolet.c
arch/alpha/kernel/sys_dp264.c
arch/alpha/kernel/sys_eb64p.c
arch/alpha/kernel/sys_eiger.c
arch/alpha/kernel/sys_jensen.c
arch/alpha/kernel/sys_marvel.c
arch/alpha/kernel/sys_mikasa.c
arch/alpha/kernel/sys_noritake.c
arch/alpha/kernel/sys_rawhide.c
arch/alpha/kernel/sys_rx164.c
arch/alpha/kernel/sys_sable.c
arch/alpha/kernel/sys_takara.c
arch/alpha/kernel/sys_titan.c
arch/alpha/kernel/sys_wildfire.c
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/boot/compressed/.gitignore
arch/arm/include/asm/hardware/cache-l2x0.h
arch/arm/include/asm/hardware/sp810.h
arch/arm/include/asm/tlb.h
arch/arm/include/asm/tlbflush.h
arch/arm/kernel/kprobes-decode.c
arch/arm/kernel/pmu.c
arch/arm/kernel/setup.c
arch/arm/kernel/signal.c
arch/arm/kernel/vmlinux.lds.S
arch/arm/mach-omap2/clkt_dpll.c
arch/arm/mach-omap2/mailbox.c
arch/arm/mach-omap2/mux.c
arch/arm/mach-omap2/pm-debug.c
arch/arm/mach-omap2/prcm_mpu44xx.h
arch/arm/mach-omap2/smartreflex.c
arch/arm/mach-omap2/timer-gp.c
arch/arm/mach-s5p6442/include/mach/map.h
arch/arm/mach-s5p64x0/include/mach/map.h
arch/arm/mach-s5pc100/include/mach/map.h
arch/arm/mach-s5pv210/include/mach/map.h
arch/arm/mach-s5pv210/mach-aquila.c
arch/arm/mach-s5pv210/mach-goni.c
arch/arm/mach-s5pv310/include/mach/map.h
arch/arm/mach-spear3xx/include/mach/spear320.h
arch/arm/mach-tegra/include/mach/kbc.h
arch/arm/mm/cache-l2x0.c
arch/arm/mm/proc-v7.S
arch/arm/plat-omap/mailbox.c
arch/arm/plat-s5p/dev-uart.c
arch/arm/plat-samsung/dev-ts.c
arch/arm/plat-spear/include/plat/uncompress.h
arch/arm/plat-spear/include/plat/vmalloc.h
arch/cris/kernel/vmlinux.lds.S
arch/powerpc/include/asm/machdep.h
arch/powerpc/kernel/machine_kexec.c
arch/powerpc/kernel/process.c
arch/powerpc/mm/tlb_hash64.c
arch/s390/boot/compressed/misc.c
arch/s390/include/asm/atomic.h
arch/s390/include/asm/cache.h
arch/x86/include/asm/acpi.h
arch/x86/include/asm/msr-index.h
arch/x86/include/asm/perf_event_p4.h
arch/x86/include/asm/smpboot_hooks.h
arch/x86/kernel/acpi/boot.c
arch/x86/kernel/apb_timer.c
arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
arch/x86/kernel/cpu/cpufreq/powernow-k8.c
arch/x86/kernel/cpu/perf_event_p4.c
arch/x86/kernel/early-quirks.c
arch/x86/kernel/reboot.c
arch/x86/kvm/svm.c
arch/x86/platform/olpc/olpc_dt.c
block/blk-core.c
block/blk-flush.c
block/blk-lib.c
block/blk-throttle.c
block/cfq-iosched.c
block/elevator.c
block/genhd.c
block/ioctl.c
drivers/acpi/acpica/aclocal.h
drivers/acpi/acpica/evgpe.c
drivers/acpi/acpica/evxfgpe.c
drivers/acpi/debugfs.c
drivers/block/drbd/drbd_nl.c
drivers/block/floppy.c
drivers/block/loop.c
drivers/bluetooth/btusb.c
drivers/char/agp/amd64-agp.c
drivers/char/agp/intel-agp.h
drivers/char/agp/intel-gtt.c
drivers/char/pcmcia/cm4000_cs.c
drivers/char/pcmcia/ipwireless/main.c
drivers/char/tpm/tpm.c
drivers/char/tpm/tpm.h
drivers/char/tpm/tpm_tis.c
drivers/cpufreq/cpufreq.c
drivers/gpu/drm/drm_irq.c
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_gem_tiling.c
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_panel.c
drivers/gpu/drm/nouveau/nouveau_bo.c
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/radeon_display.c
drivers/gpu/drm/radeon/radeon_fb.c
drivers/hwmon/Kconfig
drivers/hwmon/ad7414.c
drivers/hwmon/adt7411.c
drivers/hwmon/jc42.c
drivers/hwmon/k10temp.c
drivers/hwmon/lm85.c
drivers/i2c/busses/i2c-omap.c
drivers/i2c/busses/i2c-stu300.c
drivers/idle/intel_idle.c
drivers/input/gameport/gameport.c
drivers/input/keyboard/tegra-kbc.c
drivers/input/mouse/synaptics.h
drivers/input/serio/serio.c
drivers/isdn/hardware/eicon/istream.c
drivers/md/dm-log-userspace-transfer.c
drivers/md/linear.c
drivers/md/md.c
drivers/md/md.h
drivers/md/multipath.c
drivers/md/raid0.c
drivers/md/raid1.c
drivers/md/raid10.c
drivers/md/raid5.c
drivers/mfd/asic3.c
drivers/mfd/davinci_voicecodec.c
drivers/mfd/tps6586x.c
drivers/mfd/ucb1x00-ts.c
drivers/mfd/wm8994-core.c
drivers/net/Kconfig
drivers/net/Makefile
drivers/net/benet/be_main.c
drivers/net/bnx2x/bnx2x.h
drivers/net/bnx2x/bnx2x_cmn.c
drivers/net/bnx2x/bnx2x_cmn.h
drivers/net/bnx2x/bnx2x_ethtool.c
drivers/net/bnx2x/bnx2x_init.h
drivers/net/bnx2x/bnx2x_main.c
drivers/net/bnx2x/bnx2x_stats.c
drivers/net/can/softing/softing_main.c
drivers/net/cnic.c
drivers/net/davinci_emac.c
drivers/net/dm9000.c
drivers/net/dnet.c
drivers/net/e1000/e1000_osdep.h
drivers/net/e1000e/netdev.c
drivers/net/eql.c
drivers/net/fec.c
drivers/net/ftmac100.c [new file with mode: 0644]
drivers/net/ftmac100.h [new file with mode: 0644]
drivers/net/igbvf/vf.c
drivers/net/macb.c
drivers/net/mii.c
drivers/net/mv643xx_eth.c
drivers/net/pcmcia/fmvj18x_cs.c
drivers/net/r8169.c
drivers/net/sfc/ethtool.c
drivers/net/skge.c
drivers/net/tlan.c
drivers/net/tun.c
drivers/net/usb/dm9601.c
drivers/net/wireless/ath/ath9k/hif_usb.c
drivers/net/wireless/ath/ath9k/mac.c
drivers/net/wireless/ath/carl9170/usb.c
drivers/net/wireless/iwlwifi/iwl-5000.c
drivers/net/wireless/p54/p54pci.c
drivers/net/wireless/p54/p54usb.c
drivers/net/wireless/rndis_wlan.c
drivers/nfc/Kconfig
drivers/nfc/pn544.c
drivers/of/pdt.c
drivers/pcmcia/pcmcia_resource.c
drivers/pcmcia/pxa2xx_base.c
drivers/pcmcia/pxa2xx_base.h
drivers/pcmcia/pxa2xx_lubbock.c
drivers/platform/x86/Kconfig
drivers/platform/x86/acer-wmi.c
drivers/platform/x86/asus_acpi.c
drivers/platform/x86/dell-laptop.c
drivers/platform/x86/intel_pmic_gpio.c
drivers/platform/x86/tc1100-wmi.c
drivers/platform/x86/thinkpad_acpi.c
drivers/pps/kapi.c
drivers/rapidio/rio-sysfs.c
drivers/regulator/mc13xxx-regulator-core.c
drivers/regulator/wm831x-dcdc.c
drivers/rtc/rtc-at91sam9.c
drivers/rtc/rtc-ds3232.c
drivers/s390/block/dasd_eckd.c
drivers/scsi/scsi_lib.c
drivers/scsi/scsi_transport_fc.c
drivers/staging/pohmelfs/config.c
drivers/thermal/Kconfig
drivers/thermal/thermal_sys.c
drivers/tty/serial/serial_cs.c
drivers/usb/core/hub.c
drivers/usb/core/quirks.c
drivers/usb/gadget/f_phonet.c
drivers/usb/host/ehci-xilinx-of.c
drivers/usb/host/xhci-dbg.c
drivers/usb/host/xhci-mem.c
drivers/usb/host/xhci-ring.c
drivers/usb/host/xhci.c
drivers/usb/host/xhci.h
drivers/usb/musb/musb_core.c
drivers/usb/musb/musb_core.h
drivers/usb/musb/omap2430.c
drivers/usb/serial/sierra.c
drivers/usb/serial/usb_wwan.c
drivers/usb/serial/visor.c
drivers/video/uvesafb.c
fs/afs/write.c
fs/aio.c
fs/block_dev.c
fs/btrfs/ctree.h
fs/btrfs/extent-tree.c
fs/btrfs/extent_io.c
fs/btrfs/extent_io.h
fs/btrfs/inode.c
fs/btrfs/ioctl.c
fs/btrfs/lzo.c
fs/btrfs/relocation.c
fs/btrfs/super.c
fs/btrfs/volumes.c
fs/ceph/dir.c
fs/ceph/snap.c
fs/ceph/super.h
fs/cifs/cifsfs.h
fs/cifs/netmisc.c
fs/cifs/sess.c
fs/ecryptfs/dentry.c
fs/ecryptfs/ecryptfs_kernel.h
fs/ecryptfs/file.c
fs/ecryptfs/inode.c
fs/eventfd.c
fs/eventpoll.c
fs/exofs/namei.c
fs/ext2/namei.c
fs/fuse/dir.c
fs/fuse/file.c
fs/fuse/fuse_i.h
fs/gfs2/main.c
fs/hfs/dir.c
fs/inode.c
fs/internal.h
fs/minix/namei.c
fs/namespace.c
fs/nilfs2/btnode.c
fs/nilfs2/btnode.h
fs/nilfs2/mdt.c
fs/nilfs2/namei.c
fs/nilfs2/page.c
fs/nilfs2/page.h
fs/nilfs2/segment.c
fs/nilfs2/super.c
fs/ocfs2/journal.h
fs/ocfs2/refcounttree.c
fs/ocfs2/super.c
fs/partitions/ldm.c
fs/proc/proc_devtree.c
fs/reiserfs/namei.c
fs/sysv/namei.c
fs/udf/namei.c
fs/ufs/namei.c
fs/xfs/linux-2.6/xfs_discard.c
fs/xfs/linux-2.6/xfs_ioctl.c
fs/xfs/xfs_fsops.c
include/asm-generic/pgtable.h
include/drm/drmP.h
include/keys/rxrpc-type.h
include/linux/blkdev.h
include/linux/blktrace_api.h
include/linux/fs.h
include/linux/mfd/wm8994/core.h
include/linux/module.h
include/linux/netlink.h
include/linux/pm.h
include/linux/pm_wakeup.h
include/linux/rio_regs.h
include/linux/thermal.h
include/net/ipv6.h
include/net/sch_generic.h
include/pcmcia/ds.h
include/sound/wm8903.h
include/trace/events/block.h
kernel/irq/internals.h
kernel/irq/irqdesc.c
kernel/irq/manage.c
kernel/irq/resend.c
kernel/perf_event.c
kernel/time/tick-broadcast.c
kernel/time/tick-common.c
kernel/time/tick-internal.h
kernel/trace/blktrace.c
lib/nlattr.c
lib/swiotlb.c
mm/memory.c
mm/mempolicy.c
mm/migrate.c
mm/mremap.c
mm/page_alloc.c
mm/swapfile.c
mm/truncate.c
mm/vmscan.c
net/bridge/br_multicast.c
net/ceph/messenger.c
net/core/dev_addr_lists.c
net/dcb/dcbnl.c
net/dccp/input.c
net/dns_resolver/dns_key.c
net/ipv4/tcp_input.c
net/ipv4/tcp_output.c
net/ipv6/route.c
net/mac80211/iface.c
net/netfilter/ipvs/ip_vs_ctl.c
net/netfilter/nf_log.c
net/netlink/af_netlink.c
net/rxrpc/ar-input.c
net/rxrpc/ar-key.c
net/sched/sch_generic.c
net/wireless/wext-compat.c
scripts/basic/fixdep.c
security/commoncap.c
sound/core/jack.c
sound/pci/au88x0/au88x0_core.c
sound/pci/hda/hda_intel.c
sound/pci/hda/patch_conexant.c
sound/pci/hda/patch_sigmatel.c
sound/pci/hda/patch_via.c
sound/soc/codecs/cx20442.c
sound/soc/codecs/wm8903.c
sound/soc/codecs/wm8903.h
sound/soc/codecs/wm8994.c
sound/soc/codecs/wm_hubs.c
sound/soc/imx/eukrea-tlv320.c
sound/soc/pxa/e740_wm9705.c
sound/soc/pxa/e750_wm9705.c
sound/soc/pxa/e800_wm9712.c
sound/soc/pxa/em-x270.c
sound/soc/pxa/mioa701_wm9713.c
sound/soc/pxa/palm27x.c
sound/soc/pxa/tosa.c
sound/soc/pxa/zylonite.c
sound/soc/soc-dapm.c
sound/usb/caiaq/audio.c
sound/usb/caiaq/midi.c
sound/usb/card.c
sound/usb/pcm.c
sound/usb/usbaudio.h
tools/perf/builtin-timechart.c
tools/perf/util/hist.c
tools/perf/util/svghelper.c

index 8faa6c0..5d56a3f 100644 (file)
@@ -28,6 +28,7 @@ modules.builtin
 *.gz
 *.bz2
 *.lzma
+*.xz
 *.lzo
 *.patch
 *.gcno
index 5e87ad5..f51f285 100644 (file)
      </sect1>
   </chapter>
 
+  <chapter id="fs_events">
+     <title>Events based on file descriptors</title>
+!Efs/eventfd.c
+  </chapter>
+
   <chapter id="sysfs">
      <title>The Filesystem for Exporting Kernel Objects</title>
 !Efs/sysfs/file.c
index 0e76ef1..a22ecf4 100644 (file)
@@ -51,7 +51,8 @@ Supported chips:
   * JEDEC JC 42.4 compliant temperature sensor chips
     Prefix: 'jc42'
     Addresses scanned: I2C 0x18 - 0x1f
-    Datasheet: -
+    Datasheet:
+       http://www.jedec.org/sites/default/files/docs/4_01_04R19.pdf
 
 Author:
        Guenter Roeck <guenter.roeck@ericsson.com>
@@ -60,7 +61,11 @@ Author:
 Description
 -----------
 
-This driver implements support for JEDEC JC 42.4 compliant temperature sensors.
+This driver implements support for JEDEC JC 42.4 compliant temperature sensors,
+which are used on many DDR3 memory modules for mobile devices and servers. Some
+systems use the sensor to prevent memory overheating by automatically throttling
+the memory controller.
+
 The driver auto-detects the chips listed above, but can be manually instantiated
 to support other JC 42.4 compliant chips.
 
@@ -81,15 +86,19 @@ limits. The chip supports only a single register to configure the hysteresis,
 which applies to all limits. This register can be written by writing into
 temp1_crit_hyst. Other hysteresis attributes are read-only.
 
+If the BIOS has configured the sensor for automatic temperature management, it
+is likely that it has locked the registers, i.e., that the temperature limits
+cannot be changed.
+
 Sysfs entries
 -------------
 
 temp1_input            Temperature (RO)
-temp1_min              Minimum temperature (RW)
-temp1_max              Maximum temperature (RW)
-temp1_crit             Critical high temperature (RW)
+temp1_min              Minimum temperature (RO or RW)
+temp1_max              Maximum temperature (RO or RW)
+temp1_crit             Critical high temperature (RO or RW)
 
-temp1_crit_hyst                Critical hysteresis temperature (RW)
+temp1_crit_hyst                Critical hysteresis temperature (RO or RW)
 temp1_max_hyst         Maximum hysteresis temperature (RO)
 
 temp1_min_alarm                Temperature low alarm
index 6526eee..d2b56a4 100644 (file)
@@ -9,6 +9,8 @@ Supported chips:
   Socket S1G3: Athlon II, Sempron, Turion II
 * AMD Family 11h processors:
   Socket S1G2: Athlon (X2), Sempron (X2), Turion X2 (Ultra)
+* AMD Family 12h processors: "Llano"
+* AMD Family 14h processors: "Brazos" (C/E/G-Series)
 
   Prefix: 'k10temp'
   Addresses scanned: PCI space
@@ -17,10 +19,14 @@ Supported chips:
     http://support.amd.com/us/Processor_TechDocs/31116.pdf
   BIOS and Kernel Developer's Guide (BKDG) for AMD Family 11h Processors:
     http://support.amd.com/us/Processor_TechDocs/41256.pdf
+  BIOS and Kernel Developer's Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors:
+    http://support.amd.com/us/Processor_TechDocs/43170.pdf
   Revision Guide for AMD Family 10h Processors:
     http://support.amd.com/us/Processor_TechDocs/41322.pdf
   Revision Guide for AMD Family 11h Processors:
     http://support.amd.com/us/Processor_TechDocs/41788.pdf
+  Revision Guide for AMD Family 14h Models 00h-0Fh Processors:
+    http://support.amd.com/us/Processor_TechDocs/47534.pdf
   AMD Family 11h Processor Power and Thermal Data Sheet for Notebooks:
     http://support.amd.com/us/Processor_TechDocs/43373.pdf
   AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet:
@@ -34,7 +40,7 @@ Description
 -----------
 
 This driver permits reading of the internal temperature sensor of AMD
-Family 10h and 11h processors.
+Family 10h/11h/12h/14h processors.
 
 All these processors have a sensor, but on those for Socket F or AM2+,
 the sensor may return inconsistent values (erratum 319).  The driver
index 89835a4..f4a04c0 100644 (file)
@@ -144,6 +144,11 @@ a fixed number of characters. This limit depends on the architecture
 and is between 256 and 4096 characters. It is defined in the file
 ./include/asm/setup.h as COMMAND_LINE_SIZE.
 
+Finally, the [KMG] suffix is commonly described after a number of kernel
+parameter values. These 'K', 'M', and 'G' letters represent the _binary_
+multipliers 'Kilo', 'Mega', and 'Giga', equalling 2^10, 2^20, and 2^30
+bytes respectively. Such letter suffixes can also be entirely omitted.
+
 
        acpi=           [HW,ACPI,X86]
                        Advanced Configuration and Power Interface
@@ -545,16 +550,20 @@ and is between 256 and 4096 characters. It is defined in the file
                        Format:
                        <first_slot>,<last_slot>,<port>,<enum_bit>[,<debug>]
 
-       crashkernel=nn[KMG]@ss[KMG]
-                       [KNL] Reserve a chunk of physical memory to
-                       hold a kernel to switch to with kexec on panic.
+       crashkernel=size[KMG][@offset[KMG]]
+                       [KNL] Using kexec, Linux can switch to a 'crash kernel'
+                       upon panic. This parameter reserves the physical
+                       memory region [offset, offset + size] for that kernel
+                       image. If '@offset' is omitted, then a suitable offset
+                       is selected automatically. Check
+                       Documentation/kdump/kdump.txt for further details.
 
        crashkernel=range1:size1[,range2:size2,...][@offset]
                        [KNL] Same as above, but depends on the memory
                        in the running system. The syntax of range is
                        start-[end] where start and end are both
                        a memory unit (amount[KMG]). See also
-                       Documentation/kdump/kdump.txt for a example.
+                       Documentation/kdump/kdump.txt for an example.
 
        cs89x0_dma=     [HW,NET]
                        Format: <dma>
@@ -1262,10 +1271,9 @@ and is between 256 and 4096 characters. It is defined in the file
                        6 (KERN_INFO)           informational
                        7 (KERN_DEBUG)          debug-level messages
 
-       log_buf_len=n   Sets the size of the printk ring buffer, in bytes.
-                       Format: { n | nk | nM }
-                       n must be a power of two.  The default size
-                       is set in the kernel config file.
+       log_buf_len=n[KMG]      Sets the size of the printk ring buffer,
+                       in bytes.  n must be a power of two.  The default
+                       size is set in the kernel config file.
 
        logo.nologo     [FB] Disables display of the built-in Linux logo.
                        This may be used to provide more screen space for
index fe5c099..4edd78d 100644 (file)
@@ -40,8 +40,6 @@ decnet.txt
        - info on using the DECnet networking layer in Linux.
 depca.txt
        - the Digital DEPCA/EtherWORKS DE1?? and DE2?? LANCE Ethernet driver
-dgrs.txt
-       - the Digi International RightSwitch SE-X Ethernet driver
 dmfe.txt
        - info on the Davicom DM9102(A)/DM9132/DM9801 fast ethernet driver.
 e100.txt
@@ -50,8 +48,6 @@ e1000.txt
        - info on Intel's E1000 line of gigabit ethernet boards
 eql.txt
        - serial IP load balancing
-ethertap.txt
-       - the Ethertap user space packet reception and transmission driver
 ewrk3.txt
        - the Digital EtherWORKS 3 DE203/4/5 Ethernet driver
 filter.txt
@@ -104,8 +100,6 @@ tuntap.txt
        - TUN/TAP device driver, allowing user space Rx/Tx of packets.
 vortex.txt
        - info on using 3Com Vortex (3c590, 3c592, 3c595, 3c597) Ethernet cards.
-wavelan.txt
-       - AT&T GIS (nee NCR) WaveLAN card: An Ethernet-like radio transceiver
 x25.txt
        - general info on X.25 development.
 x25-iface.txt
index aefd1e6..04ca063 100644 (file)
@@ -61,7 +61,6 @@ before the more general line given above as the first match is the one taken.
        create  dns_resolver    foo:*   *       /usr/sbin/dns.foo %k
 
 
-
 =====
 USAGE
 =====
@@ -104,6 +103,14 @@ implemented in the module can be called after doing:
      returned also.
 
 
+===============================
+READING DNS KEYS FROM USERSPACE
+===============================
+
+Keys of dns_resolver type can be read from userspace using keyctl_read() or
+"keyctl read/print/pipe".
+
+
 =========
 MECHANISM
 =========
index 0d83e58..75760e7 100644 (file)
@@ -885,7 +885,7 @@ S:  Supported
 
 ARM/QUALCOMM MSM MACHINE SUPPORT
 M:     David Brown <davidb@codeaurora.org>
-M:     Daniel Walker <dwalker@codeaurora.org>
+M:     Daniel Walker <dwalker@fifo99.com>
 M:     Bryan Huntsman <bryanh@codeaurora.org>
 L:     linux-arm-msm@vger.kernel.org
 F:     arch/arm/mach-msm/
@@ -1467,6 +1467,7 @@ F:        include/net/bluetooth/
 
 BONDING DRIVER
 M:     Jay Vosburgh <fubar@us.ibm.com>
+M:     Andy Gospodarek <andy@greyhouse.net>
 L:     netdev@vger.kernel.org
 W:     http://sourceforge.net/projects/bonding/
 S:     Supported
@@ -1692,6 +1693,13 @@ M:       Andy Whitcroft <apw@canonical.com>
 S:     Supported
 F:     scripts/checkpatch.pl
 
+CHINESE DOCUMENTATION
+M:     Harry Wei <harryxiyou@gmail.com>
+L:     xiyoulinuxkernelgroup@googlegroups.com
+L:     linux-kernel@zh-kernel.org (moderated for non-subscribers)
+S:     Maintained
+F:     Documentation/zh_CN/
+
 CISCO VIC ETHERNET NIC DRIVER
 M:     Christian Benvenuti <benve@cisco.com>
 M:     Vasanthy Kolluri <vkolluri@cisco.com>
@@ -2027,7 +2035,7 @@ F:        Documentation/scsi/dc395x.txt
 F:     drivers/scsi/dc395x.*
 
 DCCP PROTOCOL
-M:     Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
+M:     Gerrit Renker <gerrit@erg.abdn.ac.uk>
 L:     dccp@vger.kernel.org
 W:     http://www.linuxfoundation.org/collaborate/workgroups/networking/dccp
 S:     Maintained
@@ -2874,7 +2882,6 @@ M:        Guenter Roeck <guenter.roeck@ericsson.com>
 L:     lm-sensors@lm-sensors.org
 W:     http://www.lm-sensors.org/
 T:     quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-hwmon/
-T:     quilt kernel.org/pub/linux/kernel/people/groeck/linux-staging/
 T:     git git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git
 S:     Maintained
 F:     Documentation/hwmon/
@@ -5269,7 +5276,7 @@ S:        Maintained
 F:     drivers/net/wireless/rtl818x/rtl8180/
 
 RTL8187 WIRELESS DRIVER
-M:     Herton Ronaldo Krzesinski <herton@mandriva.com.br>
+M:     Herton Ronaldo Krzesinski <herton@canonical.com>
 M:     Hin-Tak Leung <htl10@users.sourceforge.net>
 M:     Larry Finger <Larry.Finger@lwfinger.net>
 L:     linux-wireless@vger.kernel.org
@@ -6107,7 +6114,7 @@ S:        Maintained
 F:     security/tomoyo/
 
 TOPSTAR LAPTOP EXTRAS DRIVER
-M:     Herton Ronaldo Krzesinski <herton@mandriva.com.br>
+M:     Herton Ronaldo Krzesinski <herton@canonical.com>
 L:     platform-driver-x86@vger.kernel.org
 S:     Maintained
 F:     drivers/platform/x86/topstar-laptop.c
index 5e40aa2..2f7d922 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 6
 SUBLEVEL = 38
-EXTRAVERSION = -rc5
+EXTRAVERSION = -rc7
 NAME = Flesh-Eating Bats with Fangs
 
 # *DOCUMENTATION*
index 47f63d4..cc31bec 100644 (file)
@@ -11,6 +11,7 @@ config ALPHA
        select HAVE_GENERIC_HARDIRQS
        select GENERIC_IRQ_PROBE
        select AUTO_IRQ_AFFINITY if SMP
+       select GENERIC_HARDIRQS_NO_DEPRECATED
        help
          The Alpha is a 64-bit general-purpose processor designed and
          marketed by the Digital Equipment Corporation of blessed memory,
index 9ab234f..a19d600 100644 (file)
@@ -44,11 +44,16 @@ static char irq_user_affinity[NR_IRQS];
 
 int irq_select_affinity(unsigned int irq)
 {
-       struct irq_desc *desc = irq_to_desc[irq];
+       struct irq_data *data = irq_get_irq_data(irq);
+       struct irq_chip *chip;
        static int last_cpu;
        int cpu = last_cpu + 1;
 
-       if (!desc || !get_irq_desc_chip(desc)->set_affinity || irq_user_affinity[irq])
+       if (!data)
+               return 1;
+       chip = irq_data_get_irq_chip(data);
+
+       if (!chip->irq_set_affinity || irq_user_affinity[irq])
                return 1;
 
        while (!cpu_possible(cpu) ||
@@ -56,8 +61,8 @@ int irq_select_affinity(unsigned int irq)
                cpu = (cpu < (NR_CPUS-1) ? cpu + 1 : 0);
        last_cpu = cpu;
 
-       cpumask_copy(desc->affinity, cpumask_of(cpu));
-       get_irq_desc_chip(desc)->set_affinity(irq, cpumask_of(cpu));
+       cpumask_copy(data->affinity, cpumask_of(cpu));
+       chip->irq_set_affinity(data, cpumask_of(cpu), false);
        return 0;
 }
 #endif /* CONFIG_SMP */
index 2d0679b..411ca11 100644 (file)
@@ -228,14 +228,9 @@ struct irqaction timer_irqaction = {
 void __init
 init_rtc_irq(void)
 {
-       struct irq_desc *desc = irq_to_desc(RTC_IRQ);
-
-       if (desc) {
-               desc->status |= IRQ_DISABLED;
-               set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
-                       handle_simple_irq, "RTC");
-               setup_irq(RTC_IRQ, &timer_irqaction);
-       }
+       set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
+                                     handle_simple_irq, "RTC");
+       setup_irq(RTC_IRQ, &timer_irqaction);
 }
 
 /* Dummy irqactions.  */
index 956ea0e..c7cc981 100644 (file)
@@ -33,10 +33,10 @@ i8259_update_irq_hw(unsigned int irq, unsigned long mask)
 }
 
 inline void
-i8259a_enable_irq(unsigned int irq)
+i8259a_enable_irq(struct irq_data *d)
 {
        spin_lock(&i8259_irq_lock);
-       i8259_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq));
+       i8259_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq));
        spin_unlock(&i8259_irq_lock);
 }
 
@@ -47,16 +47,18 @@ __i8259a_disable_irq(unsigned int irq)
 }
 
 void
-i8259a_disable_irq(unsigned int irq)
+i8259a_disable_irq(struct irq_data *d)
 {
        spin_lock(&i8259_irq_lock);
-       __i8259a_disable_irq(irq);
+       __i8259a_disable_irq(d->irq);
        spin_unlock(&i8259_irq_lock);
 }
 
 void
-i8259a_mask_and_ack_irq(unsigned int irq)
+i8259a_mask_and_ack_irq(struct irq_data *d)
 {
+       unsigned int irq = d->irq;
+
        spin_lock(&i8259_irq_lock);
        __i8259a_disable_irq(irq);
 
@@ -71,9 +73,9 @@ i8259a_mask_and_ack_irq(unsigned int irq)
 
 struct irq_chip i8259a_irq_type = {
        .name           = "XT-PIC",
-       .unmask         = i8259a_enable_irq,
-       .mask           = i8259a_disable_irq,
-       .mask_ack       = i8259a_mask_and_ack_irq,
+       .irq_unmask     = i8259a_enable_irq,
+       .irq_mask       = i8259a_disable_irq,
+       .irq_mask_ack   = i8259a_mask_and_ack_irq,
 };
 
 void __init
index b63ccd7..d507a23 100644 (file)
@@ -31,11 +31,9 @@ extern void init_rtc_irq(void);
 
 extern void common_init_isa_dma(void);
 
-extern void i8259a_enable_irq(unsigned int);
-extern void i8259a_disable_irq(unsigned int);
-extern void i8259a_mask_and_ack_irq(unsigned int);
-extern unsigned int i8259a_startup_irq(unsigned int);
-extern void i8259a_end_irq(unsigned int);
+extern void i8259a_enable_irq(struct irq_data *d);
+extern void i8259a_disable_irq(struct irq_data *d);
+extern void i8259a_mask_and_ack_irq(struct irq_data *d);
 extern struct irq_chip i8259a_irq_type;
 extern void init_i8259a_irqs(void);
 
index 2863458..b30227f 100644 (file)
@@ -29,21 +29,21 @@ pyxis_update_irq_hw(unsigned long mask)
 }
 
 static inline void
-pyxis_enable_irq(unsigned int irq)
+pyxis_enable_irq(struct irq_data *d)
 {
-       pyxis_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
+       pyxis_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
 }
 
 static void
-pyxis_disable_irq(unsigned int irq)
+pyxis_disable_irq(struct irq_data *d)
 {
-       pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
+       pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
 }
 
 static void
-pyxis_mask_and_ack_irq(unsigned int irq)
+pyxis_mask_and_ack_irq(struct irq_data *d)
 {
-       unsigned long bit = 1UL << (irq - 16);
+       unsigned long bit = 1UL << (d->irq - 16);
        unsigned long mask = cached_irq_mask &= ~bit;
 
        /* Disable the interrupt.  */
@@ -58,9 +58,9 @@ pyxis_mask_and_ack_irq(unsigned int irq)
 
 static struct irq_chip pyxis_irq_type = {
        .name           = "PYXIS",
-       .mask_ack       = pyxis_mask_and_ack_irq,
-       .mask           = pyxis_disable_irq,
-       .unmask         = pyxis_enable_irq,
+       .irq_mask_ack   = pyxis_mask_and_ack_irq,
+       .irq_mask       = pyxis_disable_irq,
+       .irq_unmask     = pyxis_enable_irq,
 };
 
 void 
@@ -103,7 +103,7 @@ init_pyxis_irqs(unsigned long ignore_mask)
                if ((ignore_mask >> i) & 1)
                        continue;
                set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq);
-               irq_to_desc(i)->status |= IRQ_LEVEL;
+               irq_set_status_flags(i, IRQ_LEVEL);
        }
 
        setup_irq(16+7, &isa_cascade_irqaction);
index 0e57e82..82a47bb 100644 (file)
 DEFINE_SPINLOCK(srm_irq_lock);
 
 static inline void
-srm_enable_irq(unsigned int irq)
+srm_enable_irq(struct irq_data *d)
 {
        spin_lock(&srm_irq_lock);
-       cserve_ena(irq - 16);
+       cserve_ena(d->irq - 16);
        spin_unlock(&srm_irq_lock);
 }
 
 static void
-srm_disable_irq(unsigned int irq)
+srm_disable_irq(struct irq_data *d)
 {
        spin_lock(&srm_irq_lock);
-       cserve_dis(irq - 16);
+       cserve_dis(d->irq - 16);
        spin_unlock(&srm_irq_lock);
 }
 
 /* Handle interrupts from the SRM, assuming no additional weirdness.  */
 static struct irq_chip srm_irq_type = {
        .name           = "SRM",
-       .unmask         = srm_enable_irq,
-       .mask           = srm_disable_irq,
-       .mask_ack       = srm_disable_irq,
+       .irq_unmask     = srm_enable_irq,
+       .irq_mask       = srm_disable_irq,
+       .irq_mask_ack   = srm_disable_irq,
 };
 
 void __init
@@ -52,7 +52,7 @@ init_srm_irqs(long max, unsigned long ignore_mask)
                if (i < 64 && ((ignore_mask >> i) & 1))
                        continue;
                set_irq_chip_and_handler(i, &srm_irq_type, handle_level_irq);
-               irq_to_desc(i)->status |= IRQ_LEVEL;
+               irq_set_status_flags(i, IRQ_LEVEL);
        }
 }
 
index 7bef617..88d95e8 100644 (file)
@@ -44,31 +44,31 @@ alcor_update_irq_hw(unsigned long mask)
 }
 
 static inline void
-alcor_enable_irq(unsigned int irq)
+alcor_enable_irq(struct irq_data *d)
 {
-       alcor_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
+       alcor_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
 }
 
 static void
-alcor_disable_irq(unsigned int irq)
+alcor_disable_irq(struct irq_data *d)
 {
-       alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
+       alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
 }
 
 static void
-alcor_mask_and_ack_irq(unsigned int irq)
+alcor_mask_and_ack_irq(struct irq_data *d)
 {
-       alcor_disable_irq(irq);
+       alcor_disable_irq(d);
 
        /* On ALCOR/XLT, need to dismiss interrupt via GRU. */
-       *(vuip)GRU_INT_CLEAR = 1 << (irq - 16); mb();
+       *(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb();
        *(vuip)GRU_INT_CLEAR = 0; mb();
 }
 
 static void
-alcor_isa_mask_and_ack_irq(unsigned int irq)
+alcor_isa_mask_and_ack_irq(struct irq_data *d)
 {
-       i8259a_mask_and_ack_irq(irq);
+       i8259a_mask_and_ack_irq(d);
 
        /* On ALCOR/XLT, need to dismiss interrupt via GRU. */
        *(vuip)GRU_INT_CLEAR = 0x80000000; mb();
@@ -77,9 +77,9 @@ alcor_isa_mask_and_ack_irq(unsigned int irq)
 
 static struct irq_chip alcor_irq_type = {
        .name           = "ALCOR",
-       .unmask         = alcor_enable_irq,
-       .mask           = alcor_disable_irq,
-       .mask_ack       = alcor_mask_and_ack_irq,
+       .irq_unmask     = alcor_enable_irq,
+       .irq_mask       = alcor_disable_irq,
+       .irq_mask_ack   = alcor_mask_and_ack_irq,
 };
 
 static void
@@ -126,9 +126,9 @@ alcor_init_irq(void)
                if (i >= 16+20 && i <= 16+30)
                        continue;
                set_irq_chip_and_handler(i, &alcor_irq_type, handle_level_irq);
-               irq_to_desc(i)->status |= IRQ_LEVEL;
+               irq_set_status_flags(i, IRQ_LEVEL);
        }
-       i8259a_irq_type.ack = alcor_isa_mask_and_ack_irq;
+       i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq;
 
        init_i8259a_irqs();
        common_init_isa_dma();
index b0c9164..57eb630 100644 (file)
@@ -46,22 +46,22 @@ cabriolet_update_irq_hw(unsigned int irq, unsigned long mask)
 }
 
 static inline void
-cabriolet_enable_irq(unsigned int irq)
+cabriolet_enable_irq(struct irq_data *d)
 {
-       cabriolet_update_irq_hw(irq, cached_irq_mask &= ~(1UL << irq));
+       cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq));
 }
 
 static void
-cabriolet_disable_irq(unsigned int irq)
+cabriolet_disable_irq(struct irq_data *d)
 {
-       cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq);
+       cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq);
 }
 
 static struct irq_chip cabriolet_irq_type = {
        .name           = "CABRIOLET",
-       .unmask         = cabriolet_enable_irq,
-       .mask           = cabriolet_disable_irq,
-       .mask_ack       = cabriolet_disable_irq,
+       .irq_unmask     = cabriolet_enable_irq,
+       .irq_mask       = cabriolet_disable_irq,
+       .irq_mask_ack   = cabriolet_disable_irq,
 };
 
 static void 
@@ -107,7 +107,7 @@ common_init_irq(void (*srm_dev_int)(unsigned long v))
                for (i = 16; i < 35; ++i) {
                        set_irq_chip_and_handler(i, &cabriolet_irq_type,
                                handle_level_irq);
-                       irq_to_desc(i)->status |= IRQ_LEVEL;
+                       irq_set_status_flags(i, IRQ_LEVEL);
                }
        }
 
index edad5f7..481df4e 100644 (file)
@@ -98,37 +98,37 @@ tsunami_update_irq_hw(unsigned long mask)
 }
 
 static void
-dp264_enable_irq(unsigned int irq)
+dp264_enable_irq(struct irq_data *d)
 {
        spin_lock(&dp264_irq_lock);
-       cached_irq_mask |= 1UL << irq;
+       cached_irq_mask |= 1UL << d->irq;
        tsunami_update_irq_hw(cached_irq_mask);
        spin_unlock(&dp264_irq_lock);
 }
 
 static void
-dp264_disable_irq(unsigned int irq)
+dp264_disable_irq(struct irq_data *d)
 {
        spin_lock(&dp264_irq_lock);
-       cached_irq_mask &= ~(1UL << irq);
+       cached_irq_mask &= ~(1UL << d->irq);
        tsunami_update_irq_hw(cached_irq_mask);
        spin_unlock(&dp264_irq_lock);
 }
 
 static void
-clipper_enable_irq(unsigned int irq)
+clipper_enable_irq(struct irq_data *d)
 {
        spin_lock(&dp264_irq_lock);
-       cached_irq_mask |= 1UL << (irq - 16);
+       cached_irq_mask |= 1UL << (d->irq - 16);
        tsunami_update_irq_hw(cached_irq_mask);
        spin_unlock(&dp264_irq_lock);
 }
 
 static void
-clipper_disable_irq(unsigned int irq)
+clipper_disable_irq(struct irq_data *d)
 {
        spin_lock(&dp264_irq_lock);
-       cached_irq_mask &= ~(1UL << (irq - 16));
+       cached_irq_mask &= ~(1UL << (d->irq - 16));
        tsunami_update_irq_hw(cached_irq_mask);
        spin_unlock(&dp264_irq_lock);
 }
@@ -149,10 +149,11 @@ cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
 }
 
 static int
-dp264_set_affinity(unsigned int irq, const struct cpumask *affinity)
-{ 
+dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity,
+                  bool force)
+{
        spin_lock(&dp264_irq_lock);
-       cpu_set_irq_affinity(irq, *affinity);
+       cpu_set_irq_affinity(d->irq, *affinity);
        tsunami_update_irq_hw(cached_irq_mask);
        spin_unlock(&dp264_irq_lock);
 
@@ -160,10 +161,11 @@ dp264_set_affinity(unsigned int irq, const struct cpumask *affinity)
 }
 
 static int
-clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
-{ 
+clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity,
+                    bool force)
+{
        spin_lock(&dp264_irq_lock);
-       cpu_set_irq_affinity(irq - 16, *affinity);
+       cpu_set_irq_affinity(d->irq - 16, *affinity);
        tsunami_update_irq_hw(cached_irq_mask);
        spin_unlock(&dp264_irq_lock);
 
@@ -171,19 +173,19 @@ clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
 }
 
 static struct irq_chip dp264_irq_type = {
-       .name           = "DP264",
-       .unmask         = dp264_enable_irq,
-       .mask           = dp264_disable_irq,
-       .mask_ack       = dp264_disable_irq,
-       .set_affinity   = dp264_set_affinity,
+       .name                   = "DP264",
+       .irq_unmask             = dp264_enable_irq,
+       .irq_mask               = dp264_disable_irq,
+       .irq_mask_ack           = dp264_disable_irq,
+       .irq_set_affinity       = dp264_set_affinity,
 };
 
 static struct irq_chip clipper_irq_type = {
-       .name           = "CLIPPER",
-       .unmask         = clipper_enable_irq,
-       .mask           = clipper_disable_irq,
-       .mask_ack       = clipper_disable_irq,
-       .set_affinity   = clipper_set_affinity,
+       .name                   = "CLIPPER",
+       .irq_unmask             = clipper_enable_irq,
+       .irq_mask               = clipper_disable_irq,
+       .irq_mask_ack           = clipper_disable_irq,
+       .irq_set_affinity       = clipper_set_affinity,
 };
 
 static void
@@ -268,8 +270,8 @@ init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
 {
        long i;
        for (i = imin; i <= imax; ++i) {
-               irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, ops, handle_level_irq);
+               irq_set_status_flags(i, IRQ_LEVEL);
        }
 }
 
index ae5f29d..402e908 100644 (file)
@@ -44,22 +44,22 @@ eb64p_update_irq_hw(unsigned int irq, unsigned long mask)
 }
 
 static inline void
-eb64p_enable_irq(unsigned int irq)
+eb64p_enable_irq(struct irq_data *d)
 {
-       eb64p_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq));
+       eb64p_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq));
 }
 
 static void
-eb64p_disable_irq(unsigned int irq)
+eb64p_disable_irq(struct irq_data *d)
 {
-       eb64p_update_irq_hw(irq, cached_irq_mask |= 1 << irq);
+       eb64p_update_irq_hw(d->irq, cached_irq_mask |= 1 << d->irq);
 }
 
 static struct irq_chip eb64p_irq_type = {
        .name           = "EB64P",
-       .unmask         = eb64p_enable_irq,
-       .mask           = eb64p_disable_irq,
-       .mask_ack       = eb64p_disable_irq,
+       .irq_unmask     = eb64p_enable_irq,
+       .irq_mask       = eb64p_disable_irq,
+       .irq_mask_ack   = eb64p_disable_irq,
 };
 
 static void 
@@ -118,9 +118,9 @@ eb64p_init_irq(void)
        init_i8259a_irqs();
 
        for (i = 16; i < 32; ++i) {
-               irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, &eb64p_irq_type, handle_level_irq);
-       }               
+               irq_set_status_flags(i, IRQ_LEVEL);
+       }
 
        common_init_isa_dma();
        setup_irq(16+5, &isa_cascade_irqaction);
index 1121bc5..0b44a54 100644 (file)
@@ -51,16 +51,18 @@ eiger_update_irq_hw(unsigned long irq, unsigned long mask)
 }
 
 static inline void
-eiger_enable_irq(unsigned int irq)
+eiger_enable_irq(struct irq_data *d)
 {
+       unsigned int irq = d->irq;
        unsigned long mask;
        mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
        eiger_update_irq_hw(irq, mask);
 }
 
 static void
-eiger_disable_irq(unsigned int irq)
+eiger_disable_irq(struct irq_data *d)
 {
+       unsigned int irq = d->irq;
        unsigned long mask;
        mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
        eiger_update_irq_hw(irq, mask);
@@ -68,9 +70,9 @@ eiger_disable_irq(unsigned int irq)
 
 static struct irq_chip eiger_irq_type = {
        .name           = "EIGER",
-       .unmask         = eiger_enable_irq,
-       .mask           = eiger_disable_irq,
-       .mask_ack       = eiger_disable_irq,
+       .irq_unmask     = eiger_enable_irq,
+       .irq_mask       = eiger_disable_irq,
+       .irq_mask_ack   = eiger_disable_irq,
 };
 
 static void
@@ -136,8 +138,8 @@ eiger_init_irq(void)
        init_i8259a_irqs();
 
        for (i = 16; i < 128; ++i) {
-               irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, &eiger_irq_type, handle_level_irq);
+               irq_set_status_flags(i, IRQ_LEVEL);
        }
 }
 
index 34f55e0..00341b7 100644 (file)
  */
 
 static void
-jensen_local_enable(unsigned int irq)
+jensen_local_enable(struct irq_data *d)
 {
        /* the parport is really hw IRQ 1, silly Jensen.  */
-       if (irq == 7)
-               i8259a_enable_irq(1);
+       if (d->irq == 7)
+               i8259a_enable_irq(d);
 }
 
 static void
-jensen_local_disable(unsigned int irq)
+jensen_local_disable(struct irq_data *d)
 {
        /* the parport is really hw IRQ 1, silly Jensen.  */
-       if (irq == 7)
-               i8259a_disable_irq(1);
+       if (d->irq == 7)
+               i8259a_disable_irq(d);
 }
 
 static void
-jensen_local_mask_ack(unsigned int irq)
+jensen_local_mask_ack(struct irq_data *d)
 {
        /* the parport is really hw IRQ 1, silly Jensen.  */
-       if (irq == 7)
-               i8259a_mask_and_ack_irq(1);
+       if (d->irq == 7)
+               i8259a_mask_and_ack_irq(d);
 }
 
 static struct irq_chip jensen_local_irq_type = {
        .name           = "LOCAL",
-       .unmask         = jensen_local_enable,
-       .mask           = jensen_local_disable,
-       .mask_ack       = jensen_local_mask_ack,
+       .irq_unmask     = jensen_local_enable,
+       .irq_mask       = jensen_local_disable,
+       .irq_mask_ack   = jensen_local_mask_ack,
 };
 
 static void 
index 2bfc9f1..e619107 100644 (file)
@@ -104,9 +104,10 @@ io7_get_irq_ctl(unsigned int irq, struct io7 **pio7)
 }
 
 static void
-io7_enable_irq(unsigned int irq)
+io7_enable_irq(struct irq_data *d)
 {
        volatile unsigned long *ctl;
+       unsigned int irq = d->irq;
        struct io7 *io7;
 
        ctl = io7_get_irq_ctl(irq, &io7);
@@ -115,7 +116,7 @@ io7_enable_irq(unsigned int irq)
                       __func__, irq);
                return;
        }
-               
+
        spin_lock(&io7->irq_lock);
        *ctl |= 1UL << 24;
        mb();
@@ -124,9 +125,10 @@ io7_enable_irq(unsigned int irq)
 }
 
 static void
-io7_disable_irq(unsigned int irq)
+io7_disable_irq(struct irq_data *d)
 {
        volatile unsigned long *ctl;
+       unsigned int irq = d->irq;
        struct io7 *io7;
 
        ctl = io7_get_irq_ctl(irq, &io7);
@@ -135,7 +137,7 @@ io7_disable_irq(unsigned int irq)
                       __func__, irq);
                return;
        }
-               
+
        spin_lock(&io7->irq_lock);
        *ctl &= ~(1UL << 24);
        mb();
@@ -144,35 +146,29 @@ io7_disable_irq(unsigned int irq)
 }
 
 static void
-marvel_irq_noop(unsigned int irq) 
-{ 
-       return; 
-}
-
-static unsigned int
-marvel_irq_noop_return(unsigned int irq) 
-{ 
-       return 0; 
+marvel_irq_noop(struct irq_data *d)
+{
+       return;
 }
 
 static struct irq_chip marvel_legacy_irq_type = {
        .name           = "LEGACY",
-       .mask           = marvel_irq_noop,
-       .unmask         = marvel_irq_noop,
+       .irq_mask       = marvel_irq_noop,
+       .irq_unmask     = marvel_irq_noop,
 };
 
 static struct irq_chip io7_lsi_irq_type = {
        .name           = "LSI",
-       .unmask         = io7_enable_irq,
-       .mask           = io7_disable_irq,
-       .mask_ack       = io7_disable_irq,
+       .irq_unmask     = io7_enable_irq,
+       .irq_mask       = io7_disable_irq,
+       .irq_mask_ack   = io7_disable_irq,
 };
 
 static struct irq_chip io7_msi_irq_type = {
        .name           = "MSI",
-       .unmask         = io7_enable_irq,
-       .mask           = io7_disable_irq,
-       .ack            = marvel_irq_noop,
+       .irq_unmask     = io7_enable_irq,
+       .irq_mask       = io7_disable_irq,
+       .irq_ack        = marvel_irq_noop,
 };
 
 static void
@@ -280,8 +276,8 @@ init_io7_irqs(struct io7 *io7,
 
        /* Set up the lsi irqs.  */
        for (i = 0; i < 128; ++i) {
-               irq_to_desc(base + i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq);
+               irq_set_status_flags(i, IRQ_LEVEL);
        }
 
        /* Disable the implemented irqs in hardware.  */
@@ -294,8 +290,8 @@ init_io7_irqs(struct io7 *io7,
 
        /* Set up the msi irqs.  */
        for (i = 128; i < (128 + 512); ++i) {
-               irq_to_desc(base + i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq);
+               irq_set_status_flags(i, IRQ_LEVEL);
        }
 
        for (i = 0; i < 16; ++i)
index bcc1639..cf7f43d 100644 (file)
@@ -43,22 +43,22 @@ mikasa_update_irq_hw(int mask)
 }
 
 static inline void
-mikasa_enable_irq(unsigned int irq)
+mikasa_enable_irq(struct irq_data *d)
 {
-       mikasa_update_irq_hw(cached_irq_mask |= 1 << (irq - 16));
+       mikasa_update_irq_hw(cached_irq_mask |= 1 << (d->irq - 16));
 }
 
 static void
-mikasa_disable_irq(unsigned int irq)
+mikasa_disable_irq(struct irq_data *d)
 {
-       mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16)));
+       mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (d->irq - 16)));
 }
 
 static struct irq_chip mikasa_irq_type = {
        .name           = "MIKASA",
-       .unmask         = mikasa_enable_irq,
-       .mask           = mikasa_disable_irq,
-       .mask_ack       = mikasa_disable_irq,
+       .irq_unmask     = mikasa_enable_irq,
+       .irq_mask       = mikasa_disable_irq,
+       .irq_mask_ack   = mikasa_disable_irq,
 };
 
 static void 
@@ -98,8 +98,8 @@ mikasa_init_irq(void)
        mikasa_update_irq_hw(0);
 
        for (i = 16; i < 32; ++i) {
-               irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq);
+               irq_set_status_flags(i, IRQ_LEVEL);
        }
 
        init_i8259a_irqs();
index e88f4ae..92bc188 100644 (file)
@@ -48,22 +48,22 @@ noritake_update_irq_hw(int irq, int mask)
 }
 
 static void
-noritake_enable_irq(unsigned int irq)
+noritake_enable_irq(struct irq_data *d)
 {
-       noritake_update_irq_hw(irq, cached_irq_mask |= 1 << (irq - 16));
+       noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16));
 }
 
 static void
-noritake_disable_irq(unsigned int irq)
+noritake_disable_irq(struct irq_data *d)
 {
-       noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16)));
+       noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16)));
 }
 
 static struct irq_chip noritake_irq_type = {
        .name           = "NORITAKE",
-       .unmask         = noritake_enable_irq,
-       .mask           = noritake_disable_irq,
-       .mask_ack       = noritake_disable_irq,
+       .irq_unmask     = noritake_enable_irq,
+       .irq_mask       = noritake_disable_irq,
+       .irq_mask_ack   = noritake_disable_irq,
 };
 
 static void 
@@ -127,8 +127,8 @@ noritake_init_irq(void)
        outw(0, 0x54c);
 
        for (i = 16; i < 48; ++i) {
-               irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, &noritake_irq_type, handle_level_irq);
+               irq_set_status_flags(i, IRQ_LEVEL);
        }
 
        init_i8259a_irqs();
index 6a51364..936d414 100644 (file)
@@ -56,9 +56,10 @@ rawhide_update_irq_hw(int hose, int mask)
   (((h) < MCPCIA_MAX_HOSES) && (cached_irq_masks[(h)] != 0))
 
 static inline void 
-rawhide_enable_irq(unsigned int irq)
+rawhide_enable_irq(struct irq_data *d)
 {
        unsigned int mask, hose;
+       unsigned int irq = d->irq;
 
        irq -= 16;
        hose = irq / 24;
@@ -76,9 +77,10 @@ rawhide_enable_irq(unsigned int irq)
 }
 
 static void 
-rawhide_disable_irq(unsigned int irq)
+rawhide_disable_irq(struct irq_data *d)
 {
        unsigned int mask, hose;
+       unsigned int irq = d->irq;
 
        irq -= 16;
        hose = irq / 24;
@@ -96,9 +98,10 @@ rawhide_disable_irq(unsigned int irq)
 }
 
 static void
-rawhide_mask_and_ack_irq(unsigned int irq)
+rawhide_mask_and_ack_irq(struct irq_data *d)
 {
        unsigned int mask, mask1, hose;
+       unsigned int irq = d->irq;
 
        irq -= 16;
        hose = irq / 24;
@@ -123,9 +126,9 @@ rawhide_mask_and_ack_irq(unsigned int irq)
 
 static struct irq_chip rawhide_irq_type = {
        .name           = "RAWHIDE",
-       .unmask         = rawhide_enable_irq,
-       .mask           = rawhide_disable_irq,
-       .mask_ack       = rawhide_mask_and_ack_irq,
+       .irq_unmask     = rawhide_enable_irq,
+       .irq_mask       = rawhide_disable_irq,
+       .irq_mask_ack   = rawhide_mask_and_ack_irq,
 };
 
 static void 
@@ -177,8 +180,8 @@ rawhide_init_irq(void)
        }
 
        for (i = 16; i < 128; ++i) {
-               irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, &rawhide_irq_type, handle_level_irq);
+               irq_set_status_flags(i, IRQ_LEVEL);
        }
 
        init_i8259a_irqs();
index 89e7e37..cea22a6 100644 (file)
@@ -47,22 +47,22 @@ rx164_update_irq_hw(unsigned long mask)
 }
 
 static inline void
-rx164_enable_irq(unsigned int irq)
+rx164_enable_irq(struct irq_data *d)
 {
-       rx164_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
+       rx164_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
 }
 
 static void
-rx164_disable_irq(unsigned int irq)
+rx164_disable_irq(struct irq_data *d)
 {
-       rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
+       rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
 }
 
 static struct irq_chip rx164_irq_type = {
        .name           = "RX164",
-       .unmask         = rx164_enable_irq,
-       .mask           = rx164_disable_irq,
-       .mask_ack       = rx164_disable_irq,
+       .irq_unmask     = rx164_enable_irq,
+       .irq_mask       = rx164_disable_irq,
+       .irq_mask_ack   = rx164_disable_irq,
 };
 
 static void 
@@ -99,8 +99,8 @@ rx164_init_irq(void)
 
        rx164_update_irq_hw(0);
        for (i = 16; i < 40; ++i) {
-               irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
+               irq_set_status_flags(i, IRQ_LEVEL);
        }
 
        init_i8259a_irqs();
index 5c4423d..a349538 100644 (file)
@@ -443,11 +443,11 @@ lynx_swizzle(struct pci_dev *dev, u8 *pinp)
 /* GENERIC irq routines */
 
 static inline void
-sable_lynx_enable_irq(unsigned int irq)
+sable_lynx_enable_irq(struct irq_data *d)
 {
        unsigned long bit, mask;
 
-       bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
+       bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
        spin_lock(&sable_lynx_irq_lock);
        mask = sable_lynx_irq_swizzle->shadow_mask &= ~(1UL << bit);
        sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
@@ -459,11 +459,11 @@ sable_lynx_enable_irq(unsigned int irq)
 }
 
 static void
-sable_lynx_disable_irq(unsigned int irq)
+sable_lynx_disable_irq(struct irq_data *d)
 {
        unsigned long bit, mask;
 
-       bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
+       bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
        spin_lock(&sable_lynx_irq_lock);
        mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
        sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
@@ -475,11 +475,11 @@ sable_lynx_disable_irq(unsigned int irq)
 }
 
 static void
-sable_lynx_mask_and_ack_irq(unsigned int irq)
+sable_lynx_mask_and_ack_irq(struct irq_data *d)
 {
        unsigned long bit, mask;
 
-       bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
+       bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
        spin_lock(&sable_lynx_irq_lock);
        mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
        sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
@@ -489,9 +489,9 @@ sable_lynx_mask_and_ack_irq(unsigned int irq)
 
 static struct irq_chip sable_lynx_irq_type = {
        .name           = "SABLE/LYNX",
-       .unmask         = sable_lynx_enable_irq,
-       .mask           = sable_lynx_disable_irq,
-       .mask_ack       = sable_lynx_mask_and_ack_irq,
+       .irq_unmask     = sable_lynx_enable_irq,
+       .irq_mask       = sable_lynx_disable_irq,
+       .irq_mask_ack   = sable_lynx_mask_and_ack_irq,
 };
 
 static void 
@@ -518,9 +518,9 @@ sable_lynx_init_irq(int nr_of_irqs)
        long i;
 
        for (i = 0; i < nr_of_irqs; ++i) {
-               irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, &sable_lynx_irq_type,
                        handle_level_irq);
+               irq_set_status_flags(i, IRQ_LEVEL);
        }
 
        common_init_isa_dma();
index f8a1e8a..42a5331 100644 (file)
@@ -45,16 +45,18 @@ takara_update_irq_hw(unsigned long irq, unsigned long mask)
 }
 
 static inline void
-takara_enable_irq(unsigned int irq)
+takara_enable_irq(struct irq_data *d)
 {
+       unsigned int irq = d->irq;
        unsigned long mask;
        mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
        takara_update_irq_hw(irq, mask);
 }
 
 static void
-takara_disable_irq(unsigned int irq)
+takara_disable_irq(struct irq_data *d)
 {
+       unsigned int irq = d->irq;
        unsigned long mask;
        mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
        takara_update_irq_hw(irq, mask);
@@ -62,9 +64,9 @@ takara_disable_irq(unsigned int irq)
 
 static struct irq_chip takara_irq_type = {
        .name           = "TAKARA",
-       .unmask         = takara_enable_irq,
-       .mask           = takara_disable_irq,
-       .mask_ack       = takara_disable_irq,
+       .irq_unmask     = takara_enable_irq,
+       .irq_mask       = takara_disable_irq,
+       .irq_mask_ack   = takara_disable_irq,
 };
 
 static void
@@ -136,8 +138,8 @@ takara_init_irq(void)
                takara_update_irq_hw(i, -1);
 
        for (i = 16; i < 128; ++i) {
-               irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, &takara_irq_type, handle_level_irq);
+               irq_set_status_flags(i, IRQ_LEVEL);
        }
 
        common_init_isa_dma();
index e02494b..f6c108a 100644 (file)
@@ -112,8 +112,9 @@ titan_update_irq_hw(unsigned long mask)
 }
 
 static inline void
-titan_enable_irq(unsigned int irq)
+titan_enable_irq(struct irq_data *d)
 {
+       unsigned int irq = d->irq;
        spin_lock(&titan_irq_lock);
        titan_cached_irq_mask |= 1UL << (irq - 16);
        titan_update_irq_hw(titan_cached_irq_mask);
@@ -121,8 +122,9 @@ titan_enable_irq(unsigned int irq)
 }
 
 static inline void
-titan_disable_irq(unsigned int irq)
+titan_disable_irq(struct irq_data *d)
 {
+       unsigned int irq = d->irq;
        spin_lock(&titan_irq_lock);
        titan_cached_irq_mask &= ~(1UL << (irq - 16));
        titan_update_irq_hw(titan_cached_irq_mask);
@@ -144,7 +146,8 @@ titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
 }
 
 static int
-titan_set_irq_affinity(unsigned int irq, const struct cpumask *affinity)
+titan_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
+                      bool force)
 { 
        spin_lock(&titan_irq_lock);
        titan_cpu_set_irq_affinity(irq - 16, *affinity);
@@ -175,17 +178,17 @@ init_titan_irqs(struct irq_chip * ops, int imin, int imax)
 {
        long i;
        for (i = imin; i <= imax; ++i) {
-               irq_to_desc(i)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i, ops, handle_level_irq);
+               irq_set_status_flags(i, IRQ_LEVEL);
        }
 }
 
 static struct irq_chip titan_irq_type = {
-       .name           = "TITAN",
-       .unmask         = titan_enable_irq,
-       .mask           = titan_disable_irq,
-       .mask_ack       = titan_disable_irq,
-       .set_affinity   = titan_set_irq_affinity,
+       .name                   = "TITAN",
+       .irq_unmask             = titan_enable_irq,
+       .irq_mask               = titan_disable_irq,
+       .irq_mask_ack           = titan_disable_irq,
+       .irq_set_affinity       = titan_set_irq_affinity,
 };
 
 static irqreturn_t
index eec5259..ca60a38 100644 (file)
@@ -104,10 +104,12 @@ wildfire_init_irq_hw(void)
 }
 
 static void
-wildfire_enable_irq(unsigned int irq)
+wildfire_enable_irq(struct irq_data *d)
 {
+       unsigned int irq = d->irq;
+
        if (irq < 16)
-               i8259a_enable_irq(irq);
+               i8259a_enable_irq(d);
 
        spin_lock(&wildfire_irq_lock);
        set_bit(irq, &cached_irq_mask);
@@ -116,10 +118,12 @@ wildfire_enable_irq(unsigned int irq)
 }
 
 static void
-wildfire_disable_irq(unsigned int irq)
+wildfire_disable_irq(struct irq_data *d)
 {
+       unsigned int irq = d->irq;
+
        if (irq < 16)
-               i8259a_disable_irq(irq);
+               i8259a_disable_irq(d);
 
        spin_lock(&wildfire_irq_lock);
        clear_bit(irq, &cached_irq_mask);
@@ -128,10 +132,12 @@ wildfire_disable_irq(unsigned int irq)
 }
 
 static void
-wildfire_mask_and_ack_irq(unsigned int irq)
+wildfire_mask_and_ack_irq(struct irq_data *d)
 {
+       unsigned int irq = d->irq;
+
        if (irq < 16)
-               i8259a_mask_and_ack_irq(irq);
+               i8259a_mask_and_ack_irq(d);
 
        spin_lock(&wildfire_irq_lock);
        clear_bit(irq, &cached_irq_mask);
@@ -141,9 +147,9 @@ wildfire_mask_and_ack_irq(unsigned int irq)
 
 static struct irq_chip wildfire_irq_type = {
        .name           = "WILDFIRE",
-       .unmask         = wildfire_enable_irq,
-       .mask           = wildfire_disable_irq,
-       .mask_ack       = wildfire_mask_and_ack_irq,
+       .irq_unmask     = wildfire_enable_irq,
+       .irq_mask       = wildfire_disable_irq,
+       .irq_mask_ack   = wildfire_mask_and_ack_irq,
 };
 
 static void __init
@@ -177,21 +183,21 @@ wildfire_init_irq_per_pca(int qbbno, int pcano)
        for (i = 0; i < 16; ++i) {
                if (i == 2)
                        continue;
-               irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
                        handle_level_irq);
+               irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
        }
 
-       irq_to_desc(36+irq_bias)->status |= IRQ_LEVEL;
        set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type,
                handle_level_irq);
+       irq_set_status_flags(36 + irq_bias, IRQ_LEVEL);
        for (i = 40; i < 64; ++i) {
-               irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL;
                set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
                        handle_level_irq);
+               irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
        }
 
-       setup_irq(32+irq_bias, &isa_enable);    
+       setup_irq(32+irq_bias, &isa_enable);
 }
 
 static void __init
index 26d45e5..166efa2 100644 (file)
@@ -1177,6 +1177,31 @@ config ARM_ERRATA_743622
          visible impact on the overall performance or power consumption of the
          processor.
 
+config ARM_ERRATA_751472
+       bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
+       depends on CPU_V7 && SMP
+       help
+         This option enables the workaround for the 751472 Cortex-A9 (prior
+         to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
+         completion of a following broadcasted operation if the second
+         operation is received by a CPU before the ICIALLUIS has completed,
+         potentially leading to corrupted entries in the cache or TLB.
+
+config ARM_ERRATA_753970
+       bool "ARM errata: cache sync operation may be faulty"
+       depends on CACHE_PL310
+       help
+         This option enables the workaround for the 753970 PL310 (r3p0) erratum.
+
+         Under some condition the effect of cache sync operation on
+         the store buffer still remains when the operation completes.
+         This means that the store buffer is always asked to drain and
+         this prevents it from merging any further writes. The workaround
+         is to replace the normal offset of cache sync operation (0x730)
+         by another offset targeting an unmapped PL310 register 0x740.
+         This has the same effect as the cache sync operation: store buffer
+         drain and waiting for all buffers empty.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
index c22c1ad..6f7b292 100644 (file)
@@ -15,7 +15,7 @@ ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux        += --be8
 endif
 
-OBJCOPYFLAGS   :=-O binary -R .note -R .note.gnu.build-id -R .comment -S
+OBJCOPYFLAGS   :=-O binary -R .comment -S
 GZFLAGS                :=-9
 #KBUILD_CFLAGS +=-pipe
 # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
index ab204db..c602896 100644 (file)
@@ -1,3 +1,7 @@
 font.c
-piggy.gz
+lib1funcs.S
+piggy.gzip
+piggy.lzo
+piggy.lzma
+vmlinux
 vmlinux.lds
index 5aeec1e..16bd480 100644 (file)
@@ -36,6 +36,7 @@
 #define L2X0_RAW_INTR_STAT             0x21C
 #define L2X0_INTR_CLEAR                        0x220
 #define L2X0_CACHE_SYNC                        0x730
+#define L2X0_DUMMY_REG                 0x740
 #define L2X0_INV_LINE_PA               0x770
 #define L2X0_INV_WAY                   0x77C
 #define L2X0_CLEAN_LINE_PA             0x7B0
index 721847d..e0d1c0c 100644 (file)
@@ -58,6 +58,9 @@
 
 static inline void sysctl_soft_reset(void __iomem *base)
 {
+       /* switch to slow mode */
+       writel(0x2, base + SCCTRL);
+
        /* writing any value to SCSYSSTAT reg will reset system */
        writel(0, base + SCSYSSTAT);
 }
index f41a6f5..82dfe5d 100644 (file)
 #define __ASMARM_TLB_H
 
 #include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
 
 #ifndef CONFIG_MMU
 
 #include <linux/pagemap.h>
+
+#define tlb_flush(tlb) ((void) tlb)
+
 #include <asm-generic/tlb.h>
 
 #else /* !CONFIG_MMU */
 
+#include <linux/swap.h>
 #include <asm/pgalloc.h>
+#include <asm/tlbflush.h>
+
+/*
+ * We need to delay page freeing for SMP as other CPUs can access pages
+ * which have been removed but not yet had their TLB entries invalidated.
+ * Also, as ARMv7 speculative prefetch can drag new entries into the TLB,
+ * we need to apply this same delaying tactic to ensure correct operation.
+ */
+#if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7)
+#define tlb_fast_mode(tlb)     0
+#define FREE_PTE_NR            500
+#else
+#define tlb_fast_mode(tlb)     1
+#define FREE_PTE_NR            0
+#endif
 
 /*
  * TLB handling.  This allows us to remove pages from the page
 struct mmu_gather {
        struct mm_struct        *mm;
        unsigned int            fullmm;
+       struct vm_area_struct   *vma;
        unsigned long           range_start;
        unsigned long           range_end;
+       unsigned int            nr;
+       struct page             *pages[FREE_PTE_NR];
 };
 
 DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
 
+/*
+ * This is unnecessarily complex.  There's three ways the TLB shootdown
+ * code is used:
+ *  1. Unmapping a range of vmas.  See zap_page_range(), unmap_region().
+ *     tlb->fullmm = 0, and tlb_start_vma/tlb_end_vma will be called.
+ *     tlb->vma will be non-NULL.
+ *  2. Unmapping all vmas.  See exit_mmap().
+ *     tlb->fullmm = 1, and tlb_start_vma/tlb_end_vma will be called.
+ *     tlb->vma will be non-NULL.  Additionally, page tables will be freed.
+ *  3. Unmapping argument pages.  See shift_arg_pages().
+ *     tlb->fullmm = 0, but tlb_start_vma/tlb_end_vma will not be called.
+ *     tlb->vma will be NULL.
+ */
+static inline void tlb_flush(struct mmu_gather *tlb)
+{
+       if (tlb->fullmm || !tlb->vma)
+               flush_tlb_mm(tlb->mm);
+       else if (tlb->range_end > 0) {
+               flush_tlb_range(tlb->vma, tlb->range_start, tlb->range_end);
+               tlb->range_start = TASK_SIZE;
+               tlb->range_end = 0;
+       }
+}
+
+static inline void tlb_add_flush(struct mmu_gather *tlb, unsigned long addr)
+{
+       if (!tlb->fullmm) {
+               if (addr < tlb->range_start)
+                       tlb->range_start = addr;
+               if (addr + PAGE_SIZE > tlb->range_end)
+                       tlb->range_end = addr + PAGE_SIZE;
+       }
+}
+
+static inline void tlb_flush_mmu(struct mmu_gather *tlb)
+{
+       tlb_flush(tlb);
+       if (!tlb_fast_mode(tlb)) {
+               free_pages_and_swap_cache(tlb->pages, tlb->nr);
+               tlb->nr = 0;
+       }
+}
+
 static inline struct mmu_gather *
 tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 {
@@ -49,6 +113,8 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 
        tlb->mm = mm;
        tlb->fullmm = full_mm_flush;
+       tlb->vma = NULL;
+       tlb->nr = 0;
 
        return tlb;
 }
@@ -56,8 +122,7 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 static inline void
 tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 {
-       if (tlb->fullmm)
-               flush_tlb_mm(tlb->mm);
+       tlb_flush_mmu(tlb);
 
        /* keep the page table cache within bounds */
        check_pgt_cache();
@@ -71,12 +136,7 @@ tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 static inline void
 tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep, unsigned long addr)
 {
-       if (!tlb->fullmm) {
-               if (addr < tlb->range_start)
-                       tlb->range_start = addr;
-               if (addr + PAGE_SIZE > tlb->range_end)
-                       tlb->range_end = addr + PAGE_SIZE;
-       }
+       tlb_add_flush(tlb, addr);
 }
 
 /*
@@ -89,6 +149,7 @@ tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
 {
        if (!tlb->fullmm) {
                flush_cache_range(vma, vma->vm_start, vma->vm_end);
+               tlb->vma = vma;
                tlb->range_start = TASK_SIZE;
                tlb->range_end = 0;
        }
@@ -97,12 +158,30 @@ tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
 static inline void
 tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
 {
-       if (!tlb->fullmm && tlb->range_end > 0)
-               flush_tlb_range(vma, tlb->range_start, tlb->range_end);
+       if (!tlb->fullmm)
+               tlb_flush(tlb);
+}
+
+static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+       if (tlb_fast_mode(tlb)) {
+               free_page_and_swap_cache(page);
+       } else {
+               tlb->pages[tlb->nr++] = page;
+               if (tlb->nr >= FREE_PTE_NR)
+                       tlb_flush_mmu(tlb);
+       }
+}
+
+static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
+       unsigned long addr)
+{
+       pgtable_page_dtor(pte);
+       tlb_add_flush(tlb, addr);
+       tlb_remove_page(tlb, pte);
 }
 
-#define tlb_remove_page(tlb,page)      free_page_and_swap_cache(page)
-#define pte_free_tlb(tlb, ptep, addr)  pte_free((tlb)->mm, ptep)
+#define pte_free_tlb(tlb, ptep, addr)  __pte_free_tlb(tlb, ptep, addr)
 #define pmd_free_tlb(tlb, pmdp, addr)  pmd_free((tlb)->mm, pmdp)
 
 #define tlb_migrate_finish(mm)         do { } while (0)
index ce7378e..d2005de 100644 (file)
 #ifndef _ASMARM_TLBFLUSH_H
 #define _ASMARM_TLBFLUSH_H
 
-
-#ifndef CONFIG_MMU
-
-#define tlb_flush(tlb) ((void) tlb)
-
-#else /* CONFIG_MMU */
+#ifdef CONFIG_MMU
 
 #include <asm/glue.h>
 
index 2c1f005..8f6ed43 100644 (file)
@@ -1437,7 +1437,7 @@ arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 
                return space_cccc_1100_010x(insn, asi);
 
-       } else if ((insn & 0x0e000000) == 0x0c400000) {
+       } else if ((insn & 0x0e000000) == 0x0c000000) {
 
                return space_cccc_110x(insn, asi);
 
index b8af96e..2c79eec 100644 (file)
@@ -97,28 +97,34 @@ set_irq_affinity(int irq,
                           irq, cpu);
        return err;
 #else
-       return 0;
+       return -EINVAL;
 #endif
 }
 
 static int
 init_cpu_pmu(void)
 {
-       int i, err = 0;
+       int i, irqs, err = 0;
        struct platform_device *pdev = pmu_devices[ARM_PMU_DEVICE_CPU];
 
-       if (!pdev) {
-               err = -ENODEV;
-               goto out;
-       }
+       if (!pdev)
+               return -ENODEV;
+
+       irqs = pdev->num_resources;
+
+       /*
+        * If we have a single PMU interrupt that we can't shift, assume that
+        * we're running on a uniprocessor machine and continue.
+        */
+       if (irqs == 1 && !irq_can_set_affinity(platform_get_irq(pdev, 0)))
+               return 0;
 
-       for (i = 0; i < pdev->num_resources; ++i) {
+       for (i = 0; i < irqs; ++i) {
                err = set_irq_affinity(platform_get_irq(pdev, i), i);
                if (err)
                        break;
        }
 
-out:
        return err;
 }
 
index 420b8d6..5ea4fb7 100644 (file)
@@ -226,8 +226,8 @@ int cpu_architecture(void)
                 * Register 0 and check for VMSAv7 or PMSAv7 */
                asm("mrc        p15, 0, %0, c0, c1, 4"
                    : "=r" (mmfr0));
-               if ((mmfr0 & 0x0000000f) == 0x00000003 ||
-                   (mmfr0 & 0x000000f0) == 0x00000030)
+               if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
+                   (mmfr0 & 0x000000f0) >= 0x00000030)
                        cpu_arch = CPU_ARCH_ARMv7;
                else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
                         (mmfr0 & 0x000000f0) == 0x00000020)
index 907d5a6..abaf844 100644 (file)
@@ -474,7 +474,9 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
        unsigned long handler = (unsigned long)ka->sa.sa_handler;
        unsigned long retcode;
        int thumb = 0;
-       unsigned long cpsr = regs->ARM_cpsr & ~PSR_f;
+       unsigned long cpsr = regs->ARM_cpsr & ~(PSR_f | PSR_E_BIT);
+
+       cpsr |= PSR_ENDSTATE;
 
        /*
         * Maybe we need to deliver a 32-bit signal to a 26-bit task.
index 86b66f3..6146279 100644 (file)
 #define ARM_CPU_KEEP(x)
 #endif
 
+#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
+#define ARM_EXIT_KEEP(x)       x
+#else
+#define ARM_EXIT_KEEP(x)
+#endif
+
 OUTPUT_ARCH(arm)
 ENTRY(stext)
 
@@ -43,6 +49,7 @@ SECTIONS
                _sinittext = .;
                        HEAD_TEXT
                        INIT_TEXT
+                       ARM_EXIT_KEEP(EXIT_TEXT)
                _einittext = .;
                ARM_CPU_DISCARD(PROC_INFO)
                __arch_info_begin = .;
@@ -67,6 +74,7 @@ SECTIONS
 #ifndef CONFIG_XIP_KERNEL
                __init_begin = _stext;
                INIT_DATA
+               ARM_EXIT_KEEP(EXIT_DATA)
 #endif
        }
 
@@ -162,6 +170,7 @@ SECTIONS
                . = ALIGN(PAGE_SIZE);
                __init_begin = .;
                INIT_DATA
+               ARM_EXIT_KEEP(EXIT_DATA)
                . = ALIGN(PAGE_SIZE);
                __init_end = .;
 #endif
@@ -247,6 +256,8 @@ SECTIONS
        }
 #endif
 
+       NOTES
+
        BSS_SECTION(0, 0, 0)
        _end = .;
 
index 337392c..acb7ae5 100644 (file)
@@ -77,7 +77,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
        dd = clk->dpll_data;
 
        /* DPLL divider must result in a valid jitter correction val */
-       fint = clk->parent->rate / (n + 1);
+       fint = clk->parent->rate / n;
        if (fint < DPLL_FINT_BAND1_MIN) {
 
                pr_debug("rejecting n=%d due to Fint failure, "
index 394413d..0a585df 100644 (file)
@@ -334,7 +334,7 @@ static struct omap_mbox mbox_iva_info = {
        .priv   = &omap2_mbox_iva_priv,
 };
 
-struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL };
+struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
 #endif
 
 #if defined(CONFIG_ARCH_OMAP4)
index 98148b6..6c84659 100644 (file)
@@ -605,7 +605,7 @@ static void __init omap_mux_dbg_create_entry(
        list_for_each_entry(e, &partition->muxmodes, node) {
                struct omap_mux *m = &e->mux;
 
-               (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
+               (void)debugfs_create_file(m->muxnames[0], S_IWUSR, mux_dbg_dir,
                                          m, &omap_mux_dbg_signal_fops);
        }
 }
index 125f565..a5a83b3 100644 (file)
@@ -637,14 +637,14 @@ static int __init pm_dbg_init(void)
 
                }
 
-       (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d,
+       (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
                                   &enable_off_mode, &pm_dbg_option_fops);
-       (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,
+       (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
                                   &sleep_while_idle, &pm_dbg_option_fops);
-       (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
+       (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
                                   &wakeup_timer_seconds, &pm_dbg_option_fops);
        (void) debugfs_create_file("wakeup_timer_milliseconds",
-                       S_IRUGO | S_IWUGO, d, &wakeup_timer_milliseconds,
+                       S_IRUGO | S_IWUSR, d, &wakeup_timer_milliseconds,
                        &pm_dbg_option_fops);
        pm_dbg_init_done = 1;
 
index 729a644..3300ff6 100644 (file)
@@ -38,8 +38,8 @@
 #define OMAP4430_PRCM_MPU_CPU1_INST            0x0800
 
 /* PRCM_MPU clockdomain register offsets (from instance start) */
-#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS      0x0000
-#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS      0x0000
+#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS      0x0018
+#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS      0x0018
 
 
 /*
index c37e823..95ac336 100644 (file)
@@ -900,7 +900,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
                return PTR_ERR(dbg_dir);
        }
 
-       (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUGO, dbg_dir,
+       (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR, dbg_dir,
                                (void *)sr_info, &pm_sr_fops);
        (void) debugfs_create_x32("errweight", S_IRUGO, dbg_dir,
                        &sr_info->err_weight);
@@ -939,7 +939,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
                strcpy(name, "volt_");
                sprintf(volt_name, "%d", volt_data[i].volt_nominal);
                strcat(name, volt_name);
-               (void) debugfs_create_x32(name, S_IRUGO | S_IWUGO, nvalue_dir,
+               (void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
                                &(sr_info->nvalue_table[i].nvalue));
        }
 
index 7b7c268..0fc550e 100644 (file)
@@ -39,6 +39,7 @@
 #include <asm/mach/time.h>
 #include <plat/dmtimer.h>
 #include <asm/localtimer.h>
+#include <asm/sched_clock.h>
 
 #include "timer-gp.h"
 
@@ -190,6 +191,7 @@ static void __init omap2_gp_clocksource_init(void)
 /*
  * clocksource
  */
+static DEFINE_CLOCK_DATA(cd);
 static struct omap_dm_timer *gpt_clocksource;
 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 {
@@ -204,6 +206,15 @@ static struct clocksource clocksource_gpt = {
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static void notrace dmtimer_update_sched_clock(void)
+{
+       u32 cyc;
+
+       cyc = omap_dm_timer_read_counter(gpt_clocksource);
+
+       update_sched_clock(&cd, cyc, (u32)~0);
+}
+
 /* Setup free-running counter for clocksource */
 static void __init omap2_gp_clocksource_init(void)
 {
@@ -224,6 +235,8 @@ static void __init omap2_gp_clocksource_init(void)
 
        omap_dm_timer_set_load_start(gpt, 1, 0);
 
+       init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
+
        if (clocksource_register_hz(&clocksource_gpt, tick_rate))
                printk(err2, clocksource_gpt.name);
 }
index 203dd5a..058dab4 100644 (file)
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s5p6442/include/mach/map.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *             http://www.samsung.com/
  *
  * S5P6442 - Memory map definitions
 #include <plat/map-base.h>
 #include <plat/map-s5p.h>
 
-#define S5P6442_PA_CHIPID      (0xE0000000)
-#define S5P_PA_CHIPID          S5P6442_PA_CHIPID
+#define S5P6442_PA_SDRAM       0x20000000
 
-#define S5P6442_PA_SYSCON      (0xE0100000)
-#define S5P_PA_SYSCON          S5P6442_PA_SYSCON
+#define S5P6442_PA_I2S0                0xC0B00000
+#define S5P6442_PA_I2S1                0xF2200000
 
-#define S5P6442_PA_GPIO                (0xE0200000)
+#define S5P6442_PA_CHIPID      0xE0000000
 
-#define S5P6442_PA_VIC0                (0xE4000000)
-#define S5P6442_PA_VIC1                (0xE4100000)
-#define S5P6442_PA_VIC2                (0xE4200000)
+#define S5P6442_PA_SYSCON      0xE0100000
 
-#define S5P6442_PA_SROMC       (0xE7000000)
-#define S5P_PA_SROMC           S5P6442_PA_SROMC
+#define S5P6442_PA_GPIO                0xE0200000
 
-#define S5P6442_PA_MDMA                0xE8000000
-#define S5P6442_PA_PDMA                0xE9000000
+#define S5P6442_PA_VIC0                0xE4000000
+#define S5P6442_PA_VIC1                0xE4100000
+#define S5P6442_PA_VIC2                0xE4200000
 
-#define S5P6442_PA_TIMER       (0xEA000000)
-#define S5P_PA_TIMER           S5P6442_PA_TIMER
+#define S5P6442_PA_SROMC       0xE7000000
 
-#define S5P6442_PA_SYSTIMER    (0xEA100000)
+#define S5P6442_PA_MDMA                0xE8000000
+#define S5P6442_PA_PDMA                0xE9000000
 
-#define S5P6442_PA_WATCHDOG    (0xEA200000)
+#define S5P6442_PA_TIMER       0xEA000000
 
-#define S5P6442_PA_UART                (0xEC000000)
+#define S5P6442_PA_SYSTIMER    0xEA100000
 
-#define S5P_PA_UART0           (S5P6442_PA_UART + 0x0)
-#define S5P_PA_UART1           (S5P6442_PA_UART + 0x400)
-#define S5P_PA_UART2           (S5P6442_PA_UART + 0x800)
-#define S5P_SZ_UART            SZ_256
+#define S5P6442_PA_WATCHDOG    0xEA200000
 
-#define S5P6442_PA_IIC0                (0xEC100000)
+#define S5P6442_PA_UART                0xEC000000
 
-#define S5P6442_PA_SDRAM       (0x20000000)
-#define S5P_PA_SDRAM           S5P6442_PA_SDRAM
+#define S5P6442_PA_IIC0                0xEC100000
 
 #define S5P6442_PA_SPI         0xEC300000
 
-/* I2S */
-#define S5P6442_PA_I2S0                0xC0B00000
-#define S5P6442_PA_I2S1                0xF2200000
-
-/* PCM */
 #define S5P6442_PA_PCM0                0xF2400000
 #define S5P6442_PA_PCM1                0xF2500000
 
-/* compatibiltiy defines. */
+/* Compatibiltiy Defines */
+
+#define S3C_PA_IIC             S5P6442_PA_IIC0
 #define S3C_PA_WDT             S5P6442_PA_WATCHDOG
+
+#define S5P_PA_CHIPID          S5P6442_PA_CHIPID
+#define S5P_PA_SDRAM           S5P6442_PA_SDRAM
+#define S5P_PA_SROMC           S5P6442_PA_SROMC
+#define S5P_PA_SYSCON          S5P6442_PA_SYSCON
+#define S5P_PA_TIMER           S5P6442_PA_TIMER
+
+/* UART */
+
 #define S3C_PA_UART            S5P6442_PA_UART
-#define S3C_PA_IIC             S5P6442_PA_IIC0
+
+#define S5P_PA_UART(x)         (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0           S5P_PA_UART(0)
+#define S5P_PA_UART1           S5P_PA_UART(1)
+#define S5P_PA_UART2           S5P_PA_UART(2)
+
+#define S5P_SZ_UART            SZ_256
 
 #endif /* __ASM_ARCH_MAP_H */
index a9365e5..95c9125 100644 (file)
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s5p64x0/include/mach/map.h
  *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
  *             http://www.samsung.com
  *
  * S5P64X0 - Memory map definitions
 #include <plat/map-base.h>
 #include <plat/map-s5p.h>
 
-#define S5P64X0_PA_SDRAM       (0x20000000)
+#define S5P64X0_PA_SDRAM       0x20000000
 
-#define S5P64X0_PA_CHIPID      (0xE0000000)
-#define S5P_PA_CHIPID          S5P64X0_PA_CHIPID
-
-#define S5P64X0_PA_SYSCON      (0xE0100000)
-#define S5P_PA_SYSCON          S5P64X0_PA_SYSCON
-
-#define S5P64X0_PA_GPIO                (0xE0308000)
-
-#define S5P64X0_PA_VIC0                (0xE4000000)
-#define S5P64X0_PA_VIC1                (0xE4100000)
+#define S5P64X0_PA_CHIPID      0xE0000000
 
-#define S5P64X0_PA_SROMC       (0xE7000000)
-#define S5P_PA_SROMC           S5P64X0_PA_SROMC
-
-#define S5P64X0_PA_PDMA                (0xE9000000)
-
-#define S5P64X0_PA_TIMER       (0xEA000000)
-#define S5P_PA_TIMER           S5P64X0_PA_TIMER
+#define S5P64X0_PA_SYSCON      0xE0100000
 
-#define S5P64X0_PA_RTC         (0xEA100000)
+#define S5P64X0_PA_GPIO                0xE0308000
 
-#define S5P64X0_PA_WDT         (0xEA200000)
+#define S5P64X0_PA_VIC0                0xE4000000
+#define S5P64X0_PA_VIC1                0xE4100000
 
-#define S5P6440_PA_UART(x)     (0xEC000000 + ((x) * S3C_UART_OFFSET))
-#define S5P6450_PA_UART(x)     ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
+#define S5P64X0_PA_SROMC       0xE7000000
 
-#define S5P_PA_UART0           S5P6450_PA_UART(0)
-#define S5P_PA_UART1           S5P6450_PA_UART(1)
-#define S5P_PA_UART2           S5P6450_PA_UART(2)
-#define S5P_PA_UART3           S5P6450_PA_UART(3)
-#define S5P_PA_UART4           S5P6450_PA_UART(4)
-#define S5P_PA_UART5           S5P6450_PA_UART(5)
+#define S5P64X0_PA_PDMA                0xE9000000
 
-#define S5P_SZ_UART            SZ_256
+#define S5P64X0_PA_TIMER       0xEA000000
+#define S5P64X0_PA_RTC         0xEA100000
+#define S5P64X0_PA_WDT         0xEA200000
 
-#define S5P6440_PA_IIC0                (0xEC104000)
-#define S5P6440_PA_IIC1                (0xEC20F000)
-#define S5P6450_PA_IIC0                (0xEC100000)
-#define S5P6450_PA_IIC1                (0xEC200000)
+#define S5P6440_PA_IIC0                0xEC104000
+#define S5P6440_PA_IIC1                0xEC20F000
+#define S5P6450_PA_IIC0                0xEC100000
+#define S5P6450_PA_IIC1                0xEC200000
 
-#define S5P64X0_PA_SPI0                (0xEC400000)
-#define S5P64X0_PA_SPI1                (0xEC500000)
+#define S5P64X0_PA_SPI0                0xEC400000
+#define S5P64X0_PA_SPI1                0xEC500000
 
-#define S5P64X0_PA_HSOTG       (0xED100000)
+#define S5P64X0_PA_HSOTG       0xED100000
 
 #define S5P64X0_PA_HSMMC(x)    (0xED800000 + ((x) * 0x100000))
 
-#define S5P64X0_PA_I2S         (0xF2000000)
+#define S5P64X0_PA_I2S         0xF2000000
 #define S5P6450_PA_I2S1                0xF2800000
 #define S5P6450_PA_I2S2                0xF2900000
 
-#define S5P64X0_PA_PCM         (0xF2100000)
+#define S5P64X0_PA_PCM         0xF2100000
 
-#define S5P64X0_PA_ADC         (0xF3000000)
+#define S5P64X0_PA_ADC         0xF3000000
 
-/* compatibiltiy defines. */
+/* Compatibiltiy Defines */
 
 #define S3C_PA_HSMMC0          S5P64X0_PA_HSMMC(0)
 #define S3C_PA_HSMMC1          S5P64X0_PA_HSMMC(1)
 #define S3C_PA_RTC             S5P64X0_PA_RTC
 #define S3C_PA_WDT             S5P64X0_PA_WDT
 
+#define S5P_PA_CHIPID          S5P64X0_PA_CHIPID
+#define S5P_PA_SROMC           S5P64X0_PA_SROMC
+#define S5P_PA_SYSCON          S5P64X0_PA_SYSCON
+#define S5P_PA_TIMER           S5P64X0_PA_TIMER
+
 #define SAMSUNG_PA_ADC         S5P64X0_PA_ADC
 
+/* UART */
+
+#define S5P6440_PA_UART(x)     (0xEC000000 + ((x) * S3C_UART_OFFSET))
+#define S5P6450_PA_UART(x)     ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
+
+#define S5P_PA_UART0           S5P6450_PA_UART(0)
+#define S5P_PA_UART1           S5P6450_PA_UART(1)
+#define S5P_PA_UART2           S5P6450_PA_UART(2)
+#define S5P_PA_UART3           S5P6450_PA_UART(3)
+#define S5P_PA_UART4           S5P6450_PA_UART(4)
+#define S5P_PA_UART5           S5P6450_PA_UART(5)
+
+#define S5P_SZ_UART            SZ_256
+
 #endif /* __ASM_ARCH_MAP_H */
index 328467b..ccbe6b7 100644 (file)
@@ -1,5 +1,8 @@
 /* linux/arch/arm/mach-s5pc100/include/mach/map.h
  *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com/
+ *
  * Copyright 2009 Samsung Electronics Co.
  *     Byungho Min <bhmin@samsung.com>
  *
 #include <plat/map-base.h>
 #include <plat/map-s5p.h>
 
-/*
- * map-base.h has already defined virtual memory address
- * S3C_VA_IRQ          S3C_ADDR(0x00000000)    irq controller(s)
- * S3C_VA_SYS          S3C_ADDR(0x00100000)    system control
- * S3C_VA_MEM          S3C_ADDR(0x00200000)    system control (not used)
- * S3C_VA_TIMER                S3C_ADDR(0x00300000)    timer block
- * S3C_VA_WATCHDOG     S3C_ADDR(0x00400000)    watchdog
- * S3C_VA_UART         S3C_ADDR(0x01000000)    UART
- *
- * S5PC100 specific virtual memory address can be defined here
- * S5PC1XX_VA_GPIO     S3C_ADDR(0x00500000)    GPIO
- *
- */
+#define S5PC100_PA_SDRAM               0x20000000
+
+#define S5PC100_PA_ONENAND             0xE7100000
+#define S5PC100_PA_ONENAND_BUF         0xB0000000
+
+#define S5PC100_PA_CHIPID              0xE0000000
 
-#define S5PC100_PA_ONENAND_BUF (0xB0000000)
-#define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
+#define S5PC100_PA_SYSCON              0xE0100000
 
-/* Chip ID */
+#define S5PC100_PA_OTHERS              0xE0200000
 
-#define S5PC100_PA_CHIPID      (0xE0000000)
-#define S5P_PA_CHIPID          S5PC100_PA_CHIPID
+#define S5PC100_PA_GPIO                        0xE0300000
 
-#define S5PC100_PA_SYSCON      (0xE0100000)
-#define S5P_PA_SYSCON          S5PC100_PA_SYSCON
+#define S5PC100_PA_VIC0                        0xE4000000
+#define S5PC100_PA_VIC1                        0xE4100000
+#define S5PC100_PA_VIC2                        0xE4200000
 
-#define S5PC100_PA_OTHERS      (0xE0200000)
-#define S5PC100_VA_OTHERS      (S3C_VA_SYS + 0x10000)
+#define S5PC100_PA_SROMC               0xE7000000
 
-#define S5PC100_PA_GPIO                (0xE0300000)
-#define S5PC1XX_VA_GPIO                S3C_ADDR(0x00500000)
+#define S5PC100_PA_CFCON               0xE7800000
 
-/* Interrupt */
-#define S5PC100_PA_VIC0                (0xE4000000)
-#define S5PC100_PA_VIC1                (0xE4100000)
-#define S5PC100_PA_VIC2                (0xE4200000)
-#define S5PC100_VA_VIC         S3C_VA_IRQ
-#define S5PC100_VA_VIC_OFFSET  0x10000
-#define S5PC1XX_VA_VIC(x)      (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
+#define S5PC100_PA_MDMA                        0xE8100000
+#define S5PC100_PA_PDMA0               0xE9000000
+#define S5PC100_PA_PDMA1               0xE9200000
 
-#define S5PC100_PA_SROMC       (0xE7000000)
-#define S5P_PA_SROMC           S5PC100_PA_SROMC
+#define S5PC100_PA_TIMER               0xEA000000
+#define S5PC100_PA_SYSTIMER            0xEA100000
+#define S5PC100_PA_WATCHDOG            0xEA200000
+#define S5PC100_PA_RTC                 0xEA300000
 
-#define S5PC100_PA_ONENAND     (0xE7100000)
+#define S5PC100_PA_UART                        0xEC000000
 
-#define S5PC100_PA_CFCON       (0xE7800000)
+#define S5PC100_PA_IIC0                        0xEC100000
+#define S5PC100_PA_IIC1                        0xEC200000
 
-/* DMA */
-#define S5PC100_PA_MDMA                (0xE8100000)
-#define S5PC100_PA_PDMA0       (0xE9000000)
-#define S5PC100_PA_PDMA1       (0xE9200000)
+#define S5PC100_PA_SPI0                        0xEC300000
+#define S5PC100_PA_SPI1                        0xEC400000
+#define S5PC100_PA_SPI2                        0xEC500000
 
-/* Timer */
-#define S5PC100_PA_TIMER       (0xEA000000)
-#define S5P_PA_TIMER           S5PC100_PA_TIMER
+#define S5PC100_PA_USB_HSOTG           0xED200000
+#define S5PC100_PA_USB_HSPHY           0xED300000
 
-#define S5PC100_PA_SYSTIMER    (0xEA100000)
+#define S5PC100_PA_HSMMC(x)            (0xED800000 + ((x) * 0x100000))
 
-#define S5PC100_PA_WATCHDOG    (0xEA200000)
-#define S5PC100_PA_RTC         (0xEA300000)
+#define S5PC100_PA_FB                  0xEE000000
 
-#define S5PC100_PA_UART                (0xEC000000)
+#define S5PC100_PA_FIMC0               0xEE200000
+#define S5PC100_PA_FIMC1               0xEE300000
+#define S5PC100_PA_FIMC2               0xEE400000
 
-#define S5P_PA_UART0           (S5PC100_PA_UART + 0x0)
-#define S5P_PA_UART1           (S5PC100_PA_UART + 0x400)
-#define S5P_PA_UART2           (S5PC100_PA_UART + 0x800)
-#define S5P_PA_UART3           (S5PC100_PA_UART + 0xC00)
-#define S5P_SZ_UART            SZ_256
+#define S5PC100_PA_I2S0                        0xF2000000
+#define S5PC100_PA_I2S1                        0xF2100000
+#define S5PC100_PA_I2S2                        0xF2200000
 
-#define S5PC100_PA_IIC0                (0xEC100000)
-#define S5PC100_PA_IIC1                (0xEC200000)
+#define S5PC100_PA_AC97                        0xF2300000
 
-/* SPI */
-#define S5PC100_PA_SPI0                0xEC300000
-#define S5PC100_PA_SPI1                0xEC400000
-#define S5PC100_PA_SPI2                0xEC500000
+#define S5PC100_PA_PCM0                        0xF2400000
+#define S5PC100_PA_PCM1                        0xF2500000
 
-/* USB HS OTG */
-#define S5PC100_PA_USB_HSOTG   (0xED200000)
-#define S5PC100_PA_USB_HSPHY   (0xED300000)
+#define S5PC100_PA_SPDIF               0xF2600000
 
-#define S5PC100_PA_FB          (0xEE000000)
+#define S5PC100_PA_TSADC               0xF3000000
 
-#define S5PC100_PA_FIMC0       (0xEE200000)
-#define S5PC100_PA_FIMC1       (0xEE300000)
-#define S5PC100_PA_FIMC2       (0xEE400000)
+#define S5PC100_PA_KEYPAD              0xF3100000
 
-#define S5PC100_PA_I2S0                (0xF2000000)
-#define S5PC100_PA_I2S1                (0xF2100000)
-#define S5PC100_PA_I2S2                (0xF2200000)
+/* Compatibiltiy Defines */
 
-#define S5PC100_PA_AC97                0xF2300000
+#define S3C_PA_FB                      S5PC100_PA_FB
+#define S3C_PA_HSMMC0                  S5PC100_PA_HSMMC(0)
+#define S3C_PA_HSMMC1                  S5PC100_PA_HSMMC(1)
+#define S3C_PA_HSMMC2                  S5PC100_PA_HSMMC(2)
+#define S3C_PA_IIC                     S5PC100_PA_IIC0
+#define S3C_PA_IIC1                    S5PC100_PA_IIC1
+#define S3C_PA_KEYPAD                  S5PC100_PA_KEYPAD
+#define S3C_PA_ONENAND                 S5PC100_PA_ONENAND
+#define S3C_PA_ONENAND_BUF             S5PC100_PA_ONENAND_BUF
+#define S3C_PA_RTC                     S5PC100_PA_RTC
+#define S3C_PA_TSADC                   S5PC100_PA_TSADC
+#define S3C_PA_USB_HSOTG               S5PC100_PA_USB_HSOTG
+#define S3C_PA_USB_HSPHY               S5PC100_PA_USB_HSPHY
+#define S3C_PA_WDT                     S5PC100_PA_WATCHDOG
 
-/* PCM */
-#define S5PC100_PA_PCM0                0xF2400000
-#define S5PC100_PA_PCM1                0xF2500000
+#define S5P_PA_CHIPID                  S5PC100_PA_CHIPID
+#define S5P_PA_FIMC0                   S5PC100_PA_FIMC0
+#define S5P_PA_FIMC1                   S5PC100_PA_FIMC1
+#define S5P_PA_FIMC2                   S5PC100_PA_FIMC2
+#define S5P_PA_SDRAM                   S5PC100_PA_SDRAM
+#define S5P_PA_SROMC                   S5PC100_PA_SROMC
+#define S5P_PA_SYSCON                  S5PC100_PA_SYSCON
+#define S5P_PA_TIMER                   S5PC100_PA_TIMER
 
-#define S5PC100_PA_SPDIF       0xF2600000
+#define SAMSUNG_PA_ADC                 S5PC100_PA_TSADC
+#define SAMSUNG_PA_CFCON               S5PC100_PA_CFCON
+#define SAMSUNG_PA_KEYPAD              S5PC100_PA_KEYPAD
 
-#define S5PC100_PA_TSADC       (0xF3000000)
+#define S5PC100_VA_OTHERS              (S3C_VA_SYS + 0x10000)
 
-/* KEYPAD */
-#define S5PC100_PA_KEYPAD      (0xF3100000)
+#define S3C_SZ_ONENAND_BUF             (SZ_256M - SZ_32M)
 
-#define S5PC100_PA_HSMMC(x)    (0xED800000 + ((x) * 0x100000))
+/* UART */
 
-#define S5PC100_PA_SDRAM       (0x20000000)
-#define S5P_PA_SDRAM           S5PC100_PA_SDRAM
+#define S3C_PA_UART                    S5PC100_PA_UART
 
-/* compatibiltiy defines. */
-#define S3C_PA_UART            S5PC100_PA_UART
-#define S3C_PA_IIC             S5PC100_PA_IIC0
-#define S3C_PA_IIC1            S5PC100_PA_IIC1
-#define S3C_PA_FB              S5PC100_PA_FB
-#define S3C_PA_G2D             S5PC100_PA_G2D
-#define S3C_PA_G3D             S5PC100_PA_G3D
-#define S3C_PA_JPEG            S5PC100_PA_JPEG
-#define S3C_PA_ROTATOR         S5PC100_PA_ROTATOR
-#define S5P_VA_VIC0            S5PC1XX_VA_VIC(0)
-#define S5P_VA_VIC1            S5PC1XX_VA_VIC(1)
-#define S5P_VA_VIC2            S5PC1XX_VA_VIC(2)
-#define S3C_PA_USB_HSOTG       S5PC100_PA_USB_HSOTG
-#define S3C_PA_USB_HSPHY       S5PC100_PA_USB_HSPHY
-#define S3C_PA_HSMMC0          S5PC100_PA_HSMMC(0)
-#define S3C_PA_HSMMC1          S5PC100_PA_HSMMC(1)
-#define S3C_PA_HSMMC2          S5PC100_PA_HSMMC(2)
-#define S3C_PA_KEYPAD          S5PC100_PA_KEYPAD
-#define S3C_PA_WDT             S5PC100_PA_WATCHDOG
-#define S3C_PA_TSADC           S5PC100_PA_TSADC
-#define S3C_PA_ONENAND         S5PC100_PA_ONENAND
-#define S3C_PA_ONENAND_BUF     S5PC100_PA_ONENAND_BUF
-#define S3C_SZ_ONENAND_BUF     S5PC100_SZ_ONENAND_BUF
-#define S3C_PA_RTC             S5PC100_PA_RTC
-
-#define SAMSUNG_PA_ADC         S5PC100_PA_TSADC
-#define SAMSUNG_PA_CFCON       S5PC100_PA_CFCON
-#define SAMSUNG_PA_KEYPAD      S5PC100_PA_KEYPAD
+#define S5P_PA_UART(x)                 (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0                   S5P_PA_UART(0)
+#define S5P_PA_UART1                   S5P_PA_UART(1)
+#define S5P_PA_UART2                   S5P_PA_UART(2)
+#define S5P_PA_UART3                   S5P_PA_UART(3)
 
-#define S5P_PA_FIMC0           S5PC100_PA_FIMC0
-#define S5P_PA_FIMC1           S5PC100_PA_FIMC1
-#define S5P_PA_FIMC2           S5PC100_PA_FIMC2
+#define S5P_SZ_UART                    SZ_256
 
-#endif /* __ASM_ARCH_C100_MAP_H */
+#endif /* __ASM_ARCH_MAP_H */
index 3611492..1dd5883 100644 (file)
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s5pv210/include/mach/map.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *             http://www.samsung.com/
  *
  * S5PV210 - Memory map definitions
 #include <plat/map-base.h>
 #include <plat/map-s5p.h>
 
-#define S5PV210_PA_SROM_BANK5  (0xA8000000)
+#define S5PV210_PA_SDRAM               0x20000000
 
-#define S5PC110_PA_ONENAND     (0xB0000000)
-#define S5P_PA_ONENAND         S5PC110_PA_ONENAND
+#define S5PV210_PA_SROM_BANK5          0xA8000000
 
-#define S5PC110_PA_ONENAND_DMA (0xB0600000)
-#define S5P_PA_ONENAND_DMA     S5PC110_PA_ONENAND_DMA
+#define S5PC110_PA_ONENAND             0xB0000000
+#define S5PC110_PA_ONENAND_DMA         0xB0600000
 
-#define S5PV210_PA_CHIPID      (0xE0000000)
-#define S5P_PA_CHIPID          S5PV210_PA_CHIPID
+#define S5PV210_PA_CHIPID              0xE0000000
 
-#define S5PV210_PA_SYSCON      (0xE0100000)
-#define S5P_PA_SYSCON          S5PV210_PA_SYSCON
+#define S5PV210_PA_SYSCON              0xE0100000
 
-#define S5PV210_PA_GPIO                (0xE0200000)
+#define S5PV210_PA_GPIO                        0xE0200000
 
-/* SPI */
-#define S5PV210_PA_SPI0                0xE1300000
-#define S5PV210_PA_SPI1                0xE1400000
+#define S5PV210_PA_SPDIF               0xE1100000
 
-#define S5PV210_PA_KEYPAD      (0xE1600000)
+#define S5PV210_PA_SPI0                        0xE1300000
+#define S5PV210_PA_SPI1                        0xE1400000
 
-#define S5PV210_PA_IIC0                (0xE1800000)
-#define S5PV210_PA_IIC1                (0xFAB00000)
-#define S5PV210_PA_IIC2                (0xE1A00000)
+#define S5PV210_PA_KEYPAD              0xE1600000
 
-#define S5PV210_PA_TIMER       (0xE2500000)
-#define S5P_PA_TIMER           S5PV210_PA_TIMER
+#define S5PV210_PA_ADC                 0xE1700000
 
-#define S5PV210_PA_SYSTIMER    (0xE2600000)
+#define S5PV210_PA_IIC0                        0xE1800000
+#define S5PV210_PA_IIC1                        0xFAB00000
+#define S5PV210_PA_IIC2                        0xE1A00000
 
-#define S5PV210_PA_WATCHDOG    (0xE2700000)
+#define S5PV210_PA_AC97                        0xE2200000
 
-#define S5PV210_PA_RTC         (0xE2800000)
-#define S5PV210_PA_UART                (0xE2900000)
+#define S5PV210_PA_PCM0                        0xE2300000
+#define S5PV210_PA_PCM1                        0xE1200000
+#define S5PV210_PA_PCM2                        0xE2B00000
 
-#define S5P_PA_UART0           (S5PV210_PA_UART + 0x0)
-#define S5P_PA_UART1           (S5PV210_PA_UART + 0x400)
-#define S5P_PA_UART2           (S5PV210_PA_UART + 0x800)
-#define S5P_PA_UART3           (S5PV210_PA_UART + 0xC00)
+#define S5PV210_PA_TIMER               0xE2500000
+#define S5PV210_PA_SYSTIMER            0xE2600000
+#define S5PV210_PA_WATCHDOG            0xE2700000
+#define S5PV210_PA_RTC                 0xE2800000
 
-#define S5P_SZ_UART            SZ_256
+#define S5PV210_PA_UART                        0xE2900000
 
-#define S3C_VA_UARTx(x)                (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+#define S5PV210_PA_SROMC               0xE8000000
 
-#define S5PV210_PA_SROMC       (0xE8000000)
-#define S5P_PA_SROMC           S5PV210_PA_SROMC
+#define S5PV210_PA_CFCON               0xE8200000
 
-#define S5PV210_PA_CFCON       (0xE8200000)
+#define S5PV210_PA_HSMMC(x)            (0xEB000000 + ((x) * 0x100000))
 
-#define S5PV210_PA_MDMA                0xFA200000
-#define S5PV210_PA_PDMA0       0xE0900000
-#define S5PV210_PA_PDMA1       0xE0A00000
+#define S5PV210_PA_HSOTG               0xEC000000
+#define S5PV210_PA_HSPHY               0xEC100000
 
-#define S5PV210_PA_FB          (0xF8000000)
+#define S5PV210_PA_IIS0                        0xEEE30000
+#define S5PV210_PA_IIS1                        0xE2100000
+#define S5PV210_PA_IIS2                        0xE2A00000
 
-#define S5PV210_PA_FIMC0       (0xFB200000)
-#define S5PV210_PA_FIMC1       (0xFB300000)
-#define S5PV210_PA_FIMC2       (0xFB400000)
+#define S5PV210_PA_DMC0                        0xF0000000
+#define S5PV210_PA_DMC1                        0xF1400000
 
-#define S5PV210_PA_HSMMC(x)    (0xEB000000 + ((x) * 0x100000))
+#define S5PV210_PA_VIC0                        0xF2000000
+#define S5PV210_PA_VIC1                        0xF2100000
+#define S5PV210_PA_VIC2                        0xF2200000
+#define S5PV210_PA_VIC3                        0xF2300000
 
-#define S5PV210_PA_HSOTG       (0xEC000000)
-#define S5PV210_PA_HSPHY       (0xEC100000)
+#define S5PV210_PA_FB                  0xF8000000
 
-#define S5PV210_PA_VIC0                (0xF2000000)
-#define S5PV210_PA_VIC1                (0xF2100000)
-#define S5PV210_PA_VIC2                (0xF2200000)
-#define S5PV210_PA_VIC3                (0xF2300000)
+#define S5PV210_PA_MDMA                        0xFA200000
+#define S5PV210_PA_PDMA0               0xE0900000
+#define S5PV210_PA_PDMA1               0xE0A00000
 
-#define S5PV210_PA_SDRAM       (0x20000000)
-#define S5P_PA_SDRAM           S5PV210_PA_SDRAM
+#define S5PV210_PA_MIPI_CSIS           0xFA600000
 
-/* S/PDIF */
-#define S5PV210_PA_SPDIF       0xE1100000
+#define S5PV210_PA_FIMC0               0xFB200000
+#define S5PV210_PA_FIMC1               0xFB300000
+#define S5PV210_PA_FIMC2               0xFB400000
 
-/* I2S */
-#define S5PV210_PA_IIS0                0xEEE30000
-#define S5PV210_PA_IIS1                0xE2100000
-#define S5PV210_PA_IIS2                0xE2A00000
+/* Compatibiltiy Defines */
 
-/* PCM */
-#define S5PV210_PA_PCM0                0xE2300000
-#define S5PV210_PA_PCM1                0xE1200000
-#define S5PV210_PA_PCM2                0xE2B00000
+#define S3C_PA_FB                      S5PV210_PA_FB
+#define S3C_PA_HSMMC0                  S5PV210_PA_HSMMC(0)
+#define S3C_PA_HSMMC1                  S5PV210_PA_HSMMC(1)
+#define S3C_PA_HSMMC2                  S5PV210_PA_HSMMC(2)
+#define S3C_PA_HSMMC3                  S5PV210_PA_HSMMC(3)
+#define S3C_PA_IIC                     S5PV210_PA_IIC0
+#define S3C_PA_IIC1                    S5PV210_PA_IIC1
+#define S3C_PA_IIC2                    S5PV210_PA_IIC2
+#define S3C_PA_RTC                     S5PV210_PA_RTC
+#define S3C_PA_USB_HSOTG               S5PV210_PA_HSOTG
+#define S3C_PA_WDT                     S5PV210_PA_WATCHDOG
 
-/* AC97 */
-#define S5PV210_PA_AC97                0xE2200000
+#define S5P_PA_CHIPID                  S5PV210_PA_CHIPID
+#define S5P_PA_FIMC0                   S5PV210_PA_FIMC0
+#define S5P_PA_FIMC1                   S5PV210_PA_FIMC1
+#define S5P_PA_FIMC2                   S5PV210_PA_FIMC2
+#define S5P_PA_MIPI_CSIS0              S5PV210_PA_MIPI_CSIS
+#define S5P_PA_ONENAND                 S5PC110_PA_ONENAND
+#define S5P_PA_ONENAND_DMA             S5PC110_PA_ONENAND_DMA
+#define S5P_PA_SDRAM                   S5PV210_PA_SDRAM
+#define S5P_PA_SROMC                   S5PV210_PA_SROMC
+#define S5P_PA_SYSCON                  S5PV210_PA_SYSCON
+#define S5P_PA_TIMER                   S5PV210_PA_TIMER
 
-#define S5PV210_PA_ADC         (0xE1700000)
+#define SAMSUNG_PA_ADC                 S5PV210_PA_ADC
+#define SAMSUNG_PA_CFCON               S5PV210_PA_CFCON
+#define SAMSUNG_PA_KEYPAD              S5PV210_PA_KEYPAD
 
-#define S5PV210_PA_DMC0                (0xF0000000)
-#define S5PV210_PA_DMC1                (0xF1400000)
+/* UART */
 
-#define S5PV210_PA_MIPI_CSIS   0xFA600000
+#define S3C_VA_UARTx(x)                        (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
-/* compatibiltiy defines. */
-#define S3C_PA_UART            S5PV210_PA_UART
-#define S3C_PA_HSMMC0          S5PV210_PA_HSMMC(0)
-#define S3C_PA_HSMMC1          S5PV210_PA_HSMMC(1)
-#define S3C_PA_HSMMC2          S5PV210_PA_HSMMC(2)
-#define S3C_PA_HSMMC3          S5PV210_PA_HSMMC(3)
-#define S3C_PA_IIC             S5PV210_PA_IIC0
-#define S3C_PA_IIC1            S5PV210_PA_IIC1
-#define S3C_PA_IIC2            S5PV210_PA_IIC2
-#define S3C_PA_FB              S5PV210_PA_FB
-#define S3C_PA_RTC             S5PV210_PA_RTC
-#define S3C_PA_WDT             S5PV210_PA_WATCHDOG
-#define S3C_PA_USB_HSOTG       S5PV210_PA_HSOTG
-#define S5P_PA_FIMC0           S5PV210_PA_FIMC0
-#define S5P_PA_FIMC1           S5PV210_PA_FIMC1
-#define S5P_PA_FIMC2           S5PV210_PA_FIMC2
-#define S5P_PA_MIPI_CSIS0      S5PV210_PA_MIPI_CSIS
+#define S3C_PA_UART                    S5PV210_PA_UART
 
-#define SAMSUNG_PA_ADC         S5PV210_PA_ADC
-#define SAMSUNG_PA_CFCON       S5PV210_PA_CFCON
-#define SAMSUNG_PA_KEYPAD      S5PV210_PA_KEYPAD
+#define S5P_PA_UART(x)                 (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0                   S5P_PA_UART(0)
+#define S5P_PA_UART1                   S5P_PA_UART(1)
+#define S5P_PA_UART2                   S5P_PA_UART(2)
+#define S5P_PA_UART3                   S5P_PA_UART(3)
+
+#define S5P_SZ_UART                    SZ_256
 
 #endif /* __ASM_ARCH_MAP_H */
index 461aa03..557add4 100644 (file)
@@ -149,7 +149,7 @@ static struct regulator_init_data aquila_ldo2_data = {
 
 static struct regulator_init_data aquila_ldo3_data = {
        .constraints    = {
-               .name           = "VUSB/MIPI_1.1V",
+               .name           = "VUSB+MIPI_1.1V",
                .min_uV         = 1100000,
                .max_uV         = 1100000,
                .apply_uV       = 1,
@@ -197,7 +197,7 @@ static struct regulator_init_data aquila_ldo7_data = {
 
 static struct regulator_init_data aquila_ldo8_data = {
        .constraints    = {
-               .name           = "VUSB/VADC_3.3V",
+               .name           = "VUSB+VADC_3.3V",
                .min_uV         = 3300000,
                .max_uV         = 3300000,
                .apply_uV       = 1,
@@ -207,7 +207,7 @@ static struct regulator_init_data aquila_ldo8_data = {
 
 static struct regulator_init_data aquila_ldo9_data = {
        .constraints    = {
-               .name           = "VCC/VCAM_2.8V",
+               .name           = "VCC+VCAM_2.8V",
                .min_uV         = 2800000,
                .max_uV         = 2800000,
                .apply_uV       = 1,
@@ -381,9 +381,12 @@ static struct max8998_platform_data aquila_max8998_pdata = {
        .buck1_set1     = S5PV210_GPH0(3),
        .buck1_set2     = S5PV210_GPH0(4),
        .buck2_set3     = S5PV210_GPH0(5),
-       .buck1_max_voltage1 = 1200000,
-       .buck1_max_voltage2 = 1200000,
-       .buck2_max_voltage = 1200000,
+       .buck1_voltage1 = 1200000,
+       .buck1_voltage2 = 1200000,
+       .buck1_voltage3 = 1200000,
+       .buck1_voltage4 = 1200000,
+       .buck2_voltage1 = 1200000,
+       .buck2_voltage2 = 1200000,
 };
 #endif
 
index e22d511..056f5c7 100644 (file)
@@ -288,7 +288,7 @@ static struct regulator_init_data goni_ldo2_data = {
 
 static struct regulator_init_data goni_ldo3_data = {
        .constraints    = {
-               .name           = "VUSB/MIPI_1.1V",
+               .name           = "VUSB+MIPI_1.1V",
                .min_uV         = 1100000,
                .max_uV         = 1100000,
                .apply_uV       = 1,
@@ -337,7 +337,7 @@ static struct regulator_init_data goni_ldo7_data = {
 
 static struct regulator_init_data goni_ldo8_data = {
        .constraints    = {
-               .name           = "VUSB/VADC_3.3V",
+               .name           = "VUSB+VADC_3.3V",
                .min_uV         = 3300000,
                .max_uV         = 3300000,
                .apply_uV       = 1,
@@ -347,7 +347,7 @@ static struct regulator_init_data goni_ldo8_data = {
 
 static struct regulator_init_data goni_ldo9_data = {
        .constraints    = {
-               .name           = "VCC/VCAM_2.8V",
+               .name           = "VCC+VCAM_2.8V",
                .min_uV         = 2800000,
                .max_uV         = 2800000,
                .apply_uV       = 1,
@@ -521,9 +521,12 @@ static struct max8998_platform_data goni_max8998_pdata = {
        .buck1_set1     = S5PV210_GPH0(3),
        .buck1_set2     = S5PV210_GPH0(4),
        .buck2_set3     = S5PV210_GPH0(5),
-       .buck1_max_voltage1 = 1200000,
-       .buck1_max_voltage2 = 1200000,
-       .buck2_max_voltage = 1200000,
+       .buck1_voltage1 = 1200000,
+       .buck1_voltage2 = 1200000,
+       .buck1_voltage3 = 1200000,
+       .buck1_voltage4 = 1200000,
+       .buck2_voltage1 = 1200000,
+       .buck2_voltage2 = 1200000,
 };
 #endif
 
index 3060f78..901657f 100644 (file)
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s5pv310/include/mach/map.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *             http://www.samsung.com/
  *
  * S5PV310 - Memory map definitions
 
 #include <plat/map-s5p.h>
 
-#define S5PV310_PA_SYSRAM              (0x02025000)
+#define S5PV310_PA_SYSRAM              0x02025000
 
-#define S5PV310_PA_SROM_BANK(x)                (0x04000000 + ((x) * 0x01000000))
-
-#define S5PC210_PA_ONENAND             (0x0C000000)
-#define S5P_PA_ONENAND                 S5PC210_PA_ONENAND
-
-#define S5PC210_PA_ONENAND_DMA         (0x0C600000)
-#define S5P_PA_ONENAND_DMA             S5PC210_PA_ONENAND_DMA
-
-#define S5PV310_PA_CHIPID              (0x10000000)
-#define S5P_PA_CHIPID                  S5PV310_PA_CHIPID
-
-#define S5PV310_PA_SYSCON              (0x10010000)
-#define S5P_PA_SYSCON                  S5PV310_PA_SYSCON
+#define S5PV310_PA_I2S0                        0x03830000
+#define S5PV310_PA_I2S1                        0xE3100000
+#define S5PV310_PA_I2S2                        0xE2A00000
 
-#define S5PV310_PA_PMU                 (0x10020000)
+#define S5PV310_PA_PCM0                        0x03840000
+#define S5PV310_PA_PCM1                        0x13980000
+#define S5PV310_PA_PCM2                        0x13990000
 
-#define S5PV310_PA_CMU                 (0x10030000)
-
-#define S5PV310_PA_WATCHDOG            (0x10060000)
-#define S5PV310_PA_RTC                 (0x10070000)
-
-#define S5PV310_PA_DMC0                        (0x10400000)
-
-#define S5PV310_PA_COMBINER            (0x10448000)
-
-#define S5PV310_PA_COREPERI            (0x10500000)
-#define S5PV310_PA_GIC_CPU             (0x10500100)
-#define S5PV310_PA_TWD                 (0x10500600)
-#define S5PV310_PA_GIC_DIST            (0x10501000)
-#define S5PV310_PA_L2CC                        (0x10502000)
-
-/* DMA */
-#define S5PV310_PA_MDMA                0x10810000
-#define S5PV310_PA_PDMA0       0x12680000
-#define S5PV310_PA_PDMA1       0x12690000
-
-#define S5PV310_PA_GPIO1               (0x11400000)
-#define S5PV310_PA_GPIO2               (0x11000000)
-#define S5PV310_PA_GPIO3               (0x03860000)
-
-#define S5PV310_PA_MIPI_CSIS0          0x11880000
-#define S5PV310_PA_MIPI_CSIS1          0x11890000
+#define S5PV310_PA_SROM_BANK(x)                (0x04000000 + ((x) * 0x01000000))
 
-#define S5PV310_PA_HSMMC(x)            (0x12510000 + ((x) * 0x10000))
+#define S5PC210_PA_ONENAND             0x0C000000
+#define S5PC210_PA_ONENAND_DMA         0x0C600000
 
-#define S5PV310_PA_SROMC               (0x12570000)
-#define S5P_PA_SROMC                   S5PV310_PA_SROMC
+#define S5PV310_PA_CHIPID              0x10000000
 
-/* S/PDIF */
-#define S5PV310_PA_SPDIF       0xE1100000
+#define S5PV310_PA_SYSCON              0x10010000
+#define S5PV310_PA_PMU                 0x10020000
+#define S5PV310_PA_CMU                 0x10030000
 
-/* I2S */
-#define S5PV310_PA_I2S0                0x03830000
-#define S5PV310_PA_I2S1                0xE3100000
-#define S5PV310_PA_I2S2                0xE2A00000
+#define S5PV310_PA_WATCHDOG            0x10060000
+#define S5PV310_PA_RTC                 0x10070000
 
-/* PCM */
-#define S5PV310_PA_PCM0                0x03840000
-#define S5PV310_PA_PCM1                0x13980000
-#define S5PV310_PA_PCM2                0x13990000
+#define S5PV310_PA_DMC0                        0x10400000
 
-/* AC97 */
-#define S5PV310_PA_AC97                0x139A0000
+#define S5PV310_PA_COMBINER            0x10448000
 
-#define S5PV310_PA_UART                        (0x13800000)
+#define S5PV310_PA_COREPERI            0x10500000
+#define S5PV310_PA_GIC_CPU             0x10500100
+#define S5PV310_PA_TWD                 0x10500600
+#define S5PV310_PA_GIC_DIST            0x10501000
+#define S5PV310_PA_L2CC                        0x10502000
 
-#define S5P_PA_UART(x)                 (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_PA_UART0                   S5P_PA_UART(0)
-#define S5P_PA_UART1                   S5P_PA_UART(1)
-#define S5P_PA_UART2                   S5P_PA_UART(2)
-#define S5P_PA_UART3                   S5P_PA_UART(3)
-#define S5P_PA_UART4                   S5P_PA_UART(4)
-
-#define S5P_SZ_UART                    SZ_256
-
-#define S5PV310_PA_IIC(x)              (0x13860000 + ((x) * 0x10000))
-
-#define S5PV310_PA_TIMER               (0x139D0000)
-#define S5P_PA_TIMER                   S5PV310_PA_TIMER
-
-#define S5PV310_PA_SDRAM               (0x40000000)
-#define S5P_PA_SDRAM                   S5PV310_PA_SDRAM
+#define S5PV310_PA_MDMA                        0x10810000
+#define S5PV310_PA_PDMA0               0x12680000
+#define S5PV310_PA_PDMA1               0x12690000
 
 #define S5PV310_PA_SYSMMU_MDMA         0x10A40000
 #define S5PV310_PA_SYSMMU_SSS          0x10A50000
 #define S5PV310_PA_SYSMMU_MFC_L                0x13620000
 #define S5PV310_PA_SYSMMU_MFC_R                0x13630000
 
-/* compatibiltiy defines. */
-#define S3C_PA_UART                    S5PV310_PA_UART
+#define S5PV310_PA_GPIO1               0x11400000
+#define S5PV310_PA_GPIO2               0x11000000
+#define S5PV310_PA_GPIO3               0x03860000
+
+#define S5PV310_PA_MIPI_CSIS0          0x11880000
+#define S5PV310_PA_MIPI_CSIS1          0x11890000
+
+#define S5PV310_PA_HSMMC(x)            (0x12510000 + ((x) * 0x10000))
+
+#define S5PV310_PA_SROMC               0x12570000
+
+#define S5PV310_PA_UART                        0x13800000
+
+#define S5PV310_PA_IIC(x)              (0x13860000 + ((x) * 0x10000))
+
+#define S5PV310_PA_AC97                        0x139A0000
+
+#define S5PV310_PA_TIMER               0x139D0000
+
+#define S5PV310_PA_SDRAM               0x40000000
+
+#define S5PV310_PA_SPDIF               0xE1100000
+
+/* Compatibiltiy Defines */
+
 #define S3C_PA_HSMMC0                  S5PV310_PA_HSMMC(0)
 #define S3C_PA_HSMMC1                  S5PV310_PA_HSMMC(1)
 #define S3C_PA_HSMMC2                  S5PV310_PA_HSMMC(2)
 #define S3C_PA_IIC7                    S5PV310_PA_IIC(7)
 #define S3C_PA_RTC                     S5PV310_PA_RTC
 #define S3C_PA_WDT                     S5PV310_PA_WATCHDOG
+
+#define S5P_PA_CHIPID                  S5PV310_PA_CHIPID
 #define S5P_PA_MIPI_CSIS0              S5PV310_PA_MIPI_CSIS0
 #define S5P_PA_MIPI_CSIS1              S5PV310_PA_MIPI_CSIS1
+#define S5P_PA_ONENAND                 S5PC210_PA_ONENAND
+#define S5P_PA_ONENAND_DMA             S5PC210_PA_ONENAND_DMA
+#define S5P_PA_SDRAM                   S5PV310_PA_SDRAM
+#define S5P_PA_SROMC                   S5PV310_PA_SROMC
+#define S5P_PA_SYSCON                  S5PV310_PA_SYSCON
+#define S5P_PA_TIMER                   S5PV310_PA_TIMER
+
+/* UART */
+
+#define S3C_PA_UART                    S5PV310_PA_UART
+
+#define S5P_PA_UART(x)                 (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0                   S5P_PA_UART(0)
+#define S5P_PA_UART1                   S5P_PA_UART(1)
+#define S5P_PA_UART2                   S5P_PA_UART(2)
+#define S5P_PA_UART3                   S5P_PA_UART(3)
+#define S5P_PA_UART4                   S5P_PA_UART(4)
+
+#define S5P_SZ_UART                    SZ_256
 
 #endif /* __ASM_ARCH_MAP_H */
index cacf17a..53677e4 100644 (file)
@@ -62,7 +62,7 @@
 #define SPEAR320_SMII1_BASE            0xAB000000
 #define SPEAR320_SMII1_SIZE            0x01000000
 
-#define SPEAR320_SOC_CONFIG_BASE       0xB4000000
+#define SPEAR320_SOC_CONFIG_BASE       0xB3000000
 #define SPEAR320_SOC_CONFIG_SIZE       0x00000070
 /* Interrupt registers offsets and masks */
 #define INT_STS_MASK_REG               0x04
index 66ad276..04c7798 100644 (file)
@@ -57,5 +57,6 @@ struct tegra_kbc_platform_data {
        const struct matrix_keymap_data *keymap_data;
 
        bool wakeup;
+       bool use_fn_map;
 };
 #endif
index 170c9bb..f2ce38e 100644 (file)
@@ -49,7 +49,13 @@ static inline void cache_wait(void __iomem *reg, unsigned long mask)
 static inline void cache_sync(void)
 {
        void __iomem *base = l2x0_base;
+
+#ifdef CONFIG_ARM_ERRATA_753970
+       /* write to an unmmapped register */
+       writel_relaxed(0, base + L2X0_DUMMY_REG);
+#else
        writel_relaxed(0, base + L2X0_CACHE_SYNC);
+#endif
        cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
 
index 0c1172b..8e33562 100644 (file)
@@ -264,6 +264,12 @@ __v7_setup:
        orreq   r10, r10, #1 << 6               @ set bit #6
        mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_751472
+       cmp     r6, #0x30                       @ present prior to r3p0
+       mrclt   p15, 0, r10, c15, c0, 1         @ read diagnostic register
+       orrlt   r10, r10, #1 << 11              @ set bit #11
+       mcrlt   p15, 0, r10, c15, c0, 1         @ write diagnostic register
+#endif
 
 3:     mov     r10, #0
 #ifdef HARVARD_CACHE
index 459b319..49d3208 100644 (file)
@@ -322,15 +322,18 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
 
 struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
 {
-       struct omap_mbox *mbox;
-       int ret;
+       struct omap_mbox *_mbox, *mbox = NULL;
+       int i, ret;
 
        if (!mboxes)
                return ERR_PTR(-EINVAL);
 
-       for (mbox = *mboxes; mbox; mbox++)
-               if (!strcmp(mbox->name, name))
+       for (i = 0; (_mbox = mboxes[i]); i++) {
+               if (!strcmp(_mbox->name, name)) {
+                       mbox = _mbox;
                        break;
+               }
+       }
 
        if (!mbox)
                return ERR_PTR(-ENOENT);
index 6a73428..afaf87f 100644 (file)
@@ -28,7 +28,7 @@
 static struct resource s5p_uart0_resource[] = {
        [0] = {
                .start  = S5P_PA_UART0,
-               .end    = S5P_PA_UART0 + S5P_SZ_UART,
+               .end    = S5P_PA_UART0 + S5P_SZ_UART - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -51,7 +51,7 @@ static struct resource s5p_uart0_resource[] = {
 static struct resource s5p_uart1_resource[] = {
        [0] = {
                .start  = S5P_PA_UART1,
-               .end    = S5P_PA_UART1 + S5P_SZ_UART,
+               .end    = S5P_PA_UART1 + S5P_SZ_UART - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -74,7 +74,7 @@ static struct resource s5p_uart1_resource[] = {
 static struct resource s5p_uart2_resource[] = {
        [0] = {
                .start  = S5P_PA_UART2,
-               .end    = S5P_PA_UART2 + S5P_SZ_UART,
+               .end    = S5P_PA_UART2 + S5P_SZ_UART - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -98,7 +98,7 @@ static struct resource s5p_uart3_resource[] = {
 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
        [0] = {
                .start  = S5P_PA_UART3,
-               .end    = S5P_PA_UART3 + S5P_SZ_UART,
+               .end    = S5P_PA_UART3 + S5P_SZ_UART - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -123,7 +123,7 @@ static struct resource s5p_uart4_resource[] = {
 #if CONFIG_SERIAL_SAMSUNG_UARTS > 4
        [0] = {
                .start  = S5P_PA_UART4,
-               .end    = S5P_PA_UART4 + S5P_SZ_UART,
+               .end    = S5P_PA_UART4 + S5P_SZ_UART - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -148,7 +148,7 @@ static struct resource s5p_uart5_resource[] = {
 #if CONFIG_SERIAL_SAMSUNG_UARTS > 5
        [0] = {
                .start  = S5P_PA_UART5,
-               .end    = S5P_PA_UART5 + S5P_SZ_UART,
+               .end    = S5P_PA_UART5 + S5P_SZ_UART - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
index 236ef84..3e4bd81 100644 (file)
@@ -58,4 +58,3 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
 
        s3c_device_ts.dev.platform_data = npd;
 }
-EXPORT_SYMBOL(s3c24xx_ts_set_platdata);
index 99ba678..6dd455b 100644 (file)
@@ -24,10 +24,10 @@ static inline void putc(int c)
 {
        void __iomem *base = (void __iomem *)SPEAR_DBG_UART_BASE;
 
-       while (readl(base + UART01x_FR) & UART01x_FR_TXFF)
+       while (readl_relaxed(base + UART01x_FR) & UART01x_FR_TXFF)
                barrier();
 
-       writel(c, base + UART01x_DR);
+       writel_relaxed(c, base + UART01x_DR);
 }
 
 static inline void flush(void)
index 09e9372..8c8b24d 100644 (file)
@@ -14,6 +14,6 @@
 #ifndef __PLAT_VMALLOC_H
 #define __PLAT_VMALLOC_H
 
-#define VMALLOC_END            0xF0000000
+#define VMALLOC_END            0xF0000000UL
 
 #endif /* __PLAT_VMALLOC_H */
index 4422189..c49be84 100644 (file)
@@ -72,11 +72,6 @@ SECTIONS
        INIT_TEXT_SECTION(PAGE_SIZE)
        .init.data : { INIT_DATA }
        .init.setup : { INIT_SETUP(16) }
-#ifdef CONFIG_ETRAX_ARCH_V32
-       __start___param = .;
-       __param : { *(__param) }
-       __stop___param = .;
-#endif
        .initcall.init : {
                INIT_CALLS
        }
index 991d599..fe56a23 100644 (file)
@@ -240,6 +240,12 @@ struct machdep_calls {
         * claims to support kexec.
         */
        int (*machine_kexec_prepare)(struct kimage *image);
+
+       /* Called to perform the _real_ kexec.
+        * Do NOT allocate memory or fail here. We are past the point of
+        * no return.
+        */
+       void (*machine_kexec)(struct kimage *image);
 #endif /* CONFIG_KEXEC */
 
 #ifdef CONFIG_SUSPEND
index 49a170a..a5f8672 100644 (file)
@@ -87,7 +87,10 @@ void machine_kexec(struct kimage *image)
 
        save_ftrace_enabled = __ftrace_enabled_save();
 
-       default_machine_kexec(image);
+       if (ppc_md.machine_kexec)
+               ppc_md.machine_kexec(image);
+       else
+               default_machine_kexec(image);
 
        __ftrace_enabled_restore(save_ftrace_enabled);
 
index 7a1d5cb..8303a6c 100644 (file)
@@ -353,6 +353,7 @@ static void switch_booke_debug_regs(struct thread_struct *new_thread)
                        prime_debug_regs(new_thread);
 }
 #else  /* !CONFIG_PPC_ADV_DEBUG_REGS */
+#ifndef CONFIG_HAVE_HW_BREAKPOINT
 static void set_debug_reg_defaults(struct thread_struct *thread)
 {
        if (thread->dabr) {
@@ -360,6 +361,7 @@ static void set_debug_reg_defaults(struct thread_struct *thread)
                set_dabr(0);
        }
 }
+#endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
 
 int set_dabr(unsigned long dabr)
@@ -670,11 +672,11 @@ void flush_thread(void)
 {
        discard_lazy_cpu_state();
 
-#ifdef CONFIG_HAVE_HW_BREAKPOINTS
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
        flush_ptrace_hw_breakpoint(current);
-#else /* CONFIG_HAVE_HW_BREAKPOINTS */
+#else /* CONFIG_HAVE_HW_BREAKPOINT */
        set_debug_reg_defaults(&current->thread);
-#endif /* CONFIG_HAVE_HW_BREAKPOINTS */
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
 }
 
 void
index 1ec0657..c14d09f 100644 (file)
@@ -38,13 +38,11 @@ DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
  * neesd to be flushed. This function will either perform the flush
  * immediately or will batch it up if the current CPU has an active
  * batch on it.
- *
- * Must be called from within some kind of spinlock/non-preempt region...
  */
 void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
                     pte_t *ptep, unsigned long pte, int huge)
 {
-       struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
+       struct ppc64_tlb_batch *batch = &get_cpu_var(ppc64_tlb_batch);
        unsigned long vsid, vaddr;
        unsigned int psize;
        int ssize;
@@ -99,6 +97,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
         */
        if (!batch->active) {
                flush_hash_page(vaddr, rpte, psize, ssize, 0);
+               put_cpu_var(ppc64_tlb_batch);
                return;
        }
 
@@ -127,6 +126,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
        batch->index = ++i;
        if (i >= PPC64_TLB_BATCH_NR)
                __flush_tlb_pending(batch);
+       put_cpu_var(ppc64_tlb_batch);
 }
 
 /*
index 0851eb1..2751b3a 100644 (file)
@@ -133,11 +133,12 @@ unsigned long decompress_kernel(void)
        unsigned long output_addr;
        unsigned char *output;
 
-       check_ipl_parmblock((void *) 0, (unsigned long) output + SZ__bss_start);
+       output_addr = ((unsigned long) &_end + HEAP_SIZE + 4095UL) & -4096UL;
+       check_ipl_parmblock((void *) 0, output_addr + SZ__bss_start);
        memset(&_bss, 0, &_ebss - &_bss);
        free_mem_ptr = (unsigned long)&_end;
        free_mem_end_ptr = free_mem_ptr + HEAP_SIZE;
-       output = (unsigned char *) ((free_mem_end_ptr + 4095UL) & -4096UL);
+       output = (unsigned char *) output_addr;
 
 #ifdef CONFIG_BLK_DEV_INITRD
        /*
index 76daea1..5c5ba10 100644 (file)
 
 static inline int atomic_read(const atomic_t *v)
 {
-       barrier();
-       return v->counter;
+       int c;
+
+       asm volatile(
+               "       l       %0,%1\n"
+               : "=d" (c) : "Q" (v->counter));
+       return c;
 }
 
 static inline void atomic_set(atomic_t *v, int i)
 {
-       v->counter = i;
-       barrier();
+       asm volatile(
+               "       st      %1,%0\n"
+               : "=Q" (v->counter) : "d" (i));
 }
 
 static inline int atomic_add_return(int i, atomic_t *v)
@@ -128,14 +133,19 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
 
 static inline long long atomic64_read(const atomic64_t *v)
 {
-       barrier();
-       return v->counter;
+       long long c;
+
+       asm volatile(
+               "       lg      %0,%1\n"
+               : "=d" (c) : "Q" (v->counter));
+       return c;
 }
 
 static inline void atomic64_set(atomic64_t *v, long long i)
 {
-       v->counter = i;
-       barrier();
+       asm volatile(
+               "       stg     %1,%0\n"
+               : "=Q" (v->counter) : "d" (i));
 }
 
 static inline long long atomic64_add_return(long long i, atomic64_t *v)
index 24aafa6..2a30d5a 100644 (file)
@@ -13,6 +13,7 @@
 
 #define L1_CACHE_BYTES     256
 #define L1_CACHE_SHIFT     8
+#define NET_SKB_PAD       32
 
 #define __read_mostly __attribute__((__section__(".data..read_mostly")))
 
index 211ca3f..4ea15ca 100644 (file)
@@ -88,6 +88,7 @@ extern int acpi_disabled;
 extern int acpi_pci_disabled;
 extern int acpi_skip_timer_override;
 extern int acpi_use_timer_override;
+extern int acpi_fix_pin2_polarity;
 
 extern u8 acpi_sci_flags;
 extern int acpi_sci_override_gsi;
index 4d0dfa0..43a18c7 100644 (file)
 #define MSR_IA32_PERFCTR1              0x000000c2
 #define MSR_FSB_FREQ                   0x000000cd
 
+#define MSR_NHM_SNB_PKG_CST_CFG_CTL    0x000000e2
+#define NHM_C3_AUTO_DEMOTE             (1UL << 25)
+#define NHM_C1_AUTO_DEMOTE             (1UL << 26)
+#define ATM_LNC_C6_AUTO_DEMOTE         (1UL << 25)
+
 #define MSR_MTRRcap                    0x000000fe
 #define MSR_IA32_BBL_CR_CTL            0x00000119
 
index e2f6a99..cc29086 100644 (file)
@@ -22,6 +22,7 @@
 
 #define ARCH_P4_CNTRVAL_BITS   (40)
 #define ARCH_P4_CNTRVAL_MASK   ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
+#define ARCH_P4_UNFLAGGED_BIT  ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
 
 #define P4_ESCR_EVENT_MASK     0x7e000000U
 #define P4_ESCR_EVENT_SHIFT    25
index 6c22bf3..725b778 100644 (file)
@@ -34,7 +34,7 @@ static inline void smpboot_restore_warm_reset_vector(void)
         */
        CMOS_WRITE(0, 0xf);
 
-       *((volatile long *)phys_to_virt(apic->trampoline_phys_low)) = 0;
+       *((volatile u32 *)phys_to_virt(apic->trampoline_phys_low)) = 0;
 }
 
 static inline void __init smpboot_setup_io_apic(void)
index b3a7113..3e6e2d6 100644 (file)
@@ -72,6 +72,7 @@ u8 acpi_sci_flags __initdata;
 int acpi_sci_override_gsi __initdata;
 int acpi_skip_timer_override __initdata;
 int acpi_use_timer_override __initdata;
+int acpi_fix_pin2_polarity __initdata;
 
 #ifdef CONFIG_X86_LOCAL_APIC
 static u64 acpi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE;
@@ -415,10 +416,15 @@ acpi_parse_int_src_ovr(struct acpi_subtable_header * header,
                return 0;
        }
 
-       if (acpi_skip_timer_override &&
-           intsrc->source_irq == 0 && intsrc->global_irq == 2) {
-               printk(PREFIX "BIOS IRQ0 pin2 override ignored.\n");
-               return 0;
+       if (intsrc->source_irq == 0 && intsrc->global_irq == 2) {
+               if (acpi_skip_timer_override) {
+                       printk(PREFIX "BIOS IRQ0 pin2 override ignored.\n");
+                       return 0;
+               }
+               if (acpi_fix_pin2_polarity && (intsrc->inti_flags & ACPI_MADT_POLARITY_MASK)) {
+                       intsrc->inti_flags &= ~ACPI_MADT_POLARITY_MASK;
+                       printk(PREFIX "BIOS IRQ0 pin2 override: forcing polarity to high active.\n");
+               }
        }
 
        mp_override_legacy_irq(intsrc->source_irq,
index 51ef31a..51d4e16 100644 (file)
@@ -284,7 +284,7 @@ static int __init apbt_clockevent_register(void)
        memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device));
 
        if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
-               apbt_clockevent.rating = APBT_CLOCKEVENT_RATING - 100;
+               adev->evt.rating = APBT_CLOCKEVENT_RATING - 100;
                global_clock_event = &adev->evt;
                printk(KERN_DEBUG "%s clockevent registered as global\n",
                       global_clock_event->name);
index bd1cac7..52c9364 100644 (file)
@@ -158,9 +158,9 @@ static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
 {
        if (c->x86 == 0x06) {
                if (cpu_has(c, X86_FEATURE_EST))
-                       printk(KERN_WARNING PFX "Warning: EST-capable CPU "
-                              "detected. The acpi-cpufreq module offers "
-                              "voltage scaling in addition of frequency "
+                       printk_once(KERN_WARNING PFX "Warning: EST-capable "
+                              "CPU detected. The acpi-cpufreq module offers "
+                              "voltage scaling in addition to frequency "
                               "scaling. You should use that instead of "
                               "p4-clockmod, if possible.\n");
                switch (c->x86_model) {
index 35c7e65..c567dec 100644 (file)
@@ -1537,6 +1537,7 @@ static struct notifier_block cpb_nb = {
 static int __cpuinit powernowk8_init(void)
 {
        unsigned int i, supported_cpus = 0, cpu;
+       int rv;
 
        for_each_online_cpu(i) {
                int rc;
@@ -1555,14 +1556,14 @@ static int __cpuinit powernowk8_init(void)
 
                cpb_capable = true;
 
-               register_cpu_notifier(&cpb_nb);
-
                msrs = msrs_alloc();
                if (!msrs) {
                        printk(KERN_ERR "%s: Error allocating msrs!\n", __func__);
                        return -ENOMEM;
                }
 
+               register_cpu_notifier(&cpb_nb);
+
                rdmsr_on_cpus(cpu_online_mask, MSR_K7_HWCR, msrs);
 
                for_each_cpu(cpu, cpu_online_mask) {
@@ -1574,7 +1575,13 @@ static int __cpuinit powernowk8_init(void)
                        (cpb_enabled ? "on" : "off"));
        }
 
-       return cpufreq_register_driver(&cpufreq_amd64_driver);
+       rv = cpufreq_register_driver(&cpufreq_amd64_driver);
+       if (rv < 0 && boot_cpu_has(X86_FEATURE_CPB)) {
+               unregister_cpu_notifier(&cpb_nb);
+               msrs_free(msrs);
+               msrs = NULL;
+       }
+       return rv;
 }
 
 /* driver entry point for term */
index f7a0993..ff751a9 100644 (file)
@@ -770,9 +770,14 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
                return 1;
        }
 
-       /* it might be unflagged overflow */
-       rdmsrl(hwc->event_base + hwc->idx, v);
-       if (!(v & ARCH_P4_CNTRVAL_MASK))
+       /*
+        * In some circumstances the overflow might issue an NMI but did
+        * not set P4_CCCR_OVF bit. Because a counter holds a negative value
+        * we simply check for high bit being set, if it's cleared it means
+        * the counter has reached zero value and continued counting before
+        * real NMI signal was received:
+        */
+       if (!(v & ARCH_P4_UNFLAGGED_BIT))
                return 1;
 
        return 0;
index 76b8cd9..9efbdcc 100644 (file)
@@ -143,15 +143,10 @@ static void __init ati_bugs(int num, int slot, int func)
 
 static u32 __init ati_sbx00_rev(int num, int slot, int func)
 {
-       u32 old, d;
+       u32 d;
 
-       d = read_pci_config(num, slot, func, 0x70);
-       old = d;
-       d &= ~(1<<8);
-       write_pci_config(num, slot, func, 0x70, d);
        d = read_pci_config(num, slot, func, 0x8);
        d &= 0xff;
-       write_pci_config(num, slot, func, 0x70, old);
 
        return d;
 }
@@ -160,13 +155,16 @@ static void __init ati_bugs_contd(int num, int slot, int func)
 {
        u32 d, rev;
 
-       if (acpi_use_timer_override)
-               return;
-
        rev = ati_sbx00_rev(num, slot, func);
+       if (rev >= 0x40)
+               acpi_fix_pin2_polarity = 1;
+
        if (rev > 0x13)
                return;
 
+       if (acpi_use_timer_override)
+               return;
+
        /* check for IRQ0 interrupt swap */
        d = read_pci_config(num, slot, func, 0x64);
        if (!(d & (1<<14)))
index fc7aae1..715037c 100644 (file)
@@ -285,6 +285,14 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = {
                        DMI_MATCH(DMI_BOARD_NAME, "P4S800"),
                },
        },
+       {       /* Handle problems with rebooting on VersaLogic Menlow boards */
+               .callback = set_bios_reboot,
+               .ident = "VersaLogic Menlow based board",
+               .matches = {
+                       DMI_MATCH(DMI_BOARD_VENDOR, "VersaLogic Corporation"),
+                       DMI_MATCH(DMI_BOARD_NAME, "VersaLogic Menlow board"),
+               },
+       },
        { }
 };
 
index 54ce246..63fec15 100644 (file)
@@ -2777,6 +2777,8 @@ static int dr_interception(struct vcpu_svm *svm)
                        kvm_register_write(&svm->vcpu, reg, val);
        }
 
+       skip_emulated_instruction(&svm->vcpu);
+
        return 1;
 }
 
index dab8746..044bda5 100644 (file)
@@ -140,8 +140,7 @@ void * __init prom_early_alloc(unsigned long size)
                 * wasted bootmem) and hand off chunks of it to callers.
                 */
                res = alloc_bootmem(chunk_size);
-               if (!res)
-                       return NULL;
+               BUG_ON(!res);
                prom_early_allocated += chunk_size;
                memset(res, 0, chunk_size);
                free_mem = chunk_size;
index 2f4002f..518dd42 100644 (file)
@@ -352,7 +352,7 @@ void blk_start_queue(struct request_queue *q)
        WARN_ON(!irqs_disabled());
 
        queue_flag_clear(QUEUE_FLAG_STOPPED, q);
-       __blk_run_queue(q);
+       __blk_run_queue(q, false);
 }
 EXPORT_SYMBOL(blk_start_queue);
 
@@ -403,13 +403,14 @@ EXPORT_SYMBOL(blk_sync_queue);
 /**
  * __blk_run_queue - run a single device queue
  * @q: The queue to run
+ * @force_kblockd: Don't run @q->request_fn directly.  Use kblockd.
  *
  * Description:
  *    See @blk_run_queue. This variant must be called with the queue lock
  *    held and interrupts disabled.
  *
  */
-void __blk_run_queue(struct request_queue *q)
+void __blk_run_queue(struct request_queue *q, bool force_kblockd)
 {
        blk_remove_plug(q);
 
@@ -423,7 +424,7 @@ void __blk_run_queue(struct request_queue *q)
         * Only recurse once to avoid overrunning the stack, let the unplug
         * handling reinvoke the handler shortly if we already got there.
         */
-       if (!queue_flag_test_and_set(QUEUE_FLAG_REENTER, q)) {
+       if (!force_kblockd && !queue_flag_test_and_set(QUEUE_FLAG_REENTER, q)) {
                q->request_fn(q);
                queue_flag_clear(QUEUE_FLAG_REENTER, q);
        } else {
@@ -446,7 +447,7 @@ void blk_run_queue(struct request_queue *q)
        unsigned long flags;
 
        spin_lock_irqsave(q->queue_lock, flags);
-       __blk_run_queue(q);
+       __blk_run_queue(q, false);
        spin_unlock_irqrestore(q->queue_lock, flags);
 }
 EXPORT_SYMBOL(blk_run_queue);
@@ -1053,7 +1054,7 @@ void blk_insert_request(struct request_queue *q, struct request *rq,
 
        drive_stat_acct(rq, 1);
        __elv_add_request(q, rq, where, 0);
-       __blk_run_queue(q);
+       __blk_run_queue(q, false);
        spin_unlock_irqrestore(q->queue_lock, flags);
 }
 EXPORT_SYMBOL(blk_insert_request);
@@ -2610,13 +2611,6 @@ int kblockd_schedule_work(struct request_queue *q, struct work_struct *work)
 }
 EXPORT_SYMBOL(kblockd_schedule_work);
 
-int kblockd_schedule_delayed_work(struct request_queue *q,
-                       struct delayed_work *dwork, unsigned long delay)
-{
-       return queue_delayed_work(kblockd_workqueue, dwork, delay);
-}
-EXPORT_SYMBOL(kblockd_schedule_delayed_work);
-
 int __init blk_dev_init(void)
 {
        BUILD_BUG_ON(__REQ_NR_BITS > 8 *
index 54b123d..b27d020 100644 (file)
@@ -66,10 +66,12 @@ static void blk_flush_complete_seq_end_io(struct request_queue *q,
 
        /*
         * Moving a request silently to empty queue_head may stall the
-        * queue.  Kick the queue in those cases.
+        * queue.  Kick the queue in those cases.  This function is called
+        * from request completion path and calling directly into
+        * request_fn may confuse the driver.  Always use kblockd.
         */
        if (was_empty && next_rq)
-               __blk_run_queue(q);
+               __blk_run_queue(q, true);
 }
 
 static void pre_flush_end_io(struct request *rq, int error)
@@ -130,7 +132,7 @@ static struct request *queue_next_fseq(struct request_queue *q)
                BUG();
        }
 
-       elv_insert(q, rq, ELEVATOR_INSERT_FRONT);
+       elv_insert(q, rq, ELEVATOR_INSERT_REQUEUE);
        return rq;
 }
 
index 1a320d2..eec78be 100644 (file)
@@ -132,7 +132,7 @@ static void bio_batch_end_io(struct bio *bio, int err)
 }
 
 /**
- * blkdev_issue_zeroout generate number of zero filed write bios
+ * blkdev_issue_zeroout - generate number of zero filed write bios
  * @bdev:      blockdev to issue
  * @sector:    start sector
  * @nr_sects:  number of sectors to write
index a89043a..e36cc10 100644 (file)
@@ -20,6 +20,11 @@ static int throtl_quantum = 32;
 /* Throttling is performed over 100ms slice and after that slice is renewed */
 static unsigned long throtl_slice = HZ/10;     /* 100 ms */
 
+/* A workqueue to queue throttle related work */
+static struct workqueue_struct *kthrotld_workqueue;
+static void throtl_schedule_delayed_work(struct throtl_data *td,
+                               unsigned long delay);
+
 struct throtl_rb_root {
        struct rb_root rb;
        struct rb_node *left;
@@ -345,10 +350,9 @@ static void throtl_schedule_next_dispatch(struct throtl_data *td)
        update_min_dispatch_time(st);
 
        if (time_before_eq(st->min_disptime, jiffies))
-               throtl_schedule_delayed_work(td->queue, 0);
+               throtl_schedule_delayed_work(td, 0);
        else
-               throtl_schedule_delayed_work(td->queue,
-                               (st->min_disptime - jiffies));
+               throtl_schedule_delayed_work(td, (st->min_disptime - jiffies));
 }
 
 static inline void
@@ -815,10 +819,10 @@ void blk_throtl_work(struct work_struct *work)
 }
 
 /* Call with queue lock held */
-void throtl_schedule_delayed_work(struct request_queue *q, unsigned long delay)
+static void
+throtl_schedule_delayed_work(struct throtl_data *td, unsigned long delay)
 {
 
-       struct throtl_data *td = q->td;
        struct delayed_work *dwork = &td->throtl_work;
 
        if (total_nr_queued(td) > 0) {
@@ -827,12 +831,11 @@ void throtl_schedule_delayed_work(struct request_queue *q, unsigned long delay)
                 * Cancel that and schedule a new one.
                 */
                __cancel_delayed_work(dwork);
-               kblockd_schedule_delayed_work(q, dwork, delay);
+               queue_delayed_work(kthrotld_workqueue, dwork, delay);
                throtl_log(td, "schedule work. delay=%lu jiffies=%lu",
                                delay, jiffies);
        }
 }
-EXPORT_SYMBOL(throtl_schedule_delayed_work);
 
 static void
 throtl_destroy_tg(struct throtl_data *td, struct throtl_grp *tg)
@@ -920,7 +923,7 @@ static void throtl_update_blkio_group_read_bps(void *key,
        smp_mb__after_atomic_inc();
 
        /* Schedule a work now to process the limit change */
-       throtl_schedule_delayed_work(td->queue, 0);
+       throtl_schedule_delayed_work(td, 0);
 }
 
 static void throtl_update_blkio_group_write_bps(void *key,
@@ -934,7 +937,7 @@ static void throtl_update_blkio_group_write_bps(void *key,
        smp_mb__before_atomic_inc();
        atomic_inc(&td->limits_changed);
        smp_mb__after_atomic_inc();
-       throtl_schedule_delayed_work(td->queue, 0);
+       throtl_schedule_delayed_work(td, 0);
 }
 
 static void throtl_update_blkio_group_read_iops(void *key,
@@ -948,7 +951,7 @@ static void throtl_update_blkio_group_read_iops(void *key,
        smp_mb__before_atomic_inc();
        atomic_inc(&td->limits_changed);
        smp_mb__after_atomic_inc();
-       throtl_schedule_delayed_work(td->queue, 0);
+       throtl_schedule_delayed_work(td, 0);
 }
 
 static void throtl_update_blkio_group_write_iops(void *key,
@@ -962,7 +965,7 @@ static void throtl_update_blkio_group_write_iops(void *key,
        smp_mb__before_atomic_inc();
        atomic_inc(&td->limits_changed);
        smp_mb__after_atomic_inc();
-       throtl_schedule_delayed_work(td->queue, 0);
+       throtl_schedule_delayed_work(td, 0);
 }
 
 void throtl_shutdown_timer_wq(struct request_queue *q)
@@ -1135,6 +1138,10 @@ void blk_throtl_exit(struct request_queue *q)
 
 static int __init throtl_init(void)
 {
+       kthrotld_workqueue = alloc_workqueue("kthrotld", WQ_MEM_RECLAIM, 0);
+       if (!kthrotld_workqueue)
+               panic("Failed to create kthrotld\n");
+
        blkio_policy_register(&blkio_policy_throtl);
        return 0;
 }
index 7be4c79..ea83a4f 100644 (file)
@@ -3355,7 +3355,7 @@ cfq_rq_enqueued(struct cfq_data *cfqd, struct cfq_queue *cfqq,
                            cfqd->busy_queues > 1) {
                                cfq_del_timer(cfqd, cfqq);
                                cfq_clear_cfqq_wait_request(cfqq);
-                               __blk_run_queue(cfqd->queue);
+                               __blk_run_queue(cfqd->queue, false);
                        } else {
                                cfq_blkiocg_update_idle_time_stats(
                                                &cfqq->cfqg->blkg);
@@ -3370,7 +3370,7 @@ cfq_rq_enqueued(struct cfq_data *cfqd, struct cfq_queue *cfqq,
                 * this new queue is RT and the current one is BE
                 */
                cfq_preempt_queue(cfqd, cfqq);
-               __blk_run_queue(cfqd->queue);
+               __blk_run_queue(cfqd->queue, false);
        }
 }
 
@@ -3731,7 +3731,7 @@ static void cfq_kick_queue(struct work_struct *work)
        struct request_queue *q = cfqd->queue;
 
        spin_lock_irq(q->queue_lock);
-       __blk_run_queue(cfqd->queue);
+       __blk_run_queue(cfqd->queue, false);
        spin_unlock_irq(q->queue_lock);
 }
 
index 2569512..236e93c 100644 (file)
@@ -602,7 +602,7 @@ void elv_quiesce_start(struct request_queue *q)
         */
        elv_drain_elevator(q);
        while (q->rq.elvpriv) {
-               __blk_run_queue(q);
+               __blk_run_queue(q, false);
                spin_unlock_irq(q->queue_lock);
                msleep(10);
                spin_lock_irq(q->queue_lock);
@@ -651,7 +651,7 @@ void elv_insert(struct request_queue *q, struct request *rq, int where)
                 *   with anything.  There's no point in delaying queue
                 *   processing.
                 */
-               __blk_run_queue(q);
+               __blk_run_queue(q, false);
                break;
 
        case ELEVATOR_INSERT_SORT:
index 6a5b772..cbf1112 100644 (file)
@@ -1355,7 +1355,7 @@ int invalidate_partition(struct gendisk *disk, int partno)
        struct block_device *bdev = bdget_disk(disk, partno);
        if (bdev) {
                fsync_bdev(bdev);
-               res = __invalidate_device(bdev);
+               res = __invalidate_device(bdev, true);
                bdput(bdev);
        }
        return res;
index 9049d46..1124cd2 100644 (file)
@@ -294,9 +294,11 @@ int blkdev_ioctl(struct block_device *bdev, fmode_t mode, unsigned cmd,
                        return -EINVAL;
                if (get_user(n, (int __user *) arg))
                        return -EFAULT;
-               if (!(mode & FMODE_EXCL) &&
-                   blkdev_get(bdev, mode | FMODE_EXCL, &bdev) < 0)
-                       return -EBUSY;
+               if (!(mode & FMODE_EXCL)) {
+                       bdgrab(bdev);
+                       if (blkdev_get(bdev, mode | FMODE_EXCL, &bdev) < 0)
+                               return -EBUSY;
+               }
                ret = set_blocksize(bdev, n);
                if (!(mode & FMODE_EXCL))
                        blkdev_put(bdev, mode | FMODE_EXCL);
index 54784bb..edc2586 100644 (file)
@@ -416,10 +416,15 @@ struct acpi_gpe_handler_info {
        u8 originally_enabled;  /* True if GPE was originally enabled */
 };
 
+struct acpi_gpe_notify_object {
+       struct acpi_namespace_node *node;
+       struct acpi_gpe_notify_object *next;
+};
+
 union acpi_gpe_dispatch_info {
        struct acpi_namespace_node *method_node;        /* Method node for this GPE level */
        struct acpi_gpe_handler_info *handler;  /* Installed GPE handler */
-       struct acpi_namespace_node *device_node;        /* Parent _PRW device for implicit notify */
+       struct acpi_gpe_notify_object device;   /* List of _PRW devices for implicit notify */
 };
 
 /*
index 14988a8..f472521 100644 (file)
@@ -457,6 +457,7 @@ static void ACPI_SYSTEM_XFACE acpi_ev_asynch_execute_gpe_method(void *context)
        acpi_status status;
        struct acpi_gpe_event_info *local_gpe_event_info;
        struct acpi_evaluate_info *info;
+       struct acpi_gpe_notify_object *notify_object;
 
        ACPI_FUNCTION_TRACE(ev_asynch_execute_gpe_method);
 
@@ -508,10 +509,18 @@ static void ACPI_SYSTEM_XFACE acpi_ev_asynch_execute_gpe_method(void *context)
                 * from this thread -- because handlers may in turn run other
                 * control methods.
                 */
-               status =
-                   acpi_ev_queue_notify_request(local_gpe_event_info->dispatch.
-                                                device_node,
-                                                ACPI_NOTIFY_DEVICE_WAKE);
+               status = acpi_ev_queue_notify_request(
+                               local_gpe_event_info->dispatch.device.node,
+                               ACPI_NOTIFY_DEVICE_WAKE);
+
+               notify_object = local_gpe_event_info->dispatch.device.next;
+               while (ACPI_SUCCESS(status) && notify_object) {
+                       status = acpi_ev_queue_notify_request(
+                                       notify_object->node,
+                                       ACPI_NOTIFY_DEVICE_WAKE);
+                       notify_object = notify_object->next;
+               }
+
                break;
 
        case ACPI_GPE_DISPATCH_METHOD:
index 3b20a34..52aaff3 100644 (file)
@@ -198,7 +198,9 @@ acpi_setup_gpe_for_wake(acpi_handle wake_device,
        acpi_status status = AE_BAD_PARAMETER;
        struct acpi_gpe_event_info *gpe_event_info;
        struct acpi_namespace_node *device_node;
+       struct acpi_gpe_notify_object *notify_object;
        acpi_cpu_flags flags;
+       u8 gpe_dispatch_mask;
 
        ACPI_FUNCTION_TRACE(acpi_setup_gpe_for_wake);
 
@@ -221,27 +223,49 @@ acpi_setup_gpe_for_wake(acpi_handle wake_device,
                goto unlock_and_exit;
        }
 
+       if (wake_device == ACPI_ROOT_OBJECT) {
+               goto out;
+       }
+
        /*
         * If there is no method or handler for this GPE, then the
         * wake_device will be notified whenever this GPE fires (aka
         * "implicit notify") Note: The GPE is assumed to be
         * level-triggered (for windows compatibility).
         */
-       if (((gpe_event_info->flags & ACPI_GPE_DISPATCH_MASK) ==
-             ACPI_GPE_DISPATCH_NONE) && (wake_device != ACPI_ROOT_OBJECT)) {
+       gpe_dispatch_mask = gpe_event_info->flags & ACPI_GPE_DISPATCH_MASK;
+       if (gpe_dispatch_mask != ACPI_GPE_DISPATCH_NONE
+           && gpe_dispatch_mask != ACPI_GPE_DISPATCH_NOTIFY) {
+               goto out;
+       }
 
-               /* Validate wake_device is of type Device */
+       /* Validate wake_device is of type Device */
 
-               device_node = ACPI_CAST_PTR(struct acpi_namespace_node,
-                                           wake_device);
-               if (device_node->type != ACPI_TYPE_DEVICE) {
-                       goto unlock_and_exit;
-               }
+       device_node = ACPI_CAST_PTR(struct acpi_namespace_node, wake_device);
+       if (device_node->type != ACPI_TYPE_DEVICE) {
+               goto unlock_and_exit;
+       }
+
+       if (gpe_dispatch_mask == ACPI_GPE_DISPATCH_NONE) {
                gpe_event_info->flags = (ACPI_GPE_DISPATCH_NOTIFY |
                                         ACPI_GPE_LEVEL_TRIGGERED);
-               gpe_event_info->dispatch.device_node = device_node;
+               gpe_event_info->dispatch.device.node = device_node;
+               gpe_event_info->dispatch.device.next = NULL;
+       } else {
+               /* There are multiple devices to notify implicitly. */
+
+               notify_object = ACPI_ALLOCATE_ZEROED(sizeof(*notify_object));
+               if (!notify_object) {
+                       status = AE_NO_MEMORY;
+                       goto unlock_and_exit;
+               }
+
+               notify_object->node = device_node;
+               notify_object->next = gpe_event_info->dispatch.device.next;
+               gpe_event_info->dispatch.device.next = notify_object;
        }
 
+ out:
        gpe_event_info->flags |= ACPI_GPE_CAN_WAKE;
        status = AE_OK;
 
index 5df67f1..384f7ab 100644 (file)
@@ -26,7 +26,9 @@ static ssize_t cm_write(struct file *file, const char __user * user_buf,
                        size_t count, loff_t *ppos)
 {
        static char *buf;
-       static int uncopied_bytes;
+       static u32 max_size;
+       static u32 uncopied_bytes;
+
        struct acpi_table_header table;
        acpi_status status;
 
@@ -37,19 +39,24 @@ static ssize_t cm_write(struct file *file, const char __user * user_buf,
                if (copy_from_user(&table, user_buf,
                                   sizeof(struct acpi_table_header)))
                        return -EFAULT;
-               uncopied_bytes = table.length;
-               buf = kzalloc(uncopied_bytes, GFP_KERNEL);
+               uncopied_bytes = max_size = table.length;
+               buf = kzalloc(max_size, GFP_KERNEL);
                if (!buf)
                        return -ENOMEM;
        }
 
-       if (uncopied_bytes < count) {
-               kfree(buf);
+       if (buf == NULL)
+               return -EINVAL;
+
+       if ((*ppos > max_size) ||
+           (*ppos + count > max_size) ||
+           (*ppos + count < count) ||
+           (count > uncopied_bytes))
                return -EINVAL;
-       }
 
        if (copy_from_user(buf + (*ppos), user_buf, count)) {
                kfree(buf);
+               buf = NULL;
                return -EFAULT;
        }
 
@@ -59,6 +66,7 @@ static ssize_t cm_write(struct file *file, const char __user * user_buf,
        if (!uncopied_bytes) {
                status = acpi_install_method(buf);
                kfree(buf);
+               buf = NULL;
                if (ACPI_FAILURE(status))
                        return -EINVAL;
                add_taint(TAINT_OVERRIDDEN_ACPI_TABLE);
index 8cbfaa6..fe81c85 100644 (file)
@@ -2177,7 +2177,7 @@ static void drbd_connector_callback(struct cn_msg *req, struct netlink_skb_parms
                return;
        }
 
-       if (!cap_raised(nsp->eff_cap, CAP_SYS_ADMIN)) {
+       if (!cap_raised(current_cap(), CAP_SYS_ADMIN)) {
                retcode = ERR_PERM;
                goto fail;
        }
index b9ba04f..77fc76f 100644 (file)
@@ -3281,7 +3281,7 @@ static int set_geometry(unsigned int cmd, struct floppy_struct *g,
                        struct block_device *bdev = opened_bdev[cnt];
                        if (!bdev || ITYPE(drive_state[cnt].fd_device) != type)
                                continue;
-                       __invalidate_device(bdev);
+                       __invalidate_device(bdev, true);
                }
                mutex_unlock(&open_lock);
        } else {
index 49e6a54..dbf31ec 100644 (file)
@@ -78,7 +78,6 @@
 
 #include <asm/uaccess.h>
 
-static DEFINE_MUTEX(loop_mutex);
 static LIST_HEAD(loop_devices);
 static DEFINE_MUTEX(loop_devices_mutex);
 
@@ -1501,11 +1500,9 @@ static int lo_open(struct block_device *bdev, fmode_t mode)
 {
        struct loop_device *lo = bdev->bd_disk->private_data;
 
-       mutex_lock(&loop_mutex);
        mutex_lock(&lo->lo_ctl_mutex);
        lo->lo_refcnt++;
        mutex_unlock(&lo->lo_ctl_mutex);
-       mutex_unlock(&loop_mutex);
 
        return 0;
 }
@@ -1515,7 +1512,6 @@ static int lo_release(struct gendisk *disk, fmode_t mode)
        struct loop_device *lo = disk->private_data;
        int err;
 
-       mutex_lock(&loop_mutex);
        mutex_lock(&lo->lo_ctl_mutex);
 
        if (--lo->lo_refcnt)
@@ -1540,7 +1536,6 @@ static int lo_release(struct gendisk *disk, fmode_t mode)
 out:
        mutex_unlock(&lo->lo_ctl_mutex);
 out_unlocked:
-       mutex_unlock(&loop_mutex);
        return 0;
 }
 
index 411ae9c..7e0ebd4 100644 (file)
@@ -1043,8 +1043,6 @@ static int btusb_probe(struct usb_interface *intf,
 
        usb_set_intfdata(intf, data);
 
-       usb_enable_autosuspend(interface_to_usbdev(intf));
-
        return 0;
 }
 
index 9252e85..780498d 100644 (file)
@@ -773,18 +773,23 @@ int __init agp_amd64_init(void)
 #else
                        printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
 #endif
+                       pci_unregister_driver(&agp_amd64_pci_driver);
                        return -ENODEV;
                }
 
                /* First check that we have at least one AMD64 NB */
-               if (!pci_dev_present(amd_nb_misc_ids))
+               if (!pci_dev_present(amd_nb_misc_ids)) {
+                       pci_unregister_driver(&agp_amd64_pci_driver);
                        return -ENODEV;
+               }
 
                /* Look for any AGP bridge */
                agp_amd64_pci_driver.id_table = agp_amd64_pci_promisc_table;
                err = driver_attach(&agp_amd64_pci_driver.driver);
-               if (err == 0 && agp_bridges_found == 0)
+               if (err == 0 && agp_bridges_found == 0) {
+                       pci_unregister_driver(&agp_amd64_pci_driver);
                        err = -ENODEV;
+               }
        }
        return err;
 }
index c195bfe..5feebe2 100644 (file)
 #define INTEL_GMCH_GMS_STOLEN_352M     (0xd << 4)
 
 #define I915_IFPADDR    0x60
+#define I830_HIC        0x70
 
 /* Intel 965G registers */
 #define I965_MSAC 0x62
index fab3d32..0d09b53 100644 (file)
@@ -21,6 +21,7 @@
 #include <linux/kernel.h>
 #include <linux/pagemap.h>
 #include <linux/agp_backend.h>
+#include <linux/delay.h>
 #include <asm/smp.h>
 #include "agp.h"
 #include "intel-agp.h"
@@ -70,12 +71,8 @@ static struct _intel_private {
        u32 __iomem *gtt;               /* I915G */
        bool clear_fake_agp; /* on first access via agp, fill with scratch */
        int num_dcache_entries;
-       union {
-               void __iomem *i9xx_flush_page;
-               void *i8xx_flush_page;
-       };
+       void __iomem *i9xx_flush_page;
        char *i81x_gtt_table;
-       struct page *i8xx_page;
        struct resource ifp_resource;
        int resource_valid;
        struct page *scratch_page;
@@ -722,28 +719,6 @@ static int intel_fake_agp_fetch_size(void)
 
 static void i830_cleanup(void)
 {
-       if (intel_private.i8xx_flush_page) {
-               kunmap(intel_private.i8xx_flush_page);
-               intel_private.i8xx_flush_page = NULL;
-       }
-
-       __free_page(intel_private.i8xx_page);
-       intel_private.i8xx_page = NULL;
-}
-
-static void intel_i830_setup_flush(void)
-{
-       /* return if we've already set the flush mechanism up */
-       if (intel_private.i8xx_page)
-               return;
-
-       intel_private.i8xx_page = alloc_page(GFP_KERNEL);
-       if (!intel_private.i8xx_page)
-               return;
-
-       intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
-       if (!intel_private.i8xx_flush_page)
-               i830_cleanup();
 }
 
 /* The chipset_flush interface needs to get data that has already been
@@ -758,14 +733,27 @@ static void intel_i830_setup_flush(void)
  */
 static void i830_chipset_flush(void)
 {
-       unsigned int *pg = intel_private.i8xx_flush_page;
+       unsigned long timeout = jiffies + msecs_to_jiffies(1000);
+
+       /* Forcibly evict everything from the CPU write buffers.
+        * clflush appears to be insufficient.
+        */
+       wbinvd_on_all_cpus();
+
+       /* Now we've only seen documents for this magic bit on 855GM,
+        * we hope it exists for the other gen2 chipsets...
+        *
+        * Also works as advertised on my 845G.
+        */
+       writel(readl(intel_private.registers+I830_HIC) | (1<<31),
+              intel_private.registers+I830_HIC);
 
-       memset(pg, 0, 1024);
+       while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
+               if (time_after(jiffies, timeout))
+                       break;
 
-       if (cpu_has_clflush)
-               clflush_cache_range(pg, 1024);
-       else if (wbinvd_on_all_cpus() != 0)
-               printk(KERN_ERR "Timed out waiting for cache flush.\n");
+               udelay(50);
+       }
 }
 
 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
@@ -849,8 +837,6 @@ static int i830_setup(void)
 
        intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
 
-       intel_i830_setup_flush();
-
        return 0;
 }
 
index 777181a..bcbbc71 100644 (file)
@@ -830,8 +830,7 @@ static void monitor_card(unsigned long p)
                            test_bit(IS_ANY_T1, &dev->flags))) {
                                DEBUGP(4, dev, "Perform AUTOPPS\n");
                                set_bit(IS_AUTOPPS_ACT, &dev->flags);
-                               ptsreq.protocol = ptsreq.protocol =
-                                   (0x01 << dev->proto);
+                               ptsreq.protocol = (0x01 << dev->proto);
                                ptsreq.flags = 0x01;
                                ptsreq.pts1 = 0x00;
                                ptsreq.pts2 = 0x00;
index 94b8eb4..444155a 100644 (file)
@@ -78,7 +78,6 @@ static void signalled_reboot_callback(void *callback_data)
 static int ipwireless_probe(struct pcmcia_device *p_dev, void *priv_data)
 {
        struct ipw_dev *ipw = priv_data;
-       struct resource *io_resource;
        int ret;
 
        p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
@@ -92,9 +91,12 @@ static int ipwireless_probe(struct pcmcia_device *p_dev, void *priv_data)
        if (ret)
                return ret;
 
-       io_resource = request_region(p_dev->resource[0]->start,
-                               resource_size(p_dev->resource[0]),
-                               IPWIRELESS_PCCARD_NAME);
+       if (!request_region(p_dev->resource[0]->start,
+                           resource_size(p_dev->resource[0]),
+                           IPWIRELESS_PCCARD_NAME)) {
+               ret = -EBUSY;
+               goto exit;
+       }
 
        p_dev->resource[2]->flags |=
                WIN_DATA_WIDTH_16 | WIN_MEMORY_TYPE_CM | WIN_ENABLE;
@@ -105,22 +107,25 @@ static int ipwireless_probe(struct pcmcia_device *p_dev, void *priv_data)
 
        ret = pcmcia_map_mem_page(p_dev, p_dev->resource[2], p_dev->card_addr);
        if (ret != 0)
-               goto exit2;
+               goto exit1;
 
        ipw->is_v2_card = resource_size(p_dev->resource[2]) == 0x100;
 
-       ipw->attr_memory = ioremap(p_dev->resource[2]->start,
+       ipw->common_memory = ioremap(p_dev->resource[2]->start,
                                resource_size(p_dev->resource[2]));
-       request_mem_region(p_dev->resource[2]->start,
-                       resource_size(p_dev->resource[2]),
-                       IPWIRELESS_PCCARD_NAME);
+       if (!request_mem_region(p_dev->resource[2]->start,
+                               resource_size(p_dev->resource[2]),
+                               IPWIRELESS_PCCARD_NAME)) {
+               ret = -EBUSY;
+               goto exit2;
+       }
 
        p_dev->resource[3]->flags |= WIN_DATA_WIDTH_16 | WIN_MEMORY_TYPE_AM |
                                        WIN_ENABLE;
        p_dev->resource[3]->end = 0; /* this used to be 0x1000 */
        ret = pcmcia_request_window(p_dev, p_dev->resource[3], 0);
        if (ret != 0)
-               goto exit2;
+               goto exit3;
 
        ret = pcmcia_map_mem_page(p_dev, p_dev->resource[3], 0);
        if (ret != 0)
@@ -128,23 +133,28 @@ static int ipwireless_probe(struct pcmcia_device *p_dev, void *priv_data)
 
        ipw->attr_memory = ioremap(p_dev->resource[3]->start,
                                resource_size(p_dev->resource[3]));
-       request_mem_region(p_dev->resource[3]->start,
-                       resource_size(p_dev->resource[3]),
-                       IPWIRELESS_PCCARD_NAME);
+       if (!request_mem_region(p_dev->resource[3]->start,
+                               resource_size(p_dev->resource[3]),
+                               IPWIRELESS_PCCARD_NAME)) {
+               ret = -EBUSY;
+               goto exit4;
+       }
 
        return 0;
 
+exit4:
+       iounmap(ipw->attr_memory);
 exit3:
+       release_mem_region(p_dev->resource[2]->start,
+                       resource_size(p_dev->resource[2]));
 exit2:
-       if (ipw->common_memory) {
-               release_mem_region(p_dev->resource[2]->start,
-                               resource_size(p_dev->resource[2]));
-               iounmap(ipw->common_memory);
-       }
+       iounmap(ipw->common_memory);
 exit1:
-       release_resource(io_resource);
+       release_region(p_dev->resource[0]->start,
+                      resource_size(p_dev->resource[0]));
+exit:
        pcmcia_disable_device(p_dev);
-       return -1;
+       return ret;
 }
 
 static int config_ipwireless(struct ipw_dev *ipw)
@@ -219,6 +229,8 @@ exit:
 
 static void release_ipwireless(struct ipw_dev *ipw)
 {
+       release_region(ipw->link->resource[0]->start,
+                      resource_size(ipw->link->resource[0]));
        if (ipw->common_memory) {
                release_mem_region(ipw->link->resource[2]->start,
                                resource_size(ipw->link->resource[2]));
index faf5a2c..1f46f1c 100644 (file)
@@ -364,14 +364,12 @@ unsigned long tpm_calc_ordinal_duration(struct tpm_chip *chip,
                    tpm_protected_ordinal_duration[ordinal &
                                                   TPM_PROTECTED_ORDINAL_MASK];
 
-       if (duration_idx != TPM_UNDEFINED) {
+       if (duration_idx != TPM_UNDEFINED)
                duration = chip->vendor.duration[duration_idx];
-               /* if duration is 0, it's because chip->vendor.duration wasn't */
-               /* filled yet, so we set the lowest timeout just to give enough */
-               /* time for tpm_get_timeouts() to succeed */
-               return (duration <= 0 ? HZ : duration);
-       } else
+       if (duration <= 0)
                return 2 * 60 * HZ;
+       else
+               return duration;
 }
 EXPORT_SYMBOL_GPL(tpm_calc_ordinal_duration);
 
@@ -577,11 +575,9 @@ duration:
        if (rc)
                return;
 
-       if (be32_to_cpu(tpm_cmd.header.out.return_code) != 0 ||
-           be32_to_cpu(tpm_cmd.header.out.length)
-           != sizeof(tpm_cmd.header.out) + sizeof(u32) + 3 * sizeof(u32))
+       if (be32_to_cpu(tpm_cmd.header.out.return_code)
+           != 3 * sizeof(u32))
                return;
-
        duration_cap = &tpm_cmd.params.getcap_out.cap.duration;
        chip->vendor.duration[TPM_SHORT] =
            usecs_to_jiffies(be32_to_cpu(duration_cap->tpm_short));
@@ -941,18 +937,6 @@ ssize_t tpm_show_caps_1_2(struct device * dev,
 }
 EXPORT_SYMBOL_GPL(tpm_show_caps_1_2);
 
-ssize_t tpm_show_timeouts(struct device *dev, struct device_attribute *attr,
-                         char *buf)
-{
-       struct tpm_chip *chip = dev_get_drvdata(dev);
-
-       return sprintf(buf, "%d %d %d\n",
-                      jiffies_to_usecs(chip->vendor.duration[TPM_SHORT]),
-                      jiffies_to_usecs(chip->vendor.duration[TPM_MEDIUM]),
-                      jiffies_to_usecs(chip->vendor.duration[TPM_LONG]));
-}
-EXPORT_SYMBOL_GPL(tpm_show_timeouts);
-
 ssize_t tpm_store_cancel(struct device *dev, struct device_attribute *attr,
                        const char *buf, size_t count)
 {
index d84ff77..72ddb03 100644 (file)
@@ -56,8 +56,6 @@ extern ssize_t tpm_show_owned(struct device *, struct device_attribute *attr,
                                char *);
 extern ssize_t tpm_show_temp_deactivated(struct device *,
                                         struct device_attribute *attr, char *);
-extern ssize_t tpm_show_timeouts(struct device *,
-                                struct device_attribute *attr, char *);
 
 struct tpm_chip;
 
index 0d1d38e..dd21df5 100644 (file)
@@ -376,7 +376,6 @@ static DEVICE_ATTR(temp_deactivated, S_IRUGO, tpm_show_temp_deactivated,
                   NULL);
 static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps_1_2, NULL);
 static DEVICE_ATTR(cancel, S_IWUSR | S_IWGRP, NULL, tpm_store_cancel);
-static DEVICE_ATTR(timeouts, S_IRUGO, tpm_show_timeouts, NULL);
 
 static struct attribute *tis_attrs[] = {
        &dev_attr_pubek.attr,
@@ -386,8 +385,7 @@ static struct attribute *tis_attrs[] = {
        &dev_attr_owned.attr,
        &dev_attr_temp_deactivated.attr,
        &dev_attr_caps.attr,
-       &dev_attr_cancel.attr,
-       &dev_attr_timeouts.attr, NULL,
+       &dev_attr_cancel.attr, NULL,
 };
 
 static struct attribute_group tis_attr_grp = {
index 1109f68..5cb4d09 100644 (file)
@@ -1919,8 +1919,10 @@ int cpufreq_register_driver(struct cpufreq_driver *driver_data)
 
        ret = sysdev_driver_register(&cpu_sysdev_class,
                                        &cpufreq_sysdev_driver);
+       if (ret)
+               goto err_null_driver;
 
-       if ((!ret) && !(cpufreq_driver->flags & CPUFREQ_STICKY)) {
+       if (!(cpufreq_driver->flags & CPUFREQ_STICKY)) {
                int i;
                ret = -ENODEV;
 
@@ -1935,21 +1937,22 @@ int cpufreq_register_driver(struct cpufreq_driver *driver_data)
                if (ret) {
                        dprintk("no CPU initialized for driver %s\n",
                                                        driver_data->name);
-                       sysdev_driver_unregister(&cpu_sysdev_class,
-                                               &cpufreq_sysdev_driver);
-
-                       spin_lock_irqsave(&cpufreq_driver_lock, flags);
-                       cpufreq_driver = NULL;
-                       spin_unlock_irqrestore(&cpufreq_driver_lock, flags);
+                       goto err_sysdev_unreg;
                }
        }
 
-       if (!ret) {
-               register_hotcpu_notifier(&cpufreq_cpu_notifier);
-               dprintk("driver %s up and running\n", driver_data->name);
-               cpufreq_debug_enable_ratelimit();
-       }
+       register_hotcpu_notifier(&cpufreq_cpu_notifier);
+       dprintk("driver %s up and running\n", driver_data->name);
+       cpufreq_debug_enable_ratelimit();
 
+       return 0;
+err_sysdev_unreg:
+       sysdev_driver_unregister(&cpu_sysdev_class,
+                       &cpufreq_sysdev_driver);
+err_null_driver:
+       spin_lock_irqsave(&cpufreq_driver_lock, flags);
+       cpufreq_driver = NULL;
+       spin_unlock_irqrestore(&cpufreq_driver_lock, flags);
        return ret;
 }
 EXPORT_SYMBOL_GPL(cpufreq_register_driver);
index 3dadfa2..28d1d3c 100644 (file)
@@ -164,8 +164,10 @@ static void vblank_disable_and_save(struct drm_device *dev, int crtc)
         * available. In that case we can't account for this and just
         * hope for the best.
         */
-       if ((vblrc > 0) && (abs(diff_ns) > 1000000))
+       if ((vblrc > 0) && (abs64(diff_ns) > 1000000)) {
                atomic_inc(&dev->_vblank_count[crtc]);
+               smp_mb__after_atomic_inc();
+       }
 
        /* Invalidate all timestamps while vblank irq's are off. */
        clear_vblank_timestamps(dev, crtc);
@@ -491,6 +493,12 @@ void drm_calc_timestamping_constants(struct drm_crtc *crtc)
        /* Dot clock in Hz: */
        dotclock = (u64) crtc->hwmode.clock * 1000;
 
+       /* Fields of interlaced scanout modes are only halve a frame duration.
+        * Double the dotclock to get halve the frame-/line-/pixelduration.
+        */
+       if (crtc->hwmode.flags & DRM_MODE_FLAG_INTERLACE)
+               dotclock *= 2;
+
        /* Valid dotclock? */
        if (dotclock > 0) {
                /* Convert scanline length in pixels and video dot clock to
@@ -603,14 +611,6 @@ int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev, int crtc,
                return -EAGAIN;
        }
 
-       /* Don't know yet how to handle interlaced or
-        * double scan modes. Just no-op for now.
-        */
-       if (mode->flags & (DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLSCAN)) {
-               DRM_DEBUG("crtc %d: Noop due to unsupported mode.\n", crtc);
-               return -ENOTSUPP;
-       }
-
        /* Get current scanout position with system timestamp.
         * Repeat query up to DRM_TIMESTAMP_MAXRETRIES times
         * if single query takes longer than max_error nanoseconds.
@@ -858,10 +858,11 @@ static void drm_update_vblank_count(struct drm_device *dev, int crtc)
        if (rc) {
                tslot = atomic_read(&dev->_vblank_count[crtc]) + diff;
                vblanktimestamp(dev, crtc, tslot) = t_vblank;
-               smp_wmb();
        }
 
+       smp_mb__before_atomic_inc();
        atomic_add(diff, &dev->_vblank_count[crtc]);
+       smp_mb__after_atomic_inc();
 }
 
 /**
@@ -1011,7 +1012,8 @@ int drm_modeset_ctl(struct drm_device *dev, void *data,
                    struct drm_file *file_priv)
 {
        struct drm_modeset_ctl *modeset = data;
-       int crtc, ret = 0;
+       int ret = 0;
+       unsigned int crtc;
 
        /* If drm_vblank_init() hasn't been called yet, just no-op */
        if (!dev->num_crtcs)
@@ -1293,15 +1295,16 @@ bool drm_handle_vblank(struct drm_device *dev, int crtc)
         * e.g., due to spurious vblank interrupts. We need to
         * ignore those for accounting.
         */
-       if (abs(diff_ns) > DRM_REDUNDANT_VBLIRQ_THRESH_NS) {
+       if (abs64(diff_ns) > DRM_REDUNDANT_VBLIRQ_THRESH_NS) {
                /* Store new timestamp in ringbuffer. */
                vblanktimestamp(dev, crtc, vblcount + 1) = tvblank;
-               smp_wmb();
 
                /* Increment cooked vblank count. This also atomically commits
                 * the timestamp computed above.
                 */
+               smp_mb__before_atomic_inc();
                atomic_inc(&dev->_vblank_count[crtc]);
+               smp_mb__after_atomic_inc();
        } else {
                DRM_DEBUG("crtc %d: Redundant vblirq ignored. diff_ns = %d\n",
                          crtc, (int) diff_ns);
index 17bd766..e33d9be 100644 (file)
@@ -1895,6 +1895,17 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
        if (IS_GEN2(dev))
                dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
 
+       /* 965GM sometimes incorrectly writes to hardware status page (HWS)
+        * using 32bit addressing, overwriting memory if HWS is located
+        * above 4GB.
+        *
+        * The documentation also mentions an issue with undefined
+        * behaviour if any general state is accessed within a page above 4GB,
+        * which also needs to be handled carefully.
+        */
+       if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
+               dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
+
        mmio_bar = IS_GEN2(dev) ? 1 : 0;
        dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
        if (!dev_priv->regs) {
index 22a32b9..79a04fd 100644 (file)
@@ -184,7 +184,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 static bool
 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
 {
-       int tile_width;
+       int tile_width, tile_height;
 
        /* Linear is always fine */
        if (tiling_mode == I915_TILING_NONE)
@@ -215,6 +215,20 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
                }
        }
 
+       if (IS_GEN2(dev) ||
+           (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
+               tile_height = 32;
+       else
+               tile_height = 8;
+       /* i8xx is strange: It has 2 interleaved rows of tiles, so needs an even
+        * number of tile rows. */
+       if (IS_GEN2(dev))
+               tile_height *= 2;
+
+       /* Size needs to be aligned to a full tile row */
+       if (size & (tile_height * stride - 1))
+               return false;
+
        /* 965+ just needs multiples of tile width */
        if (INTEL_INFO(dev)->gen >= 4) {
                if (stride & (tile_width - 1))
index 97f946d..8a9e08b 100644 (file)
@@ -316,6 +316,8 @@ static void i915_hotplug_work_func(struct work_struct *work)
        struct drm_mode_config *mode_config = &dev->mode_config;
        struct intel_encoder *encoder;
 
+       DRM_DEBUG_KMS("running encoder hotplug functions\n");
+
        list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
                if (encoder->hot_plug)
                        encoder->hot_plug(encoder);
@@ -1649,9 +1651,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
        } else {
                hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
                               SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
-               hotplug_mask |= SDE_AUX_MASK | SDE_FDI_MASK | SDE_TRANS_MASK;
-               I915_WRITE(FDI_RXA_IMR, 0);
-               I915_WRITE(FDI_RXB_IMR, 0);
+               hotplug_mask |= SDE_AUX_MASK;
        }
 
        dev_priv->pch_irq_mask = ~hotplug_mask;
index 15d94c6..729d423 100644 (file)
 
 /* Backlight control */
 #define BLC_PWM_CTL            0x61254
-#define   BACKLIGHT_MODULATION_FREQ_SHIFT              (17)
 #define BLC_PWM_CTL2           0x61250 /* 965+ only */
-#define   BLM_COMBINATION_MODE (1 << 30)
-/*
- * This is the most significant 15 bits of the number of backlight cycles in a
- * complete cycle of the modulated backlight control.
- *
- * The actual value is this field multiplied by two.
- */
-#define   BACKLIGHT_MODULATION_FREQ_MASK               (0x7fff << 17)
-#define   BLM_LEGACY_MODE                              (1 << 16)
 /*
  * This is the number of cycles out of the backlight modulation cycle for which
  * the backlight is on.
index 3b00653..e79b25b 100644 (file)
@@ -1630,19 +1630,19 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
 
                wait_event(dev_priv->pending_flip_queue,
+                          atomic_read(&dev_priv->mm.wedged) ||
                           atomic_read(&obj->pending_flip) == 0);
 
                /* Big Hammer, we also need to ensure that any pending
                 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
                 * current scanout is retired before unpinning the old
                 * framebuffer.
+                *
+                * This should only fail upon a hung GPU, in which case we
+                * can safely continue.
                 */
                ret = i915_gem_object_flush_gpu(obj, false);
-               if (ret) {
-                       i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
-                       mutex_unlock(&dev->struct_mutex);
-                       return ret;
-               }
+               (void) ret;
        }
 
        ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
@@ -2045,6 +2045,31 @@ static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
                   atomic_read(&obj->pending_flip) == 0);
 }
 
+static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
+{
+       struct drm_device *dev = crtc->dev;
+       struct drm_mode_config *mode_config = &dev->mode_config;
+       struct intel_encoder *encoder;
+
+       /*
+        * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
+        * must be driven by its own crtc; no sharing is possible.
+        */
+       list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
+               if (encoder->base.crtc != crtc)
+                       continue;
+
+               switch (encoder->type) {
+               case INTEL_OUTPUT_EDP:
+                       if (!intel_encoder_is_pch_edp(&encoder->base))
+                               return false;
+                       continue;
+               }
+       }
+
+       return true;
+}
+
 static void ironlake_crtc_enable(struct drm_crtc *crtc)
 {
        struct drm_device *dev = crtc->dev;
@@ -2053,6 +2078,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
        int pipe = intel_crtc->pipe;
        int plane = intel_crtc->plane;
        u32 reg, temp;
+       bool is_pch_port = false;
 
        if (intel_crtc->active)
                return;
@@ -2066,7 +2092,56 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
                        I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
        }
 
-       ironlake_fdi_enable(crtc);
+       is_pch_port = intel_crtc_driving_pch(crtc);
+
+       if (is_pch_port)
+               ironlake_fdi_enable(crtc);
+       else {
+               /* disable CPU FDI tx and PCH FDI rx */
+               reg = FDI_TX_CTL(pipe);
+               temp = I915_READ(reg);
+               I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
+               POSTING_READ(reg);
+
+               reg = FDI_RX_CTL(pipe);
+               temp = I915_READ(reg);
+               temp &= ~(0x7 << 16);
+               temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
+               I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
+
+               POSTING_READ(reg);
+               udelay(100);
+
+               /* Ironlake workaround, disable clock pointer after downing FDI */
+               if (HAS_PCH_IBX(dev))
+                       I915_WRITE(FDI_RX_CHICKEN(pipe),
+                                  I915_READ(FDI_RX_CHICKEN(pipe) &
+                                            ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
+
+               /* still set train pattern 1 */
+               reg = FDI_TX_CTL(pipe);
+               temp = I915_READ(reg);
+               temp &= ~FDI_LINK_TRAIN_NONE;
+               temp |= FDI_LINK_TRAIN_PATTERN_1;
+               I915_WRITE(reg, temp);
+
+               reg = FDI_RX_CTL(pipe);
+               temp = I915_READ(reg);
+               if (HAS_PCH_CPT(dev)) {
+                       temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
+                       temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
+               } else {
+                       temp &= ~FDI_LINK_TRAIN_NONE;
+                       temp |= FDI_LINK_TRAIN_PATTERN_1;
+               }
+               /* BPC in FDI rx is consistent with that in PIPECONF */
+               temp &= ~(0x07 << 16);
+               temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
+               I915_WRITE(reg, temp);
+
+               POSTING_READ(reg);
+               udelay(100);
+       }
 
        /* Enable panel fitting for LVDS */
        if (dev_priv->pch_pf_size &&
@@ -2100,6 +2175,10 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
                intel_flush_display_plane(dev, plane);
        }
 
+       /* Skip the PCH stuff if possible */
+       if (!is_pch_port)
+               goto done;
+
        /* For PCH output, training FDI link */
        if (IS_GEN6(dev))
                gen6_fdi_link_train(crtc);
@@ -2184,7 +2263,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
        I915_WRITE(reg, temp | TRANS_ENABLE);
        if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
                DRM_ERROR("failed to enable transcoder %d\n", pipe);
-
+done:
        intel_crtc_load_lut(crtc);
        intel_update_fbc(dev);
        intel_crtc_update_cursor(crtc, true);
@@ -6496,7 +6575,7 @@ static void ironlake_disable_rc6(struct drm_device *dev)
                POSTING_READ(RSTDBYCTL);
        }
 
-       ironlake_disable_rc6(dev);
+       ironlake_teardown_rc6(dev);
 }
 
 static int ironlake_setup_rc6(struct drm_device *dev)
index c65992d..d860abe 100644 (file)
@@ -30,8 +30,6 @@
 
 #include "intel_drv.h"
 
-#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
-
 void
 intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
                       struct drm_display_mode *adjusted_mode)
@@ -112,19 +110,6 @@ done:
        dev_priv->pch_pf_size = (width << 16) | height;
 }
 
-static int is_backlight_combination_mode(struct drm_device *dev)
-{
-       struct drm_i915_private *dev_priv = dev->dev_private;
-
-       if (INTEL_INFO(dev)->gen >= 4)
-               return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
-
-       if (IS_GEN2(dev))
-               return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
-
-       return 0;
-}
-
 static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
 {
        u32 val;
@@ -181,9 +166,6 @@ u32 intel_panel_get_max_backlight(struct drm_device *dev)
                        if (INTEL_INFO(dev)->gen < 4)
                                max &= ~1;
                }
-
-               if (is_backlight_combination_mode(dev))
-                       max *= 0xff;
        }
 
        DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
@@ -201,15 +183,6 @@ u32 intel_panel_get_backlight(struct drm_device *dev)
                val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
                if (IS_PINEVIEW(dev))
                        val >>= 1;
-
-               if (is_backlight_combination_mode(dev)){
-                       u8 lbpc;
-
-                       val &= ~1;
-                       pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
-                       val *= lbpc;
-                       val >>= 1;
-               }
        }
 
        DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
@@ -232,16 +205,6 @@ void intel_panel_set_backlight(struct drm_device *dev, u32 level)
 
        if (HAS_PCH_SPLIT(dev))
                return intel_pch_panel_set_backlight(dev, level);
-
-       if (is_backlight_combination_mode(dev)){
-               u32 max = intel_panel_get_max_backlight(dev);
-               u8 lpbc;
-
-               lpbc = level * 0xfe / max + 1;
-               level /= lpbc;
-               pci_write_config_byte(dev->pdev, PCI_LBPC, lpbc);
-       }
-
        tmp = I915_READ(BLC_PWM_CTL);
        if (IS_PINEVIEW(dev)) {
                tmp &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
index d38a4d9..a521840 100644 (file)
@@ -49,7 +49,10 @@ nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
                DRM_ERROR("bo %p still attached to GEM object\n", bo);
 
        nv10_mem_put_tile_region(dev, nvbo->tile, NULL);
-       nouveau_vm_put(&nvbo->vma);
+       if (nvbo->vma.node) {
+               nouveau_vm_unmap(&nvbo->vma);
+               nouveau_vm_put(&nvbo->vma);
+       }
        kfree(nvbo);
 }
 
index 56deae5..93fa735 100644 (file)
@@ -3490,7 +3490,7 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track
                track->num_texture = 16;
                track->maxy = 4096;
                track->separate_cube = 0;
-               track->aaresolve = true;
+               track->aaresolve = false;
                track->aa.robj = NULL;
        }
 
@@ -3801,8 +3801,6 @@ static int r100_startup(struct radeon_device *rdev)
        r100_mc_program(rdev);
        /* Resume clock */
        r100_clock_startup(rdev);
-       /* Initialize GPU configuration (# pipes, ...) */
-//     r100_gpu_init(rdev);
        /* Initialize GART (initialize after TTM so we can allocate
         * memory through TTM but finalize after TTM) */
        r100_enable_bm(rdev);
index 0e65709..3e7e7f9 100644 (file)
@@ -971,7 +971,7 @@ void radeon_compute_pll_legacy(struct radeon_pll *pll,
                max_fractional_feed_div = pll->max_frac_feedback_div;
        }
 
-       for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
+       for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
                uint32_t ref_div;
 
                if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
index 66324b5..cc44bdf 100644 (file)
@@ -113,11 +113,14 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
        u32 tiling_flags = 0;
        int ret;
        int aligned_size, size;
+       int height = mode_cmd->height;
 
        /* need to align pitch with crtc limits */
        mode_cmd->pitch = radeon_align_pitch(rdev, mode_cmd->width, mode_cmd->bpp, fb_tiled) * ((mode_cmd->bpp + 1) / 8);
 
-       size = mode_cmd->pitch * mode_cmd->height;
+       if (rdev->family >= CHIP_R600)
+               height = ALIGN(mode_cmd->height, 8);
+       size = mode_cmd->pitch * height;
        aligned_size = ALIGN(size, PAGE_SIZE);
        ret = radeon_gem_object_create(rdev, aligned_size, 0,
                                       RADEON_GEM_DOMAIN_VRAM,
index 773e484..297bc9a 100644 (file)
@@ -238,13 +238,13 @@ config SENSORS_K8TEMP
          will be called k8temp.
 
 config SENSORS_K10TEMP
-       tristate "AMD Phenom/Sempron/Turion/Opteron temperature sensor"
+       tristate "AMD Family 10h/11h/12h/14h temperature sensor"
        depends on X86 && PCI
        help
          If you say yes here you get support for the temperature
          sensor(s) inside your CPU. Supported are later revisions of
-         the AMD Family 10h and all revisions of the AMD Family 11h
-    &