Arm: tegra: p1852: Changed sclk to run at max.
Mohit Kataria [Mon, 7 May 2012 06:58:34 +0000 (11:58 +0530)]
Sclk frequecy changes depending on the clocks derived from sclk.
Changed it to run at max POR frequecy.

Bug 971061

Change-Id: I357e1acd8d049bf233ff79b942c911db123865f6
Signed-off-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-on: http://git-master/r/100859
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

arch/arm/mach-tegra/board-p1852.c

index 020671a..fe7d9d5 100644 (file)
@@ -141,6 +141,7 @@ static __initdata struct tegra_clk_init_table p1852_clk_init_table[] = {
        { "i2c4",               "pll_p",        3200000,        true},
        { "i2c5",               "pll_p",        3200000,        true},
        { "sdmmc2",             "pll_p",        104000000,      false},
+       {"wake.sclk",           NULL,           334000000,      true },
        { NULL,                 NULL,           0,              0},
 };