spi: tegra: dump registers when error occurs
Ashwini Ghuge [Wed, 20 Jun 2012 08:22:45 +0000 (13:22 +0530)]
When any error occurs in spi communication,
dump the spi registers for debug purpose

Change-Id: I5cf226d4b504c95a6abb8dcf5b8c0ba1ef44271c
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/109466
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

drivers/spi/spi-tegra.c

index 0af220c..7b3382e 100644 (file)
@@ -590,6 +590,7 @@ static int spi_tegra_start_dma_based_transfer(
                udelay(1);
                wmb();
        }
+       tspi->dma_control_reg = val;
 
        val |= SLINK_DMA_EN;
        spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
@@ -627,6 +628,7 @@ static int spi_tegra_start_cpu_based_transfer(
                udelay(1);
                wmb();
        }
+       tspi->dma_control_reg = val;
        val |= SLINK_DMA_EN;
        spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
        return 0;
@@ -1045,6 +1047,9 @@ static void handle_cpu_based_xfer(void *context_data)
                                (tspi->status_reg & SLINK_BSY)) {
                dev_err(&tspi->pdev->dev, "%s ERROR bit set 0x%x\n",
                                         __func__, tspi->status_reg);
+               dev_err(&tspi->pdev->dev, "%s 0x%08x:0x%08x:0x%08x\n",
+                               __func__, tspi->command_reg, tspi->command2_reg,
+                               tspi->dma_control_reg);
                tegra_periph_reset_assert(tspi->clk);
                udelay(2);
                tegra_periph_reset_deassert(tspi->clk);
@@ -1133,6 +1138,9 @@ static irqreturn_t spi_tegra_isr_thread(int irq, void *context_data)
        if (err) {
                dev_err(&tspi->pdev->dev, "%s ERROR bit set 0x%x\n",
                                         __func__, tspi->status_reg);
+               dev_err(&tspi->pdev->dev, "%s 0x%08x:0x%08x:0x%08x\n",
+                               __func__, tspi->command_reg, tspi->command2_reg,
+                               tspi->dma_control_reg);
                tegra_periph_reset_assert(tspi->clk);
                udelay(2);
                tegra_periph_reset_deassert(tspi->clk);