[PATCH] Add adm8211 802.11b wireless driver
Michael Wu [Fri, 31 Aug 2007 05:15:25 +0000 (01:15 -0400)]
This patch adds a mac80211 wireless driver for ADMtek ADM8211 based
wireless cards.

Signed-off-by: Michael Wu <flamingice@sourmilk.net>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

MAINTAINERS
drivers/net/wireless/Kconfig
drivers/net/wireless/Makefile
drivers/net/wireless/adm8211.c [new file with mode: 0644]
drivers/net/wireless/adm8211.h [new file with mode: 0644]

index 9a91d9e..e0861f7 100644 (file)
@@ -284,6 +284,14 @@ M: corentin.labbe@geomatys.fr
 L:     lm-sensors@lm-sensors.org
 S:     Maintained
 
+ADM8211 WIRELESS DRIVER
+P:     Michael Wu
+M:     flamingice@sourmilk.net
+L:     linux-wireless@vger.kernel.org
+W:     http://linuxwireless.org/
+T:     git kernel.org:/pub/scm/linux/kernel/git/mwu/mac80211-drivers.git
+S:     Maintained
+
 ADT746X FAN DRIVER
 P:     Colin Leroy
 M:     colin@colino.net
index ae27af0..86480af 100644 (file)
@@ -558,6 +558,33 @@ config RTL8187
 
          Thanks to Realtek for their support!
 
+config ADM8211
+       tristate "ADMtek ADM8211 support"
+       depends on MAC80211 && PCI && WLAN_80211 && EXPERIMENTAL
+       select CRC32
+       select EEPROM_93CX6
+       ---help---
+         This driver is for ADM8211A, ADM8211B, and ADM8211C based cards.
+         These are PCI/mini-PCI/Cardbus 802.11b chips found in cards such as:
+
+         Xterasys Cardbus XN-2411b
+         Blitz NetWave Point PC
+         TrendNet 221pc
+         Belkin F5D6001
+         SMC 2635W
+         Linksys WPC11 v1
+         Fiberline FL-WL-200X
+         3com Office Connect (3CRSHPW796)
+         Corega WLPCIB-11
+         SMC 2602W V2 EU
+         D-Link DWL-520 Revision C
+
+         However, some of these cards have been replaced with other chips
+         like the RTL8180L (Xterasys Cardbus XN-2411b, Belkin F5D6001) or
+         the Ralink RT2400 (SMC2635W) without a model number change.
+
+         Thanks to Infineon-ADMtek for their support of this driver.
+
 source "drivers/net/wireless/hostap/Kconfig"
 source "drivers/net/wireless/bcm43xx/Kconfig"
 source "drivers/net/wireless/zd1211rw/Kconfig"
index 4eb6d97..e9bffda 100644 (file)
@@ -47,3 +47,5 @@ obj-$(CONFIG_LIBERTAS)                += libertas/
 
 rtl8187-objs           := rtl8187_dev.o rtl8187_rtl8225.o
 obj-$(CONFIG_RTL8187)  += rtl8187.o
+
+obj-$(CONFIG_ADM8211)  += adm8211.o
diff --git a/drivers/net/wireless/adm8211.c b/drivers/net/wireless/adm8211.c
new file mode 100644 (file)
index 0000000..eec01fc
--- /dev/null
@@ -0,0 +1,2063 @@
+
+/*
+ * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
+ *
+ * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
+ * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
+ * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
+ * and used with permission.
+ *
+ * Much thanks to Infineon-ADMtek for their support of this driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation. See README and COPYING for
+ * more details.
+ */
+
+#include <linux/init.h>
+#include <linux/if.h>
+#include <linux/skbuff.h>
+#include <linux/etherdevice.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/crc32.h>
+#include <linux/eeprom_93cx6.h>
+#include <net/mac80211.h>
+
+#include "adm8211.h"
+
+MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
+MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
+MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
+MODULE_SUPPORTED_DEVICE("ADM8211");
+MODULE_LICENSE("GPL");
+
+static unsigned int tx_ring_size __read_mostly = 16;
+static unsigned int rx_ring_size __read_mostly = 16;
+
+module_param(tx_ring_size, uint, 0);
+module_param(rx_ring_size, uint, 0);
+
+static const char version[] = KERN_INFO "adm8211: "
+"Copyright 2003, Jouni Malinen <j@w1.fi>; "
+"Copyright 2004-2007, Michael Wu <flamingice@sourmilk.net>\n";
+
+
+static struct pci_device_id adm8211_pci_id_table[] __devinitdata = {
+       /* ADMtek ADM8211 */
+       { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
+       { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
+       { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
+       { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
+       { 0 }
+};
+
+static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
+{
+       struct adm8211_priv *priv = eeprom->data;
+       u32 reg = ADM8211_CSR_READ(SPR);
+
+       eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
+       eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
+       eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
+       eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
+}
+
+static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
+{
+       struct adm8211_priv *priv = eeprom->data;
+       u32 reg = 0x4000 | ADM8211_SPR_SRS;
+
+       if (eeprom->reg_data_in)
+               reg |= ADM8211_SPR_SDI;
+       if (eeprom->reg_data_out)
+               reg |= ADM8211_SPR_SDO;
+       if (eeprom->reg_data_clock)
+               reg |= ADM8211_SPR_SCLK;
+       if (eeprom->reg_chip_select)
+               reg |= ADM8211_SPR_SCS;
+
+       ADM8211_CSR_WRITE(SPR, reg);
+       ADM8211_CSR_READ(SPR);          /* eeprom_delay */
+}
+
+static int adm8211_read_eeprom(struct ieee80211_hw *dev)
+{
+       struct adm8211_priv *priv = dev->priv;
+       unsigned int words, i;
+       struct ieee80211_chan_range chan_range;
+       u16 cr49;
+       struct eeprom_93cx6 eeprom = {
+               .data           = priv,
+               .register_read  = adm8211_eeprom_register_read,
+               .register_write = adm8211_eeprom_register_write
+       };
+
+       if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
+               /* 256 * 16-bit = 512 bytes */
+               eeprom.width = PCI_EEPROM_WIDTH_93C66;
+               words = 256;
+       } else {
+               /* 64 * 16-bit = 128 bytes */
+               eeprom.width = PCI_EEPROM_WIDTH_93C46;
+               words = 64;
+       }
+
+       priv->eeprom_len = words * 2;
+       priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
+       if (!priv->eeprom)
+               return -ENOMEM;
+
+       eeprom_93cx6_multiread(&eeprom, 0, (__le16 __force *)priv->eeprom, words);
+
+       cr49 = le16_to_cpu(priv->eeprom->cr49);
+       priv->rf_type = (cr49 >> 3) & 0x7;
+       switch (priv->rf_type) {
+       case ADM8211_TYPE_INTERSIL:
+       case ADM8211_TYPE_RFMD:
+       case ADM8211_TYPE_MARVEL:
+       case ADM8211_TYPE_AIROHA:
+       case ADM8211_TYPE_ADMTEK:
+               break;
+
+       default:
+               if (priv->revid < ADM8211_REV_CA)
+                       priv->rf_type = ADM8211_TYPE_RFMD;
+               else
+                       priv->rf_type = ADM8211_TYPE_AIROHA;
+
+               printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
+                      pci_name(priv->pdev), (cr49 >> 3) & 0x7);
+       }
+
+       priv->bbp_type = cr49 & 0x7;
+       switch (priv->bbp_type) {
+       case ADM8211_TYPE_INTERSIL:
+       case ADM8211_TYPE_RFMD:
+       case ADM8211_TYPE_MARVEL:
+       case ADM8211_TYPE_AIROHA:
+       case ADM8211_TYPE_ADMTEK:
+               break;
+       default:
+               if (priv->revid < ADM8211_REV_CA)
+                       priv->bbp_type = ADM8211_TYPE_RFMD;
+               else
+                       priv->bbp_type = ADM8211_TYPE_ADMTEK;
+
+               printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
+                      pci_name(priv->pdev), cr49 >> 3);
+       }
+
+       if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
+               printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
+                      pci_name(priv->pdev), priv->eeprom->country_code);
+
+               chan_range = cranges[2];
+       } else
+               chan_range = cranges[priv->eeprom->country_code];
+
+       printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
+              pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
+
+       priv->modes[0].num_channels = chan_range.max - chan_range.min + 1;
+       priv->modes[0].channels = priv->channels;
+
+       memcpy(priv->channels, adm8211_channels, sizeof(adm8211_channels));
+
+       for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
+               if (i >= chan_range.min && i <= chan_range.max)
+                       priv->channels[i - 1].flag =
+                               IEEE80211_CHAN_W_SCAN |
+                               IEEE80211_CHAN_W_ACTIVE_SCAN |
+                               IEEE80211_CHAN_W_IBSS;
+
+       switch (priv->eeprom->specific_bbptype) {
+       case ADM8211_BBP_RFMD3000:
+       case ADM8211_BBP_RFMD3002:
+       case ADM8211_BBP_ADM8011:
+               priv->specific_bbptype = priv->eeprom->specific_bbptype;
+               break;
+
+       default:
+               if (priv->revid < ADM8211_REV_CA)
+                       priv->specific_bbptype = ADM8211_BBP_RFMD3000;
+               else
+                       priv->specific_bbptype = ADM8211_BBP_ADM8011;
+
+               printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
+                      pci_name(priv->pdev), priv->eeprom->specific_bbptype);
+       }
+
+       switch (priv->eeprom->specific_rftype) {
+       case ADM8211_RFMD2948:
+       case ADM8211_RFMD2958:
+       case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
+       case ADM8211_MAX2820:
+       case ADM8211_AL2210L:
+               priv->transceiver_type = priv->eeprom->specific_rftype;
+               break;
+
+       default:
+               if (priv->revid == ADM8211_REV_BA)
+                       priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
+               else if (priv->revid == ADM8211_REV_CA)
+                       priv->transceiver_type = ADM8211_AL2210L;
+               else if (priv->revid == ADM8211_REV_AB)
+                       priv->transceiver_type = ADM8211_RFMD2948;
+
+               printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
+                      pci_name(priv->pdev), priv->eeprom->specific_rftype);
+
+               break;
+       }
+
+       printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
+               "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
+              priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
+
+       return 0;
+}
+
+static inline void adm8211_write_sram(struct ieee80211_hw *dev,
+                                     u32 addr, u32 data)
+{
+       struct adm8211_priv *priv = dev->priv;
+
+       ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
+                         (priv->revid < ADM8211_REV_BA ?
+                          0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
+       ADM8211_CSR_READ(WEPCTL);
+       msleep(1);
+
+       ADM8211_CSR_WRITE(WESK, data);
+       ADM8211_CSR_READ(WESK);
+       msleep(1);
+}
+
+static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
+                                    unsigned int addr, u8 *buf,
+                                    unsigned int len)
+{
+       struct adm8211_priv *priv = dev->priv;
+       u32 reg = ADM8211_CSR_READ(WEPCTL);
+       unsigned int i;
+
+       if (priv->revid < ADM8211_REV_BA) {
+               for (i = 0; i < len; i += 2) {
+                       u16 val = buf[i] | (buf[i + 1] << 8);
+                       adm8211_write_sram(dev, addr + i / 2, val);
+               }
+       } else {
+               for (i = 0; i < len; i += 4) {
+                       u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
+                                 (buf[i + 2] << 16) | (buf[i + 3] << 24);
+                       adm8211_write_sram(dev, addr + i / 4, val);
+               }
+       }
+
+       ADM8211_CSR_WRITE(WEPCTL, reg);
+}
+
+static void adm8211_clear_sram(struct ieee80211_hw *dev)
+{
+       struct adm8211_priv *priv = dev->priv;
+       u32 reg = ADM8211_CSR_READ(WEPCTL);
+       unsigned int addr;
+
+       for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
+               adm8211_write_sram(dev, addr, 0);
+
+       ADM8211_CSR_WRITE(WEPCTL, reg);
+}
+
+static int adm8211_get_stats(struct ieee80211_hw *dev,
+                            struct ieee80211_low_level_stats *stats)
+{
+       struct adm8211_priv *priv = dev->priv;
+
+       memcpy(stats, &priv->stats, sizeof(*stats));
+
+       return 0;
+}
+
+static void adm8211_set_rx_mode(struct ieee80211_hw *dev,
+                               unsigned short flags, int mc_count)
+{
+       struct adm8211_priv *priv = dev->priv;
+       unsigned int bit_nr;
+       u32 mc_filter[2];
+       struct dev_mc_list *mclist;
+       void *tmp;
+
+       if (flags & IFF_PROMISC) {
+               priv->nar |= ADM8211_NAR_PR;
+               priv->nar &= ~ADM8211_NAR_MM;
+               mc_filter[1] = mc_filter[0] = ~0;
+       } else if ((flags & IFF_ALLMULTI) || (mc_count > -1)) {
+               priv->nar &= ~ADM8211_NAR_PR;
+               priv->nar |= ADM8211_NAR_MM;
+               mc_filter[1] = mc_filter[0] = ~0;
+       } else {
+               priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
+               mc_filter[1] = mc_filter[0] = 0;
+               mclist = NULL;
+               while ((mclist = ieee80211_get_mc_list_item(dev, mclist, &tmp))) {
+                       bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
+
+                       bit_nr &= 0x3F;
+                       mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
+               }
+       }
+
+       ADM8211_IDLE_RX();
+
+       ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
+       ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
+       ADM8211_CSR_READ(NAR);
+
+       if (flags & IFF_PROMISC)
+               dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
+       else
+               dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
+
+       ADM8211_RESTORE();
+}
+
+static int adm8211_get_tx_stats(struct ieee80211_hw *dev,
+                               struct ieee80211_tx_queue_stats *stats)
+{
+       struct adm8211_priv *priv = dev->priv;
+       struct ieee80211_tx_queue_stats_data *data = &stats->data[0];
+
+       data->len = priv->cur_tx - priv->dirty_tx;
+       data->limit = priv->tx_ring_size - 2;
+       data->count = priv->dirty_tx;
+
+       return 0;
+}
+
+static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
+{
+       struct adm8211_priv *priv = dev->priv;
+       unsigned int dirty_tx;
+
+       spin_lock(&priv->lock);
+
+       for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
+               unsigned int entry = dirty_tx % priv->tx_ring_size;
+               u32 status = le32_to_cpu(priv->tx_ring[entry].status);
+               struct adm8211_tx_ring_info *info;
+               struct sk_buff *skb;
+
+               if (status & TDES0_CONTROL_OWN ||
+                   !(status & TDES0_CONTROL_DONE))
+                       break;
+
+               info = &priv->tx_buffers[entry];
+               skb = info->skb;
+
+               /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
+
+               pci_unmap_single(priv->pdev, info->mapping,
+                                info->skb->len, PCI_DMA_TODEVICE);
+
+               if (info->tx_control.flags & IEEE80211_TXCTL_REQ_TX_STATUS) {
+                       struct ieee80211_tx_status tx_status = {{0}};
+                       struct ieee80211_hdr *hdr;
+                       size_t hdrlen = info->hdrlen;
+
+                       skb_pull(skb, sizeof(struct adm8211_tx_hdr));
+                       hdr = (struct ieee80211_hdr *)skb_push(skb, hdrlen);
+                       memcpy(hdr, skb->cb, hdrlen);
+                       memcpy(&tx_status.control, &info->tx_control,
+                              sizeof(tx_status.control));
+                       if (!(status & TDES0_STATUS_ES))
+                               tx_status.flags |= IEEE80211_TX_STATUS_ACK;
+                       ieee80211_tx_status_irqsafe(dev, skb, &tx_status);
+               } else
+                       dev_kfree_skb_irq(skb);
+               info->skb = NULL;
+       }
+
+       if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
+               ieee80211_wake_queue(dev, 0);
+
+       priv->dirty_tx = dirty_tx;
+       spin_unlock(&priv->lock);
+}
+
+
+static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
+{
+       struct adm8211_priv *priv = dev->priv;
+       unsigned int entry = priv->cur_rx % priv->rx_ring_size;
+       u32 status;
+       unsigned int pktlen;
+       struct sk_buff *skb, *newskb;
+       unsigned int limit = priv->rx_ring_size;
+       static const u8 rate_tbl[] = {10, 20, 55, 110, 220};
+       u8 rssi, rate;
+
+       while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
+               if (!limit--)
+                       break;
+
+               status = le32_to_cpu(priv->rx_ring[entry].status);
+               rate = (status & RDES0_STATUS_RXDR) >> 12;
+               rssi = le32_to_cpu(priv->rx_ring[entry].length) &
+                       RDES1_STATUS_RSSI;
+
+               pktlen = status & RDES0_STATUS_FL;
+               if (pktlen > RX_PKT_SIZE) {
+                       if (net_ratelimit())
+                               printk(KERN_DEBUG "%s: frame too long (%d)\n",
+                                      wiphy_name(dev->wiphy), pktlen);
+                       pktlen = RX_PKT_SIZE;
+               }
+
+               if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
+                       skb = NULL; /* old buffer will be reused */
+                       /* TODO: update RX error stats */
+                       /* TODO: check RDES0_STATUS_CRC*E */
+               } else if (pktlen < RX_COPY_BREAK) {
+                       skb = dev_alloc_skb(pktlen);
+                       if (skb) {
+                               pci_dma_sync_single_for_cpu(
+                                       priv->pdev,
+                                       priv->rx_buffers[entry].mapping,
+                                       pktlen, PCI_DMA_FROMDEVICE);
+                               memcpy(skb_put(skb, pktlen),
+                                      skb_tail_pointer(priv->rx_buffers[entry].skb),
+                                      pktlen);
+                               pci_dma_sync_single_for_device(
+                                       priv->pdev,
+                                       priv->rx_buffers[entry].mapping,
+                                       RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
+                       }
+               } else {
+                       newskb = dev_alloc_skb(RX_PKT_SIZE);
+                       if (newskb) {
+                               skb = priv->rx_buffers[entry].skb;
+                               skb_put(skb, pktlen);
+                               pci_unmap_single(
+                                       priv->pdev,
+                                       priv->rx_buffers[entry].mapping,
+                                       RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
+                               priv->rx_buffers[entry].skb = newskb;
+                               priv->rx_buffers[entry].mapping =
+                                       pci_map_single(priv->pdev,
+                                                      skb_tail_pointer(newskb),
+                                                      RX_PKT_SIZE,
+                                                      PCI_DMA_FROMDEVICE);
+                       } else {
+                               skb = NULL;
+                               /* TODO: update rx dropped stats */
+                       }
+
+                       priv->rx_ring[entry].buffer1 =
+                               cpu_to_le32(priv->rx_buffers[entry].mapping);
+               }
+
+               priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
+                                                         RDES0_STATUS_SQL);
+               priv->rx_ring[entry].length =
+                       cpu_to_le32(RX_PKT_SIZE |
+                                   (entry == priv->rx_ring_size - 1 ?
+                                    RDES1_CONTROL_RER : 0));
+
+               if (skb) {
+                       struct ieee80211_rx_status rx_status = {0};
+
+                       if (priv->revid < ADM8211_REV_CA)
+                               rx_status.ssi = rssi;
+                       else
+                               rx_status.ssi = 100 - rssi;
+
+                       if (rate <= 4)
+                               rx_status.rate = rate_tbl[rate];
+
+                       rx_status.channel = priv->channel;
+                       rx_status.freq = adm8211_channels[priv->channel - 1].freq;
+                       rx_status.phymode = MODE_IEEE80211B;
+
+                       ieee80211_rx_irqsafe(dev, skb, &rx_status);
+               }
+
+               entry = (++priv->cur_rx) % priv->rx_ring_size;
+       }
+
+       /* TODO: check LPC and update stats? */
+}
+
+
+static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
+{
+#define ADM8211_INT(x)                                                    \
+do {                                                                      \
+       if (unlikely(stsr & ADM8211_STSR_ ## x))                           \
+               printk(KERN_DEBUG "%s: " #x "\n", wiphy_name(dev->wiphy)); \
+} while (0)
+
+       struct ieee80211_hw *dev = dev_id;
+       struct adm8211_priv *priv = dev->priv;
+       unsigned int count = 0;
+       u32 stsr;
+
+       do {
+               stsr = ADM8211_CSR_READ(STSR);
+               ADM8211_CSR_WRITE(STSR, stsr);
+               if (stsr == 0xffffffff)
+                       return IRQ_HANDLED;
+
+               if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
+                       break;
+
+               if (stsr & ADM8211_STSR_RCI)
+                       adm8211_interrupt_rci(dev);
+               if (stsr & ADM8211_STSR_TCI)
+                       adm8211_interrupt_tci(dev);
+
+               /*ADM8211_INT(LinkOn);*/
+               /*ADM8211_INT(LinkOff);*/
+
+               ADM8211_INT(PCF);
+               ADM8211_INT(BCNTC);
+               ADM8211_INT(GPINT);
+               ADM8211_INT(ATIMTC);
+               ADM8211_INT(TSFTF);
+               ADM8211_INT(TSCZ);
+               ADM8211_INT(SQL);
+               ADM8211_INT(WEPTD);
+               ADM8211_INT(ATIME);
+               /*ADM8211_INT(TBTT);*/
+               ADM8211_INT(TEIS);
+               ADM8211_INT(FBE);
+               ADM8211_INT(REIS);
+               ADM8211_INT(GPTT);
+               ADM8211_INT(RPS);
+               ADM8211_INT(RDU);
+               ADM8211_INT(TUF);
+               /*ADM8211_INT(TRT);*/
+               /*ADM8211_INT(TLT);*/
+               /*ADM8211_INT(TDU);*/
+               ADM8211_INT(TPS);
+
+       } while (count++ < 20);
+
+       return IRQ_RETVAL(count);
+
+#undef ADM8211_INT
+}
+
+#define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
+static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev,        \
+                                          u16 addr, u32 value) {            \
+       struct adm8211_priv *priv = dev->priv;                               \
+       unsigned int i;                                                      \
+       u32 reg, bitbuf;                                                     \
+                                                                            \
+       value &= v_mask;                                                     \
+       addr &= a_mask;                                                      \
+       bitbuf = (value << v_shift) | (addr << a_shift);                     \
+                                                                            \
+       ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1);                 \
+       ADM8211_CSR_READ(SYNRF);                                             \
+       ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0);                 \
+       ADM8211_CSR_READ(SYNRF);                                             \
+                                                                            \
+       if (prewrite) {                                                      \
+               ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0);     \
+               ADM8211_CSR_READ(SYNRF);                                     \
+       }                                                                    \
+                                                                            \
+       for (i = 0; i <= bits; i++) {                                        \
+               if (bitbuf & (1 << (bits - i)))                              \
+                       reg = ADM8211_SYNRF_WRITE_SYNDATA_1;                 \
+               else                                                         \
+                       reg = ADM8211_SYNRF_WRITE_SYNDATA_0;                 \
+                                                                            \
+               ADM8211_CSR_WRITE(SYNRF, reg);                               \
+               ADM8211_CSR_READ(SYNRF);                                     \
+                                                                            \
+               ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
+               ADM8211_CSR_READ(SYNRF);                                     \
+               ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
+               ADM8211_CSR_READ(SYNRF);                                     \
+       }                                                                    \
+                                                                            \
+       if (postwrite == 1) {                                                \
+               ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0);   \
+               ADM8211_CSR_READ(SYNRF);                                     \
+       }                                                                    \
+       if (postwrite == 2) {                                                \
+               ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1);   \
+               ADM8211_CSR_READ(SYNRF);                                     \
+       }                                                                    \
+                                                                            \
+       ADM8211_CSR_WRITE(SYNRF, 0);                                         \
+       ADM8211_CSR_READ(SYNRF);                                             \
+}
+
+WRITE_SYN(max2820,  0x00FFF, 0, 0x0F, 12, 15, 1, 1)
+WRITE_SYN(al2210l,  0xFFFFF, 4, 0x0F,  0, 23, 1, 1)
+WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
+WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F,  0, 21, 0, 2)
+
+#undef WRITE_SYN
+
+static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
+{
+       struct adm8211_priv *priv = dev->priv;
+       unsigned int timeout;
+       u32 reg;
+
+       timeout = 10;
+       while (timeout > 0) {
+               reg = ADM8211_CSR_READ(BBPCTL);
+               if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
+                       break;
+               timeout--;
+               msleep(2);
+       }
+
+       if (timeout == 0) {
+               printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
+                      " prewrite (reg=0x%08x)\n",
+                      wiphy_name(dev->wiphy), addr, data, reg);
+               return -ETIMEDOUT;
+       }
+
+       switch (priv->bbp_type) {
+       case ADM8211_TYPE_INTERSIL:
+               reg = ADM8211_BBPCTL_MMISEL;    /* three wire interface */
+               break;
+       case ADM8211_TYPE_RFMD:
+               reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
+                     (0x01 << 18);
+               break;
+       case ADM8211_TYPE_ADMTEK:
+               reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
+                     (0x05 << 18);
+               break;
+       }
+       reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
+
+       ADM8211_CSR_WRITE(BBPCTL, reg);
+
+       timeout = 10;
+       while (timeout > 0) {
+               reg = ADM8211_CSR_READ(BBPCTL);
+               if (!(reg & ADM8211_BBPCTL_WR))
+                       break;
+               timeout--;
+               msleep(2);
+       }
+
+       if (timeout == 0) {
+               ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
+                                 ~ADM8211_BBPCTL_WR);
+               printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
+                      " postwrite (reg=0x%08x)\n",
+                      wiphy_name(dev->wiphy), addr, data, reg);
+               return -ETIMEDOUT;
+       }
+
+       return 0;
+}
+
+static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
+{
+       static const u32 adm8211_rfmd2958_reg5[] =
+               {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
+                0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
+       static const u32 adm8211_rfmd2958_reg6[] =
+               {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
+                0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
+
+       struct adm8211_priv *priv = dev->priv;
+       u8 ant_power = priv->ant_power > 0x3F ?
+               priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
+       u8 tx_power = priv->tx_power > 0x3F ?
+               priv->eeprom->tx_power[chan - 1] : priv->tx_power;
+       u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
+               priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
+       u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
+               priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
+       u32 reg;
+
+       ADM8211_IDLE();
+
+       /* Program synthesizer to new channel */
+       switch (priv->transceiver_type) {
+       case ADM8211_RFMD2958:
+       case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
+               adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
+               adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
+
+               adm8211_rf_write_syn_rfmd2958(dev, 0x05,
+                       adm8211_rfmd2958_reg5[chan - 1]);
+               adm8211_rf_write_syn_rfmd2958(dev, 0x06,
+                       adm8211_rfmd2958_reg6[chan - 1]);
+               break;
+
+       case ADM8211_RFMD2948:
+               adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
+                                             SI4126_MAIN_XINDIV2);
+               adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
+                                             SI4126_POWERDOWN_PDIB |
+                                             SI4126_POWERDOWN_PDRB);
+               adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
+               adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
+                                             (chan == 14 ?
+                                              2110 : (2033 + (chan * 5))));
+               adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
+               adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
+               adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
+               break;
+
+       case ADM8211_MAX2820:
+               adm8211_rf_write_syn_max2820(dev, 0x3,
+                       (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
+               break;
+
+       case ADM8211_AL2210L:
+               adm8211_rf_write_syn_al2210l(dev, 0x0,
+                       (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
+               break;
+
+       default:
+               printk(KERN_DEBUG "%s: unsupported transceiver type %d\n",
+                      wiphy_name(dev->wiphy), priv->transceiver_type);
+               break;
+       }
+
+       /* write BBP regs */
+       if (priv->bbp_type == ADM8211_TYPE_RFMD) {
+
+       /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
+       /* TODO: remove if SMC 2635W doesn't need this */
+       if (priv->transceiver_type == ADM8211_RFMD2948) {
+               reg = ADM8211_CSR_READ(GPIO);
+               reg &= 0xfffc0000;
+               reg |= ADM8211_CSR_GPIO_EN0;
+               if (chan != 14)
+                       reg |= ADM8211_CSR_GPIO_O0;
+               ADM8211_CSR_WRITE(GPIO, reg);
+       }
+
+       if (priv->transceiver_type == ADM8211_RFMD2958) {
+               /* set PCNT2 */
+               adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
+               /* set PCNT1 P_DESIRED/MID_BIAS */
+               reg = le16_to_cpu(priv->eeprom->cr49);
+               reg >>= 13;
+               reg <<= 15;
+               reg |= ant_power << 9;
+               adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
+               /* set TXRX TX_GAIN */
+               adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
+                       (priv->revid < ADM8211_REV_CA ? tx_power : 0));
+       } else {
+               reg = ADM8211_CSR_READ(PLCPHD);
+               reg &= 0xff00ffff;
+               reg |= tx_power << 18;
+               ADM8211_CSR_WRITE(PLCPHD, reg);
+       }
+
+       ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
+                         ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
+       ADM8211_CSR_READ(SYNRF);
+       msleep(30);
+
+       /* RF3000 BBP */
+       if (priv->transceiver_type != ADM8211_RFMD2958)
+               adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
+                                 tx_power<<2);
+       adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
+       adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
+       adm8211_write_bbp(dev, 0x1c, priv->revid == ADM8211_REV_BA ?
+                                    priv->eeprom->cr28 : 0);
+       adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
+
+       ADM8211_CSR_WRITE(SYNRF, 0);
+
+       /* Nothing to do for ADMtek BBP */
+       } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
+               printk(KERN_DEBUG "%s: unsupported BBP type %d\n",
+                      wiphy_name(dev->wiphy), priv->bbp_type);
+
+       ADM8211_RESTORE();
+
+       /* update current channel for adhoc (and maybe AP mode) */
+       reg = ADM8211_CSR_READ(CAP0);
+       reg &= ~0xF;
+       reg |= chan;
+       ADM8211_CSR_WRITE(CAP0, reg);
+
+       return 0;
+}
+
+static void adm8211_update_mode(struct ieee80211_hw *dev)
+{
+       struct adm8211_priv *priv = dev->priv;
+
+       ADM8211_IDLE();
+
+       priv->soft_rx_crc = 0;
+       switch (priv->mode) {
+       case IEEE80211_IF_TYPE_STA:
+               priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
+               priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
+               break;
+       case IEEE80211_IF_TYPE_IBSS:
+               priv->nar &= ~ADM8211_NAR_PR;
+               priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
+
+               /* don't trust the error bits on rev 0x20 and up in adhoc */
+               if (priv->revid >= ADM8211_REV_BA)
+                       priv->soft_rx_crc = 1;
+               break;
+       case IEEE80211_IF_TYPE_MNTR:
+               priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
+               priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
+               break;
+       }
+
+       ADM8211_RESTORE();
+}
+
+static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
+{
+       struct adm8211_priv *priv = dev->priv;
+
+       switch (priv->transceiver_type) {
+       case ADM8211_RFMD2958:
+       case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
+               /* comments taken from ADMtek vendor driver */
+
+               /* Reset RF2958 after power on */
+               adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
+               /* Initialize RF VCO Core Bias to maximum */
+               adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
+               /* Initialize IF PLL */
+               adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
+               /* Initialize IF PLL Coarse Tuning */
+               adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
+               /* Initialize RF PLL */
+               adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
+               /* Initialize RF PLL Coarse Tuning */
+               adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
+               /* Initialize TX gain and filter BW (R9) */
+               adm8211_rf_write_syn_rfmd2958(dev, 0x09,
+                       (priv->transceiver_type == ADM8211_RFMD2958 ?
+                        0x10050 : 0x00050));
+               /* Initialize CAL register */
+               adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
+               break;
+
+       case ADM8211_MAX2820:
+               adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
+               adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
+               adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
+               adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
+               adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
+               break;
+
+       case ADM8211_AL2210L:
+               adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
+               adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
+               adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
+               adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
+               adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
+               adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
+               adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
+               adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
+               adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
+               adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
+               adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
+               adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
+               break;
+
+       case ADM8211_RFMD2948:
+       default:
+               break;
+       }
+}
+
+static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
+{
+       struct adm8211_priv *priv = dev->priv;
+       u32 reg;
+
+       /* write addresses */
+       if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
+               ADM8211_CSR_WRITE(MMIWA,  0x100E0C0A);
+               ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
+               ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
+       } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
+                  priv->bbp_type == ADM8211_TYPE_ADMTEK) {
+               /* check specific BBP type */
+               switch (priv->specific_bbptype) {
+               case ADM8211_BBP_RFMD3000:
+               case ADM8211_BBP_RFMD3002:
+                       ADM8211_CSR_WRITE(MMIWA,  0x00009101);
+                       ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
+                       break;
+
+               case ADM8211_BBP_ADM8011:
+                       ADM8211_CSR_WRITE(MMIWA,  0x00008903);
+                       ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
+
+                       reg = ADM8211_CSR_READ(BBPCTL);
+                       reg &= ~ADM8211_BBPCTL_TYPE;
+                       reg |= 0x5 << 18;
+                       ADM8211_CSR_WRITE(BBPCTL, reg);
+                       break;
+               }
+
+               switch (priv->revid) {
+               case ADM8211_REV_CA:
+                       if (priv->transceiver_type == ADM8211_RFMD2958 ||
+                           priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
+                           priv->transceiver_type == ADM8211_RFMD2948)
+                               ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
+                       else if (priv->transceiver_type == ADM8211_MAX2820 ||
+                                priv->transceiver_type == ADM8211_AL2210L)
+                               ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
+                       break;
+
+               case ADM8211_REV_BA:
+                       reg  = ADM8211_CSR_READ(MMIRD1);
+                       reg &= 0x0000FFFF;
+                       reg |= 0x7e100000;
+                       ADM8211_CSR_WRITE(MMIRD1, reg);
+                       break;
+
+               case ADM8211_REV_AB:
+               case ADM8211_REV_AF:
+               default:
+                       ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
+                       break;
+               }
+
+               /* For RFMD */
+               ADM8211_CSR_WRITE(MACTEST, 0x800);
+       }
+
+       adm8211_hw_init_syn(dev);
+
+       /* Set RF Power control IF pin to PE1+PHYRST# */
+       ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
+                         ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
+       ADM8211_CSR_READ(SYNRF);
+       msleep(20);
+
+       /* write BBP regs */
+       if (priv->bbp_type == ADM8211_TYPE_RFMD) {
+               /* RF3000 BBP */
+               /* another set:
+                * 11: c8
+                * 14: 14
+                * 15: 50 (chan 1..13; chan 14: d0)
+                * 1c: 00
+                * 1d: 84
+                */
+               adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
+               /* antenna selection: diversity */
+               adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
+               adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
+               adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
+               adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
+
+               if (priv->eeprom->major_version < 2) {
+                       adm8211_write_bbp(dev, 0x1c, 0x00);
+                       adm8211_write_bbp(dev, 0x1d, 0x80);
+               } else {
+                       if (priv->revid == ADM8211_REV_BA)
+                               adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
+                       else
+                               adm8211_write_bbp(dev, 0x1c, 0x00);
+
+                       adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
+               }
+       } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
+               /* reset baseband */
+               adm8211_write_bbp(dev, 0x00, 0xFF);
+               /* antenna selection: diversity */
+               adm8211_write_bbp(dev, 0x07, 0x0A);
+
+               /* TODO: find documentation for this */
+               switch (priv->transceiver_type) {
+               case ADM8211_RFMD2958:
+               case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
+                       adm8211_write_bbp(dev, 0x00, 0x00);
+                       adm8211_write_bbp(dev, 0x01, 0x00);
+                       adm8211_write_bbp(dev, 0x02, 0x00);
+                       adm8211_write_bbp(dev, 0x03, 0x00);
+                       adm8211_write_bbp(dev, 0x06, 0x0f);
+                       adm8211_write_bbp(dev, 0x09, 0x00);
+                       adm8211_write_bbp(dev, 0x0a, 0x00);
+                       adm8211_write_bbp(dev, 0x0b, 0x00);
+                       adm8211_write_bbp(dev, 0x0c, 0x00);
+                       adm8211_write_bbp(dev, 0x0f, 0xAA);
+                       adm8211_write_bbp(dev, 0x10, 0x8c);
+                       adm8211_write_bbp(dev, 0x11, 0x43);
+                       adm8211_write_bbp(dev, 0x18, 0x40);
+                       adm8211_write_bbp(dev, 0x20, 0x23);
+                       adm8211_write_bbp(dev, 0x21, 0x02);
+                       adm8211_write_bbp(dev, 0x22, 0x28);
+                       adm8211_write_bbp(dev, 0x23, 0x30);
+                       adm8211_write_bbp(dev, 0x24, 0x2d);
+                       adm8211_write_bbp(dev, 0x28, 0x35);
+                       adm8211_write_bbp(dev, 0x2a, 0x8c);
+                       adm8211_write_bbp(dev, 0x2b, 0x81);
+                       adm8211_write_bbp(dev, 0x2c, 0x44);
+                       adm8211_write_bbp(dev, 0x2d, 0x0A);
+                       adm8211_write_bbp(dev, 0x29, 0x40);
+                       adm8211_write_bbp(dev, 0x60, 0x08);
+                       adm8211_write_bbp(dev, 0x64, 0x01);
+                       break;
+
+               case ADM8211_MAX2820:
+                       adm8211_write_bbp(dev, 0x00, 0x00);
+                       adm8211_write_bbp(dev, 0x01, 0x00);
+                       adm8211_write_bbp(dev, 0x02, 0x00);
+                       adm8211_write_bbp(dev, 0x03, 0x00);
+                       adm8211_write_bbp(dev, 0x06, 0x0f);
+                       adm8211_write_bbp(dev, 0x09, 0x05);
+                       adm8211_write_bbp(dev, 0x0a, 0x02);
+                       adm8211_write_bbp(dev, 0x0b, 0x00);
+                       adm8211_write_bbp(dev, 0x0c, 0x0f);
+                       adm8211_write_bbp(dev, 0x0f, 0x55);
+                       adm8211_write_bbp(dev, 0x10, 0x8d);
+                       adm8211_write_bbp(dev, 0x11, 0x43);
+                       adm8211_write_bbp(dev, 0x18, 0x4a);
+                       adm8211_write_bbp(dev, 0x20, 0x20);
+                       adm8211_write_bbp(dev, 0x21, 0x02);
+                       adm8211_write_bbp(dev, 0x22, 0x23);
+                       adm8211_write_bbp(dev, 0x23, 0x30);
+                       adm8211_write_bbp(dev, 0x24, 0x2d);
+                       adm8211_write_bbp(dev, 0x2a, 0x8c);
+                       adm8211_write_bbp(dev, 0x2b, 0x81);
+                       adm8211_write_bbp(dev, 0x2c, 0x44);
+                       adm8211_write_bbp(dev, 0x29, 0x4a);
+                       adm8211_write_bbp(dev, 0x60, 0x2b);
+                       adm8211_write_bbp(dev, 0x64, 0x01);
+                       break;
+
+               case ADM8211_AL2210L:
+                       adm8211_write_bbp(dev, 0x00, 0x00);
+                       adm8211_write_bbp(dev, 0x01, 0x00);
+                       adm8211_write_bbp(dev, 0x02, 0x00);
+                       adm8211_write_bbp(dev, 0x03, 0x00);
+                       adm8211_write_bbp(dev, 0x06, 0x0f);
+                       adm8211_write_bbp(dev, 0x07, 0x05);
+                       adm8211_write_bbp(dev, 0x08, 0x03);
+                       adm8211_write_bbp(dev, 0x09, 0x00);
+                       adm8211_write_bbp(dev, 0x0a, 0x00);
+                       adm8211_write_bbp(dev, 0x0b, 0x00);
+                       adm8211_write_bbp(dev, 0x0c, 0x10);
+                       adm8211_write_bbp(dev, 0x0f, 0x55);
+                       adm8211_write_bbp(dev, 0x10, 0x8d);
+                       adm8211_write_bbp(dev, 0x11, 0x43);
+                       adm8211_write_bbp(dev, 0x18, 0x4a);
+                       adm8211_write_bbp(dev, 0x20, 0x20);
+                       adm8211_write_bbp(dev, 0x21, 0x02);
+                       adm8211_write_bbp(dev, 0x22, 0x23);
+                       adm8211_write_bbp(dev, 0x23, 0x30);
+                       adm8211_write_bbp(dev, 0x24, 0x2d);
+                       adm8211_write_bbp(dev, 0x2a, 0xaa);
+                       adm8211_write_bbp(dev, 0x2b, 0x81);
+                       adm8211_write_bbp(dev, 0x2c, 0x44);
+                       adm8211_write_bbp(dev, 0x29, 0xfa);
+                       adm8211_write_bbp(dev, 0x60, 0x2d);
+                       adm8211_write_bbp(dev, 0x64, 0x01);
+                       break;
+
+               case ADM8211_RFMD2948:
+                       break;
+
+               default:
+                       printk(KERN_DEBUG "%s: unsupported transceiver %d\n",
+                              wiphy_name(dev->wiphy), priv->transceiver_type);
+                       break;
+               }
+       } else
+               printk(KERN_DEBUG "%s: unsupported BBP %d\n",
+                      wiphy_name(dev->wiphy), priv->bbp_type);
+
+       ADM8211_CSR_WRITE(SYNRF, 0);
+
+       /* Set RF CAL control source to MAC control */
+       reg = ADM8211_CSR_READ(SYNCTL);
+       reg |= ADM8211_SYNCTL_SELCAL;
+       ADM8211_CSR_WRITE(SYNCTL, reg);
+
+       return 0;
+}
+
+/* configures hw beacons/probe responses */
+static int adm8211_set_rate(struct ieee80211_hw *dev)
+{
+       struct adm8211_priv *priv = dev->priv;
+       u32 reg;
+       int i = 0;
+       u8 rate_buf[12] = {0};
+
+       /* write supported rates */
+       if (priv->revid != ADM8211_REV_BA) {
+               rate_buf[0] = ARRAY_SIZE(adm8211_rates);
+               for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
+                       rate_buf[i + 1] = (adm8211_rates[i].rate / 5) | 0x80;
+       } else {
+               /* workaround for rev BA specific bug */
+               rate_buf[0] = 0x04;
+               rate_buf[1] = 0x82;
+               rate_buf[2] = 0x04;
+               rate_buf[3] = 0x0b;
+               rate_buf[4] = 0x16;
+       }
+
+       adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
+                                ARRAY_SIZE(adm8211_rates) + 1);
+
+       reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
+       reg |= 1 << 15; /* short preamble */
+       reg |= 110 << 24;
+       ADM8211_CSR_WRITE(PLCPHD, reg);
+
+       /* MTMLT   = 512 TU (max TX MSDU lifetime)
+        * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
+        * SRTYLIM = 224 (short retry limit, TX header value is default) */
+       ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
+
+       return 0;
+}
+
+static void adm8211_hw_init(struct ieee80211_hw *dev)
+{
+       struct adm8211_priv *priv = dev->priv;
+       u32 reg;
+       u8 cline;
+
+       reg = le32_to_cpu(ADM8211_CSR_READ(PAR));
+       reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
+       reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
+
+       if (!pci_set_mwi(priv->pdev)) {
+               reg |= 0x1 << 24;
+               pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
+
+               switch (cline) {
+               case  0x8: reg |= (0x1 << 14);
+                          break;
+               case 0x16: reg |= (0x2 << 14);
+                          break;
+               case 0x32: reg |= (0x3 << 14);
+                          break;
+                 default: reg |= (0x0 << 14);
+                          break;
+               }
+       }
+
+       ADM8211_CSR_WRITE(PAR, reg);
+
+       reg = ADM8211_CSR_READ(CSR_TEST1);
+       reg &= ~(0xF << 28);
+       reg |= (1 << 28) | (1 << 31);
+       ADM8211_CSR_WRITE(CSR_TEST1, reg);
+
+       /* lose link after 4 lost beacons */
+       reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
+       ADM8211_CSR_WRITE(WCSR, reg);
+
+       /* Disable APM, enable receive FIFO threshold, and set drain receive
+        * threshold to store-and-forward */
+       reg = ADM8211_CSR_READ(CMDR);
+       reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
+       reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
+       ADM8211_CSR_WRITE(CMDR, reg);
+
+       adm8211_set_rate(dev);
+
+       /* 4-bit values:
+        * PWR1UP   = 8 * 2 ms
+        * PWR0PAPE = 8 us or 5 us
+        * PWR1PAPE = 1 us or 3 us
+        * PWR0TRSW = 5 us
+        * PWR1TRSW = 12 us
+        * PWR0PE2  = 13 us
+        * PWR1PE2  = 1 us
+        * PWR0TXPE = 8 or 6 */
+       if (priv->revid < ADM8211_REV_CA)
+               ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
+       else
+               ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
+
+       /* Enable store and forward for transmit */
+       priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
+       ADM8211_CSR_WRITE(NAR, priv->nar);
+
+       /* Reset RF */
+       ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
+       ADM8211_CSR_READ(SYNRF);
+       msleep(10);
+       ADM8211_CSR_WRITE(SYNRF, 0);
+       ADM8211_CSR_READ(SYNRF);
+       msleep(5);
+
+       /* Set CFP Max Duration to 0x10 TU */
+       reg = ADM8211_CSR_READ(CFPP);
+       reg &= ~(0xffff << 8);
+       reg |= 0x0010 << 8;
+       ADM8211_CSR_WRITE(CFPP, reg);
+
+       /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
+        * TUCNT = 0x3ff - Tu counter 1024 us  */
+       ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
+
+       /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
+        * DIFS=50 us, EIFS=100 us */
+       if (priv->revid < ADM8211_REV_CA)
+               ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
+                                       (50 << 9)  | 100);
+       else
+               ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
+                                       (50 << 9)  | 100);
+
+       /* PCNT = 1 (MAC idle time awake/sleep, unit S)
+        * RMRD = 2346 * 8 + 1 us (max RX duration)  */
+       ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
+
+       /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
+       ADM8211_CSR_WRITE(RSPT, 0xffffff00);
+
+       /* Initialize BBP (and SYN) */
+       adm8211_hw_init_bbp(dev);
+
+       /* make sure interrupts are off */
+       ADM8211_CSR_WRITE(IER, 0);
+
+       /* ACK interrupts */
+       ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
+
+       /* Setup WEP (turns it off for now) */
+       reg = ADM8211_CSR_READ(MACTEST);
+       reg &= ~(7 << 20);
+       ADM8211_CSR_WRITE(MACTEST, reg);
+
+       reg = ADM8211_CSR_READ(WEPCTL);
+       reg &= ~ADM8211_WEPCTL_WEPENABLE;
+       reg |= ADM8211_WEPCTL_WEPRXBYP;
+       ADM8211_CSR_WRITE(WEPCTL, reg);
+
+       /* Clear the missed-packet counter. */
+       ADM8211_CSR_READ(LPC);
+
+       if (!priv->mac_addr)
+               return;
+
+       /* set mac address */
+       ADM8211_CSR_WRITE(PAR0, *(u32 *)priv->mac_addr);
+       ADM8211_CSR_WRITE(PAR1, *(u16 *)&priv->mac_addr[4]);
+}
+
+static int adm8211_hw_reset(struct ieee80211_hw *dev)
+{
+       struct adm8211_priv *priv = dev->priv;
+       u32 reg, tmp;
+       int timeout = 100;
+
+       /* Power-on issue */
+       /* TODO: check if this is necessary */
+       ADM8211_CSR_WRITE(FRCTL, 0);
+
+       /* Reset the chip */
+       tmp = ADM8211_CSR_READ(PAR);
+       ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
+
+       while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
+               msleep(50);
+
+       if (timeout <= 0)
+               return -ETIMEDOUT;
+
+       ADM8211_CSR_WRITE(PAR, tmp);
+
+       if (priv->revid == ADM8211_REV_BA &&
+           (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
+            priv->transceiver_type == ADM8211_RFMD2958)) {
+               reg = ADM8211_CSR_READ(CSR_TEST1);
+               reg |= (1 << 4) | (1 << 5);
+               ADM8211_CSR_WRITE(CSR_TEST1, reg);
+       } else if (priv->revid == ADM8211_REV_CA) {
+               reg = ADM8211_CSR_READ(CSR_TEST1);
+               reg &= ~((1 << 4) | (1 << 5));
+               ADM8211_CSR_WRITE(CSR_TEST1, reg);
+       }
+
+       ADM8211_CSR_WRITE(FRCTL, 0);
+
+       reg = ADM8211_CSR_READ(CSR_TEST0);
+       reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
+       ADM8211_CSR_WRITE(CSR_TEST0, reg);
+
+       adm8211_clear_sram(dev);
+
+       return 0;
+}
+
+static u64 adm8211_get_tsft(struct ieee80211_hw *dev)
+{
+       struct adm8211_priv *priv = dev->priv;
+       u32 tsftl;
+       u64 tsft;
+
+       tsftl = ADM8211_CSR_READ(TSFTL);
+       tsft = ADM8211_CSR_READ(TSFTH);
+       tsft <<= 32;
+       tsft |= tsftl;
+
+       return tsft;
+}
+
+static void adm8211_set_interval(struct ieee80211_hw *dev,
+                                unsigned short bi, unsigned short li)
+{
+       struct adm8211_priv *priv = dev->priv;
+       u32 reg;
+
+       /* BP (beacon interval) = data->beacon_interval
+        * LI (listen interval) = data->listen_interval (in beacon intervals) */
+       reg = (bi << 16) | li;
+       ADM8211_CSR_WRITE(BPLI, reg);
+}
+
+static void adm8211_set_bssid(struct ieee80211_hw *dev, u8 *bssid)
+{
+       struct adm8211_priv *priv = dev->priv;
+       u32 reg;
+
+       reg = bssid[0] | (bssid[1] << 8) | (bssid[2] << 16) | (bssid[3] << 24);
+       ADM8211_CSR_WRITE(BSSID0, reg);
+       reg = ADM8211_CSR_READ(ABDA1);
+       reg &= 0x0000ffff;
+       reg |= (bssid[4] << 16) | (bssid[5] << 24);
+       ADM8211_CSR_WRITE(ABDA1, reg);
+}
+
+static int adm8211_set_ssid(struct ieee80211_hw *dev, u8 *ssid, size_t ssid_len)
+{
+       struct adm8211_priv *priv = dev->priv;
+       u8 buf[36];
+
+       if (ssid_len > 32)
+               return -EINVAL;
+
+       memset(buf, 0, sizeof(buf));
+       buf[0] = ssid_len;
+       memcpy(buf + 1, ssid, ssid_len);
+       adm8211_write_sram_bytes(dev, ADM8211_SRAM_SSID, buf, 33);
+       /* TODO: configure beacon for adhoc? */
+       return 0;
+}
+
+static int adm8211_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
+{
+       struct adm8211_priv *priv = dev->priv;
+
+       if (conf->channel != priv->channel) {
+               priv->channel = conf->channel;
+               adm8211_rf_set_channel(dev, priv->channel);
+       }
+
+       return 0;
+}
+
+static int adm8211_config_interface(struct ieee80211_hw *dev, int if_id,
+                                   struct ieee80211_if_conf *conf)
+{
+       struct adm8211_priv *priv = dev->priv;
+
+       if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
+               adm8211_set_bssid(dev, conf->bssid);
+               memcpy(priv->bssid, conf->bssid, ETH_ALEN);
+       }
+
+       if (conf->ssid_len != priv->ssid_len ||
+           memcmp(conf->ssid, priv->ssid, conf->ssid_len)) {
+               adm8211_set_ssid(dev, conf->ssid, conf->ssid_len);
+               priv->ssid_len = conf->ssid_len;
+               memcpy(priv->ssid, conf->ssid, conf->ssid_len);
+       }
+
+       return 0;
+}
+
+static int adm8211_add_interface(struct ieee80211_hw *dev,
+                                struct ieee80211_if_init_conf *conf)
+{
+       struct adm8211_priv *priv = dev->priv;
+       /* NOTE: using IEEE80211_IF_TYPE_MGMT to indicate no mode selected */
+       if (priv->mode != IEEE80211_IF_TYPE_MGMT)
+               return -1;
+
+       switch (conf->type) {
+       case IEEE80211_IF_TYPE_STA:
+       case IEEE80211_IF_TYPE_MNTR:
+               priv->mode = conf->type;
+               break;
+       default:
+               return -EOPNOTSUPP;
+       }
+
+       priv->mac_addr = conf->mac_addr;
+
+       return 0;
+}
+
+static void adm8211_remove_interface(struct ieee80211_hw *dev,
+                                    struct ieee80211_if_init_conf *conf)
+{
+       struct adm8211_priv *priv = dev->priv;
+       priv->mode = IEEE80211_IF_TYPE_MGMT;
+}
+
+static int adm8211_init_rings(struct ieee80211_hw *dev)
+{
+       struct adm8211_priv *priv = dev->priv;
+       struct adm8211_desc *desc = NULL;
+       struct adm8211_rx_ring_info *rx_info;
+       struct adm8211_tx_ring_info *tx_info;
+       unsigned int i;
+
+       for (i = 0; i < priv->rx_ring_size; i++) {
+               desc = &priv->rx_ring[i];
+               desc->status = 0;
+               desc->length = cpu_to_le32(RX_PKT_SIZE);
+               priv->rx_buffers[i].skb = NULL;
+       }
+       /* Mark the end of RX ring; hw returns to base address after this
+        * descriptor */
+       desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
+
+       for (i = 0; i < priv->rx_ring_size; i++) {
+               desc = &priv->rx_ring[i];
+               rx_info = &priv->rx_buffers[i];
+
+               rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
+               if (rx_info->skb == NULL)
+                       break;
+               rx_info->mapping = pci_map_single(priv->pdev,
+                                                 skb_tail_pointer(rx_info->skb),
+                                                 RX_PKT_SIZE,
+                                                 PCI_DMA_FROMDEVICE);
+               desc->buffer1 = cpu_to_le32(rx_info->mapping);
+               desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
+       }
+
+       /* Setup TX ring. TX buffers descriptors will be filled in as needed */
+       for (i = 0; i < priv->tx_ring_size; i++) {
+               desc = &priv->tx_ring[i];
+               tx_info = &priv->tx_buffers[i];
+
+               tx_info->skb = NULL;
+               tx_info->mapping = 0;
+               desc->status = 0;
+       }
+       desc->length = cpu_to_le32(TDES1_CONTROL_TER);
+
+       priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
+       ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
+       ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
+
+       return 0;
+}
+
+static void adm8211_free_rings(struct ieee80211_hw *dev)
+{
+       struct adm8211_priv *priv = dev->priv;
+       unsigned int i;
+
+       for (i = 0; i < priv->rx_ring_size; i++) {
+               if (!priv->rx_buffers[i].skb)
+                       continue;
+
+               pci_unmap_single(
+                       priv->pdev,
+                       priv->rx_buffers[i].mapping,
+                       RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
+
+               dev_kfree_skb(priv->rx_buffers[i].skb);
+       }
+
+       for (i = 0; i < priv->tx_ring_size; i++) {
+               if (!priv->tx_buffers[i].skb)
+                       continue;
+
+               pci_unmap_single(priv->pdev,
+                                priv->tx_buffers[i].mapping,
+                                priv->tx_buffers[i].skb->len,
+                                PCI_DMA_TODEVICE);
+
+               dev_kfree_skb(priv->tx_buffers[i].skb);
+       }
+}
+
+static int adm8211_open(struct ieee80211_hw *dev)
+{
+       struct adm8211_priv *priv = dev->priv;
+       int retval;
+
+       /* Power up MAC and RF chips */
+       retval = adm8211_hw_reset(dev);
+       if (retval) {
+               printk(KERN_ERR "%s: hardware reset failed\n",
+                      wiphy_name(dev->wiphy));
+               goto fail;
+       }
+
+       retval = adm8211_init_rings(dev);
+       if (retval) {
+               printk(KERN_ERR "%s: failed to initialize rings\n",
+                      wiphy_name(dev->wiphy));
+               goto fail;
+       }
+
+       /* Init hardware */
+       adm8211_hw_init(dev);
+       adm8211_rf_set_channel(dev, priv->channel);
+
+       retval = request_irq(priv->pdev->irq, &adm8211_interrupt,
+                            IRQF_SHARED, "adm8211", dev);
+       if (retval) {
+               printk(KERN_ERR "%s: failed to register IRQ handler\n",
+                      wiphy_name(dev->wiphy));
+               goto fail;
+       }
+
+       ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
+                              ADM8211_IER_RCIE | ADM8211_IER_TCIE |
+                              ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
+       adm8211_update_mode(dev);
+       ADM8211_CSR_WRITE(RDR, 0);
+
+       adm8211_set_interval(dev, 100, 10);
+       return 0;
+
+fail:
+       return retval;
+}
+
+static int adm8211_stop(struct ieee80211_hw *dev)
+{
+       struct adm8211_priv *priv = dev->priv;
+
+       priv->nar = 0;
+       ADM8211_CSR_WRITE(NAR, 0);
+       ADM8211_CSR_WRITE(IER, 0);
+       ADM8211_CSR_READ(NAR);
+
+       free_irq(priv->pdev->irq, dev);
+
+       adm8211_free_rings(dev);
+       return 0;
+}
+
+static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
+                                  int plcp_signal, int short_preamble)
+{
+       /* Alternative calculation from NetBSD: */
+
+/* IEEE 802.11b durations for DSSS PHY in microseconds */
+#define IEEE80211_DUR_DS_LONG_PREAMBLE 144
+#define IEEE80211_DUR_DS_SHORT_PREAMBLE        72
+#define IEEE80211_DUR_DS_FAST_PLCPHDR  24
+#define IEEE80211_DUR_DS_SLOW_PLCPHDR  48
+#define IEEE80211_DUR_DS_SLOW_ACK      112
+#define IEEE80211_DUR_DS_FAST_ACK      56
+#define IEEE80211_DUR_DS_SLOW_CTS      112
+#define IEEE80211_DUR_DS_FAST_CTS      56
+#define IEEE80211_DUR_DS_SLOT          20
+#define IEEE80211_DUR_DS_SIFS          10
+
+       int remainder;
+
+       *dur = (80 * (24 + payload_len) + plcp_signal - 1)
+               / plcp_signal;
+
+       if (plcp_signal <= PLCP_SIGNAL_2M)
+               /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
+               *dur += 3 * (IEEE80211_DUR_DS_SIFS +
+                            IEEE80211_DUR_DS_SHORT_PREAMBLE +
+                            IEEE80211_DUR_DS_FAST_PLCPHDR) +
+                            IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
+       else
+               /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
+               *dur += 3 * (IEEE80211_DUR_DS_SIFS +
+                            IEEE80211_DUR_DS_SHORT_PREAMBLE +
+                            IEEE80211_DUR_DS_FAST_PLCPHDR) +
+                            IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
+
+       /* lengthen duration if long preamble */
+       if (!short_preamble)
+               *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
+                            IEEE80211_DUR_DS_SHORT_PREAMBLE) +
+                       3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
+                            IEEE80211_DUR_DS_FAST_PLCPHDR);
+
+
+       *plcp = (80 * len) / plcp_signal;
+       remainder = (80 * len) % plcp_signal;
+       if (plcp_signal == PLCP_SIGNAL_11M &&
+           remainder <= 30 && remainder > 0)
+               *plcp = (*plcp | 0x8000) + 1;
+       else if (remainder)
+               (*plcp)++;
+}
+
+/* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
+static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
+                          u16 plcp_signal,
+                          struct ieee80211_tx_control *control,
+                          size_t hdrlen)
+{
+       struct adm8211_priv *priv = dev->priv;
+       unsigned long flags;
+       dma_addr_t mapping;
+       unsigned int entry;
+       u32 flag;
+
+       mapping = pci_map_single(priv->pdev, skb->data, skb->len,
+                                PCI_DMA_TODEVICE);
+
+       spin_lock_irqsave(&priv->lock, flags);
+
+       if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
+               flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
+       else
+               flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
+
+       if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
+               ieee80211_stop_queue(dev, 0);
+
+       entry = priv->cur_tx % priv->tx_ring_size;
+
+       priv->tx_buffers[entry].skb = skb;
+       priv->tx_buffers[entry].mapping = mapping;
+       memcpy(&priv->tx_buffers[entry].tx_control, control, sizeof(*control));
+       priv->tx_buffers[entry].hdrlen = hdrlen;
+       priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
+
+       if (entry == priv->tx_ring_size - 1)
+               flag |= TDES1_CONTROL_TER;
+       priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
+
+       /* Set TX rate (SIGNAL field in PLCP PPDU format) */
+       flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
+       priv->tx_ring[entry].status = cpu_to_le32(flag);
+
+       priv->cur_tx++;
+
+       spin_unlock_irqrestore(&priv->lock, flags);
+
+       /* Trigger transmit poll */
+       ADM8211_CSR_WRITE(TDR, 0);
+}
+
+/* Put adm8211_tx_hdr on skb and transmit */
+static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
+                     struct ieee80211_tx_control *control)
+{
+       struct adm8211_tx_hdr *txhdr;
+       u16 fc;
+       size_t payload_len, hdrlen;
+       int plcp, dur, len, plcp_signal, short_preamble;
+       struct ieee80211_hdr *hdr;
+
+       if (control->tx_rate < 0) {
+               short_preamble = 1;
+               plcp_signal = -control->tx_rate;
+       } else {
+               short_preamble = 0;
+               plcp_signal = control->tx_rate;
+       }
+
+       hdr = (struct ieee80211_hdr *)skb->data;
+       fc = le16_to_cpu(hdr->frame_control) & ~IEEE80211_FCTL_PROTECTED;
+       hdrlen = ieee80211_get_hdrlen(fc);
+       memcpy(skb->cb, skb->data, hdrlen);
+       hdr = (struct ieee80211_hdr *)skb->cb;
+       skb_pull(skb, hdrlen);
+       payload_len = skb->len;
+
+       txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
+       memset(txhdr, 0, sizeof(*txhdr));
+       memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
+       txhdr->signal = plcp_signal;
+       txhdr->frame_body_size = cpu_to_le16(payload_len);
+       txhdr->frame_control = hdr->frame_control;
+
+       len = hdrlen + payload_len + FCS_LEN;
+       if (fc & IEEE80211_FCTL_PROTECTED)
+               len += 8;
+
+       txhdr->frag = cpu_to_le16(0x0FFF);
+       adm8211_calc_durations(&dur, &plcp, payload_len,
+                              len, plcp_signal, short_preamble);
+       txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
+       txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
+       txhdr->dur_frag_head = cpu_to_le16(dur);
+       txhdr->dur_frag_tail = cpu_to_le16(dur);
+
+       txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
+
+       if (short_preamble)
+               txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
+
+       if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
+               txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
+
+       if (fc & IEEE80211_FCTL_PROTECTED)
+               txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE);
+
+       txhdr->retry_limit = control->retry_limit;
+
+       adm8211_tx_raw(dev, skb, plcp_signal, control, hdrlen);
+
+       return NETDEV_TX_OK;
+}
+
+static int adm8211_alloc_rings(struct ieee80211_hw *dev)
+{
+       struct adm8211_priv *priv = dev->priv;
+       unsigned int ring_size;
+
+       priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
+                                  sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
+       if (!priv->rx_buffers)
+               return -ENOMEM;
+
+       priv->tx_buffers = (void *)priv->rx_buffers +
+                          sizeof(*priv->rx_buffers) * priv->rx_ring_size;
+
+       /* Allocate TX/RX descriptors */
+       ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
+                   sizeof(struct adm8211_desc) * priv->tx_ring_size;
+       priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
+                                            &priv->rx_ring_dma);
+
+       if (!priv->rx_ring) {
+               kfree(priv->rx_buffers);
+               priv->rx_buffers = NULL;
+               priv->tx_buffers = NULL;
+               return -ENOMEM;
+       }
+
+       priv->tx_ring = (struct adm8211_desc *)(priv->rx_ring +
+                                               priv->rx_ring_size);
+       priv->tx_ring_dma = priv->rx_ring_dma +
+                           sizeof(struct adm8211_desc) * priv->rx_ring_size;
+
+       return 0;
+}
+
+static const struct ieee80211_ops adm8211_ops = {
+       .tx                     = adm8211_tx,
+       .open                   = adm8211_open,
+       .stop                   = adm8211_stop,
+       .add_interface          = adm8211_add_interface,
+       .remove_interface       = adm8211_remove_interface,
+       .config                 = adm8211_config,
+       .config_interface       = adm8211_config_interface,
+       .set_multicast_list     = adm8211_set_rx_mode,
+       .get_stats              = adm8211_get_stats,
+       .get_tx_stats           = adm8211_get_tx_stats,
+       .get_tsf                = adm8211_get_tsft
+};
+
+static int __devinit adm8211_probe(struct pci_dev *pdev,
+                                  const struct pci_device_id *id)
+{
+       struct ieee80211_hw *dev;
+       struct adm8211_priv *priv;
+       unsigned long mem_addr, mem_len;
+       unsigned int io_addr, io_len;
+       int err;
+       u32 reg;
+       u8 perm_addr[ETH_ALEN];
+
+#ifndef MODULE
+       static unsigned int cardidx;
+       if (!cardidx++)
+               printk(version);
+#endif
+
+       err = pci_enable_device(pdev);
+       if (err) {
+               printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
+                      pci_name(pdev));
+               return err;
+       }
+
+       io_addr = pci_resource_start(pdev, 0);
+       io_len = pci_resource_len(pdev, 0);
+       mem_addr = pci_resource_start(pdev, 1);
+       mem_len = pci_resource_len(pdev, 1);
+       if (io_len < 256 || mem_len < 1024) {
+               printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
+                      pci_name(pdev));
+               goto err_disable_pdev;
+       }
+
+
+       /* check signature */
+       pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
+       if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
+               printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
+                      pci_name(pdev), reg);
+               goto err_disable_pdev;
+       }
+
+       err = pci_request_regions(pdev, "adm8211");
+       if (err) {
+               printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
+                      pci_name(pdev));
+               return err; /* someone else grabbed it? don't disable it */
+       }
+
+       if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) ||
+           pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
+               printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
+                      pci_name(pdev));
+               goto err_free_reg;
+       }
+
+       pci_set_master(pdev);
+
+       dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
+       if (!dev) {
+               printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
+                      pci_name(pdev));
+               err = -ENOMEM;
+               goto err_free_reg;
+       }
+       priv = dev->priv;
+       priv->pdev = pdev;
+
+       spin_lock_init(&priv->lock);
+
+       SET_IEEE80211_DEV(dev, &pdev->dev);
+
+       pci_set_drvdata(pdev, dev);
+
+       priv->map = pci_iomap(pdev, 1, mem_len);
+       if (!priv->map)
+               priv->map = pci_iomap(pdev, 0, io_len);
+
+       if (!priv->map) {
+               printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
+                      pci_name(pdev));
+               goto err_free_dev;
+       }
+
+       priv->rx_ring_size = rx_ring_size;
+       priv->tx_ring_size = tx_ring_size;
+
+       if (adm8211_alloc_rings(dev)) {
+               printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
+                      pci_name(pdev));
+               goto err_iounmap;
+       }
+
+       pci_read_config_byte(pdev, PCI_CLASS_REVISION, &priv->revid);
+
+       *(u32 *)perm_addr = le32_to_cpu((__force __le32)ADM8211_CSR_READ(PAR0));
+       *(u16 *)&perm_addr[4] =
+               le16_to_cpu((__force __le16)ADM8211_CSR_READ(PAR1) & 0xFFFF);
+
+       if (!is_valid_ether_addr(perm_addr)) {
+               printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
+                      pci_name(pdev));
+               random_ether_addr(perm_addr);
+       }
+       SET_IEEE80211_PERM_ADDR(dev, perm_addr);
+
+       dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
+       dev->flags = IEEE80211_HW_DEFAULT_REG_DOMAIN_CONFIGURED;
+       /* IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */
+
+       dev->channel_change_time = 1000;
+       dev->max_rssi = 100;    /* FIXME: find better value */
+
+       priv->modes[0].mode = MODE_IEEE80211B;
+       /* channel info filled in by adm8211_read_eeprom */
+       memcpy(priv->rates, adm8211_rates, sizeof(adm8211_rates));
+       priv->modes[0].num_rates = ARRAY_SIZE(adm8211_rates);
+       priv->modes[0].rates = priv->rates;
+
+       dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
+
+       priv->retry_limit = 3;
+       priv->ant_power = 0x40;
+       priv->tx_power = 0x40;
+       priv->lpf_cutoff = 0xFF;
+       priv->lnags_threshold = 0xFF;
+       priv->mode = IEEE80211_IF_TYPE_MGMT;
+
+       /* Power-on issue. EEPROM won't read correctly without */
+       if (priv->revid >= ADM8211_REV_BA) {
+               ADM8211_CSR_WRITE(FRCTL, 0);
+               ADM8211_CSR_READ(FRCTL);
+               ADM8211_CSR_WRITE(FRCTL, 1);
+               ADM8211_CSR_READ(FRCTL);
+               msleep(100);
+       }
+
+       err = adm8211_read_eeprom(dev);
+       if (err) {
+               printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
+                      pci_name(pdev));
+               goto err_free_desc;
+       }
+
+       priv->channel = priv->modes[0].channels[0].chan;
+
+       err = ieee80211_register_hwmode(dev, &priv->modes[0]);
+       if (err) {
+               printk(KERN_ERR "%s (adm8211): Can't register hwmode\n",
+                      pci_name(pdev));
+               goto err_free_desc;
+       }
+
+       err = ieee80211_register_hw(dev);
+       if (err) {
+               printk(KERN_ERR "%s (adm8211): Cannot register device\n",
+                      pci_name(pdev));
+               goto err_free_desc;
+       }
+
+       printk(KERN_INFO "%s: hwaddr " MAC_FMT ", Rev 0x%02x\n",
+              wiphy_name(dev->wiphy), MAC_ARG(dev->wiphy->perm_addr),
+              priv->revid);
+
+       return 0;
+
+ err_free_desc:
+       pci_free_consistent(pdev,
+                           sizeof(struct adm8211_desc) * priv->rx_ring_size +
+                           sizeof(struct adm8211_desc) * priv->tx_ring_size,
+                           priv->rx_ring, priv->rx_ring_dma);
+       kfree(priv->rx_buffers);
+
+ err_iounmap:
+       pci_iounmap(pdev, priv->map);
+
+ err_free_dev:
+       pci_set_drvdata(pdev, NULL);
+       ieee80211_free_hw(dev);
+
+ err_free_reg:
+       pci_release_regions(pdev);
+
+ err_disable_pdev:
+       pci_disable_device(pdev);
+       return err;
+}
+
+
+static void __devexit adm8211_remove(struct pci_dev *pdev)
+{
+       struct ieee80211_hw *dev = pci_get_drvdata(pdev);
+       struct adm8211_priv *priv;
+
+       if (!dev)
+               return;
+
+       ieee80211_unregister_hw(dev);
+
+       priv = dev->priv;
+
+       pci_free_consistent(pdev,
+                           sizeof(struct adm8211_desc) * priv->rx_ring_size +
+                           sizeof(struct adm8211_desc) * priv->tx_ring_size,
+                           priv->rx_ring, priv->rx_ring_dma);
+
+       kfree(priv->rx_buffers);
+       kfree(priv->eeprom);
+       pci_iounmap(pdev, priv->map);
+       pci_release_regions(pdev);
+       pci_disable_device(pdev);
+       ieee80211_free_hw(dev);
+}
+
+
+#ifdef CONFIG_PM
+static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+       struct ieee80211_hw *dev = pci_get_drvdata(pdev);
+       struct adm8211_priv *priv = dev->priv;
+
+       if (priv->mode != IEEE80211_IF_TYPE_MGMT) {
+               ieee80211_stop_queues(dev);
+               adm8211_stop(dev);
+       }
+
+       pci_save_state(pdev);
+       pci_set_power_state(pdev, pci_choose_state(pdev, state));
+       return 0;
+}
+
+static int adm8211_resume(struct pci_dev *pdev)
+{
+       struct ieee80211_hw *dev = pci_get_drvdata(pdev);
+       struct adm8211_priv *priv = dev->priv;
+
+       pci_set_power_state(pdev, PCI_D0);
+       pci_restore_state(pdev);
+
+       if (priv->mode != IEEE80211_IF_TYPE_MGMT) {
+               adm8211_open(dev);
+               ieee80211_start_queues(dev);
+       }
+
+       return 0;
+}
+#endif /* CONFIG_PM */
+
+
+MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
+
+/* TODO: implement enable_wake */
+static struct pci_driver adm8211_driver = {
+       .name           = "adm8211",
+       .id_table       = adm8211_pci_id_table,
+       .probe          = adm8211_probe,
+       .remove         = __devexit_p(adm8211_remove),
+#ifdef CONFIG_PM
+       .suspend        = adm8211_suspend,
+       .resume         = adm8211_resume,
+#endif /* CONFIG_PM */
+};
+
+
+
+static int __init adm8211_init(void)
+{
+#ifdef MODULE
+       printk(version);
+#endif
+
+       return pci_register_driver(&adm8211_driver);
+}
+
+
+static void __exit adm8211_exit(void)
+{
+       pci_unregister_driver(&adm8211_driver);
+}
+
+
+module_init(adm8211_init);
+module_exit(adm8211_exit);
diff --git a/drivers/net/wireless/adm8211.h b/drivers/net/wireless/adm8211.h
new file mode 100644 (file)
index 0000000..795d895
--- /dev/null
@@ -0,0 +1,659 @@
+#ifndef ADM8211_H
+#define ADM8211_H
+
+/* ADM8211 Registers */
+
+/* CR32 (SIG) signature */
+#define ADM8211_SIG1           0x82011317 /* ADM8211A */
+#define ADM8211_SIG2           0x82111317 /* ADM8211B/ADM8211C */
+
+#define ADM8211_CSR_READ(r) ioread32(&priv->map->r)
+#define ADM8211_CSR_WRITE(r, val) iowrite32((val), &priv->map->r)
+
+/* CSR (Host Control and Status Registers) */
+struct adm8211_csr {
+       __le32 PAR;             /* 0x00 CSR0 */
+       __le32 FRCTL;           /* 0x04 CSR0A */
+       __le32 TDR;             /* 0x08 CSR1 */
+       __le32 WTDP;            /* 0x0C CSR1A */
+       __le32 RDR;             /* 0x10 CSR2 */
+       __le32 WRDP;            /* 0x14 CSR2A */
+       __le32 RDB;             /* 0x18 CSR3 */
+       __le32 TDBH;            /* 0x1C CSR3A */
+       __le32 TDBD;            /* 0x20 CSR4 */
+       __le32 TDBP;            /* 0x24 CSR4A */
+       __le32 STSR;            /* 0x28 CSR5 */
+       __le32 TDBB;            /* 0x2C CSR5A */
+       __le32 NAR;             /* 0x30 CSR6 */
+       __le32 CSR6A;           /* reserved */
+       __le32 IER;             /* 0x38 CSR7 */
+       __le32 TKIPSCEP;        /* 0x3C CSR7A */
+       __le32 LPC;             /* 0x40 CSR8 */
+       __le32 CSR_TEST1;       /* 0x44 CSR8A */
+       __le32 SPR;             /* 0x48 CSR9 */
+       __le32 CSR_TEST0;       /* 0x4C CSR9A */
+       __le32 WCSR;            /* 0x50 CSR10 */
+       __le32 WPDR;            /* 0x54 CSR10A */
+       __le32 GPTMR;           /* 0x58 CSR11 */
+       __le32 GPIO;            /* 0x5C CSR11A */
+       __le32 BBPCTL;          /* 0x60 CSR12 */
+       __le32 SYNCTL;          /* 0x64 CSR12A */
+       __le32 PLCPHD;          /* 0x68 CSR13 */
+       __le32 MMIWA;           /* 0x6C CSR13A */
+       __le32 MMIRD0;          /* 0x70 CSR14 */
+       __le32 MMIRD1;          /* 0x74 CSR14A */
+       __le32 TXBR;            /* 0x78 CSR15 */
+       __le32 SYNDATA;         /* 0x7C CSR15A */
+       __le32 ALCS;            /* 0x80 CSR16 */
+       __le32 TOFS2;           /* 0x84 CSR17 */
+       __le32 CMDR;            /* 0x88 CSR18 */
+       __le32 PCIC;            /* 0x8C CSR19 */
+       __le32 PMCSR;           /* 0x90 CSR20 */
+       __le32 PAR0;            /* 0x94 CSR21 */
+       __le32 PAR1;            /* 0x98 CSR22 */
+       __le32 MAR0;            /* 0x9C CSR23 */
+       __le32 MAR1;            /* 0xA0 CSR24 */
+       __le32 ATIMDA0;         /* 0xA4 CSR25 */
+       __le32 ABDA1;           /* 0xA8 CSR26 */
+       __le32 BSSID0;          /* 0xAC CSR27 */
+       __le32 TXLMT;           /* 0xB0 CSR28 */
+       __le32 MIBCNT;          /* 0xB4 CSR29 */
+       __le32 BCNT;            /* 0xB8 CSR30 */
+       __le32 TSFTH;           /* 0xBC CSR31 */
+       __le32 TSC;             /* 0xC0 CSR32 */
+       __le32 SYNRF;           /* 0xC4 CSR33 */
+       __le32 BPLI;            /* 0xC8 CSR34 */
+       __le32 CAP0;            /* 0xCC CSR35 */
+       __le32 CAP1;            /* 0xD0 CSR36 */
+       __le32 RMD;             /* 0xD4 CSR37 */
+       __le32 CFPP;            /* 0xD8 CSR38 */
+       __le32 TOFS0;           /* 0xDC CSR39 */
+       __le32 TOFS1;           /* 0xE0 CSR40 */
+       __le32 IFST;            /* 0xE4 CSR41 */
+       __le32 RSPT;            /* 0xE8 CSR42 */
+       __le32 TSFTL;           /* 0xEC CSR43 */
+       __le32 WEPCTL;          /* 0xF0 CSR44 */
+       __le32 WESK;            /* 0xF4 CSR45 */
+       __le32 WEPCNT;          /* 0xF8 CSR46 */
+       __le32 MACTEST;         /* 0xFC CSR47 */
+       __le32 FER;             /* 0x100 */
+       __le32 FEMR;            /* 0x104 */
+       __le32 FPSR;            /* 0x108 */
+       __le32 FFER;            /* 0x10C */
+} __attribute__ ((packed));
+
+/* CSR0 - PAR (PCI Address Register) */
+#define ADM8211_PAR_MWIE       (1 << 24)
+#define ADM8211_PAR_MRLE       (1 << 23)
+#define ADM8211_PAR_MRME       (1 << 21)
+#define ADM8211_PAR_RAP                ((1 << 18) | (1 << 17))
+#define ADM8211_PAR_CAL                ((1 << 15) | (1 << 14))
+#define ADM8211_PAR_PBL                0x00003f00
+#define ADM8211_PAR_BLE                (1 << 7)
+#define ADM8211_PAR_DSL                0x0000007c
+#define ADM8211_PAR_BAR                (1 << 1)
+#define ADM8211_PAR_SWR                (1 << 0)
+
+/* CSR1 - FRCTL (Frame Control Register) */
+#define ADM8211_FRCTL_PWRMGT   (1 << 31)
+#define ADM8211_FRCTL_MAXPSP   (1 << 27)
+#define ADM8211_FRCTL_DRVPRSP  (1 << 26)
+#define ADM8211_FRCTL_DRVBCON  (1 << 25)
+#define ADM8211_FRCTL_AID      0x0000ffff
+#define ADM8211_FRCTL_AID_ON   0x0000c000
+
+/* CSR5 - STSR (Status Register) */
+#define ADM8211_STSR_PCF       (1 << 31)
+#define ADM8211_STSR_BCNTC     (1 << 30)
+#define ADM8211_STSR_GPINT     (1 << 29)
+#define ADM8211_STSR_LinkOff   (1 << 28)
+#define ADM8211_STSR_ATIMTC    (1 << 27)
+#define ADM8211_STSR_TSFTF     (1 << 26)
+#define ADM8211_STSR_TSCZ      (1 << 25)
+#define ADM8211_STSR_LinkOn    (1 << 24)
+#define ADM8211_STSR_SQL       (1 << 23)
+#define ADM8211_STSR_WEPTD     (1 << 22)
+#define ADM8211_STSR_ATIME     (1 << 21)
+#define ADM8211_STSR_TBTT      (1 << 20)
+#define ADM8211_STSR_NISS      (1 << 16)
+#define ADM8211_STSR_AISS      (1 << 15)
+#define ADM8211_STSR_TEIS      (1 << 14)
+#define ADM8211_STSR_FBE       (1 << 13)
+#define ADM8211_STSR_REIS      (1 << 12)
+#define ADM8211_STSR_GPTT      (1 << 11)
+#define ADM8211_STSR_RPS       (1 << 8)
+#define ADM8211_STSR_RDU       (1 << 7)
+#define ADM8211_STSR_RCI       (1 << 6)
+#define ADM8211_STSR_TUF       (1 << 5)
+#define ADM8211_STSR_TRT       (1 << 4)
+#define ADM8211_STSR_TLT       (1 << 3)
+#define ADM8211_STSR_TDU       (1 << 2)
+#define ADM8211_STSR_TPS       (1 << 1)
+#define ADM8211_STSR_TCI       (1 << 0)
+
+/* CSR6 - NAR (Network Access Register) */
+#define ADM8211_NAR_TXCF       (1 << 31)
+#define ADM8211_NAR_HF         (1 << 30)
+#define ADM8211_NAR_UTR                (1 << 29)
+#define ADM8211_NAR_SQ         (1 << 28)
+#define ADM8211_NAR_CFP                (1 << 27)
+#define ADM8211_NAR_SF         (1 << 21)
+#define ADM8211_NAR_TR         ((1 << 15) | (1 << 14))
+#define ADM8211_NAR_ST         (1 << 13)
+#define ADM8211_NAR_OM         ((1 << 11) | (1 << 10))
+#define ADM8211_NAR_MM         (1 << 7)
+#define ADM8211_NAR_PR         (1 << 6)
+#define ADM8211_NAR_EA         (1 << 5)
+#define ADM8211_NAR_PB         (1 << 3)
+#define ADM8211_NAR_STPDMA     (1 << 2)
+#define ADM8211_NAR_SR         (1 << 1)
+#define ADM8211_NAR_CTX                (1 << 0)
+
+#define ADM8211_IDLE()                                                            \
+do {                                                                      \
+       if (priv->nar & (ADM8211_NAR_SR | ADM8211_NAR_ST)) {               \
+               ADM8211_CSR_WRITE(NAR, priv->nar &                         \
+                                      ~(ADM8211_NAR_SR | ADM8211_NAR_ST));\
+               ADM8211_CSR_READ(NAR);                                     \
+               msleep(20);                                                \
+       }                                                                  \
+} while (0)
+
+#define ADM8211_IDLE_RX()                                              \
+do {                                                                   \
+       if (priv->nar & ADM8211_NAR_SR) {                               \
+               ADM8211_CSR_WRITE(NAR, priv->nar & ~ADM8211_NAR_SR);    \
+               ADM8211_CSR_READ(NAR);                                  \
+               mdelay(20);                                             \
+       }                                                               \
+} while (0)
+
+#define ADM8211_RESTORE()                                      \
+do {                                                           \
+       if (priv->nar & (ADM8211_NAR_SR | ADM8211_NAR_ST))      \
+               ADM8211_CSR_WRITE(NAR, priv->nar);              \
+} while (0)
+
+/* CSR7 - IER (Interrupt Enable Register) */
+#define ADM8211_IER_PCFIE      (1 << 31)
+#define ADM8211_IER_BCNTCIE    (1 << 30)
+#define ADM8211_IER_GPIE       (1 << 29)
+#define ADM8211_IER_LinkOffIE  (1 << 28)
+#define ADM8211_IER_ATIMTCIE   (1 << 27)
+#define ADM8211_IER_TSFTFIE    (1 << 26)
+#define ADM8211_IER_TSCZE      (1 << 25)
+#define ADM8211_IER_LinkOnIE   (1 << 24)
+#define ADM8211_IER_SQLIE      (1 << 23)
+#define ADM8211_IER_WEPIE      (1 << 22)
+#define ADM8211_IER_ATIMEIE    (1 << 21)
+#define ADM8211_IER_TBTTIE     (1 << 20)
+#define ADM8211_IER_NIE                (1 << 16)
+#define ADM8211_IER_AIE                (1 << 15)
+#define ADM8211_IER_TEIE       (1 << 14)
+#define ADM8211_IER_FBEIE      (1 << 13)
+#define ADM8211_IER_REIE       (1 << 12)
+#define ADM8211_IER_GPTIE      (1 << 11)
+#define ADM8211_IER_RSIE       (1 << 8)
+#define ADM8211_IER_RUIE       (1 << 7)
+#define ADM8211_IER_RCIE       (1 << 6)
+#define ADM8211_IER_TUIE       (1 << 5)
+#define ADM8211_IER_TRTIE      (1 << 4)
+#define ADM8211_IER_TLTTIE     (1 << 3)
+#define ADM8211_IER_TDUIE      (1 << 2)
+#define ADM8211_IER_TPSIE      (1 << 1)
+#define ADM8211_IER_TCIE       (1 << 0)
+
+/* CSR9 - SPR (Serial Port Register) */
+#define ADM8211_SPR_SRS                (1 << 11)
+#define ADM8211_SPR_SDO                (1 << 3)
+#define ADM8211_SPR_SDI                (1 << 2)
+#define ADM8211_SPR_SCLK       (1 << 1)
+#define ADM8211_SPR_SCS                (1 << 0)
+
+/* CSR9A - CSR_TEST0 */
+#define ADM8211_CSR_TEST0_EPNE (1 << 18)
+#define ADM8211_CSR_TEST0_EPSNM        (1 << 17)
+#define ADM8211_CSR_TEST0_EPTYP        (1 << 16)
+#define ADM8211_CSR_TEST0_EPRLD        (1 << 15)
+
+/* CSR10 - WCSR (Wake-up Control/Status Register) */
+#define ADM8211_WCSR_CRCT      (1 << 30)
+#define ADM8211_WCSR_TSFTWE    (1 << 20)
+#define ADM8211_WCSR_TIMWE     (1 << 19)
+#define ADM8211_WCSR_ATIMWE    (1 << 18)
+#define ADM8211_WCSR_KEYWE     (1 << 17)
+#define ADM8211_WCSR_MPRE      (1 << 9)
+#define ADM8211_WCSR_LSOE      (1 << 8)
+#define ADM8211_WCSR_KEYUP     (1 << 6)
+#define ADM8211_WCSR_TSFTW     (1 << 5)
+#define ADM8211_WCSR_TIMW      (1 << 4)
+#define ADM8211_WCSR_ATIMW     (1 << 3)
+#define ADM8211_WCSR_MPR       (1 << 1)
+#define ADM8211_WCSR_LSO       (1 << 0)
+
+/* CSR11A - GPIO */
+#define ADM8211_CSR_GPIO_EN5   (1 << 17)
+#define ADM8211_CSR_GPIO_EN4   (1 << 16)
+#define ADM8211_CSR_GPIO_EN3   (1 << 15)
+#define ADM8211_CSR_GPIO_EN2   (1 << 14)
+#define ADM8211_CSR_GPIO_EN1   (1 << 13)
+#define ADM8211_CSR_GPIO_EN0   (1 << 12)
+#define ADM8211_CSR_GPIO_O5    (1 << 11)
+#define ADM8211_CSR_GPIO_O4    (1 << 10)
+#define ADM8211_CSR_GPIO_O3    (1 << 9)
+#define ADM8211_CSR_GPIO_O2    (1 << 8)
+#define ADM8211_CSR_GPIO_O1    (1 << 7)
+#define ADM8211_CSR_GPIO_O0    (1 << 6)
+#define ADM8211_CSR_GPIO_IN    0x0000003f
+
+/* CSR12 - BBPCTL (BBP Control port) */
+#define ADM8211_BBPCTL_MMISEL  (1 << 31)
+#define ADM8211_BBPCTL_SPICADD  (0x7F << 24)
+#define ADM8211_BBPCTL_RF3000  (0x20 << 24)
+#define ADM8211_BBPCTL_TXCE    (1 << 23)
+#define ADM8211_BBPCTL_RXCE    (1 << 22)
+#define ADM8211_BBPCTL_CCAP    (1 << 21)
+#define ADM8211_BBPCTL_TYPE    0x001c0000
+#define ADM8211_BBPCTL_WR      (1 << 17)
+#define ADM8211_BBPCTL_RD      (1 << 16)
+#define ADM8211_BBPCTL_ADDR    0x0000ff00
+#define ADM8211_BBPCTL_DATA    0x000000ff
+
+/* CSR12A - SYNCTL (Synthesizer Control port) */
+#define ADM8211_SYNCTL_WR      (1 << 31)
+#define ADM8211_SYNCTL_RD      (1 << 30)
+#define ADM8211_SYNCTL_CS0     (1 << 29)
+#define ADM8211_SYNCTL_CS1     (1 << 28)
+#define ADM8211_SYNCTL_CAL     (1 << 27)
+#define ADM8211_SYNCTL_SELCAL  (1 << 26)
+#define ADM8211_SYNCTL_RFtype  ((1 << 24) || (1 << 23) || (1 << 22))
+#define ADM8211_SYNCTL_RFMD    (1 << 22)
+#define ADM8211_SYNCTL_GENERAL (0x7 << 22)
+/* SYNCTL 21:0 Data (Si4126: 18-bit data, 4-bit address) */
+
+/* CSR18 - CMDR (Command Register) */
+#define ADM8211_CMDR_PM                (1 << 19)
+#define ADM8211_CMDR_APM       (1 << 18)
+#define ADM8211_CMDR_RTE       (1 << 4)
+#define ADM8211_CMDR_DRT       ((1 << 3) | (1 << 2))
+#define ADM8211_CMDR_DRT_8DW   (0x0 << 2)
+#define ADM8211_CMDR_DRT_16DW  (0x1 << 2)
+#define ADM8211_CMDR_DRT_SF    (0x2 << 2)
+
+/* CSR33 - SYNRF (SYNRF direct control) */
+#define ADM8211_SYNRF_SELSYN   (1 << 31)
+#define ADM8211_SYNRF_SELRF    (1 << 30)
+#define ADM8211_SYNRF_LERF     (1 << 29)
+#define ADM8211_SYNRF_LEIF     (1 << 28)
+#define ADM8211_SYNRF_SYNCLK   (1 << 27)
+#define ADM8211_SYNRF_SYNDATA  (1 << 26)
+#define ADM8211_SYNRF_PE1      (1 << 25)
+#define ADM8211_SYNRF_PE2      (1 << 24)
+#define ADM8211_SYNRF_PA_PE    (1 << 23)
+#define ADM8211_SYNRF_TR_SW    (1 << 22)
+#define ADM8211_SYNRF_TR_SWN   (1 << 21)
+#define ADM8211_SYNRF_RADIO    (1 << 20)
+#define ADM8211_SYNRF_CAL_EN   (1 << 19)
+#define ADM8211_SYNRF_PHYRST   (1 << 18)
+
+#define ADM8211_SYNRF_IF_SELECT_0      (1 << 31)
+#define ADM8211_SYNRF_IF_SELECT_1      ((1 << 31) | (1 << 28))
+#define ADM8211_SYNRF_WRITE_SYNDATA_0  (1 << 31)
+#define ADM8211_SYNRF_WRITE_SYNDATA_1  ((1 << 31) | (1 << 26))
+#define ADM8211_SYNRF_WRITE_CLOCK_0    (1 << 31)
+#define ADM8211_SYNRF_WRITE_CLOCK_1    ((1 << 31) | (1 << 27))
+
+/* CSR44 - WEPCTL (WEP Control) */
+#define ADM8211_WEPCTL_WEPENABLE   (1 << 31)
+#define ADM8211_WEPCTL_WPAENABLE   (1 << 30)
+#define ADM8211_WEPCTL_CURRENT_TABLE (1 << 29)
+#define ADM8211_WEPCTL_TABLE_WR        (1 << 28)
+#define ADM8211_WEPCTL_TABLE_RD        (1 << 27)
+#define ADM8211_WEPCTL_WEPRXBYP        (1 << 25)
+#define ADM8211_WEPCTL_SEL_WEPTABLE (1 << 23)
+#define ADM8211_WEPCTL_ADDR    (0x000001ff)
+
+/* CSR45 - WESK (Data Entry for Share/Individual Key) */
+#define ADM8211_WESK_DATA      (0x0000ffff)
+
+/* FER (Function Event Register) */
+#define ADM8211_FER_INTR_EV_ENT        (1 << 15)
+
+
+/* Si4126 RF Synthesizer - Control Registers */
+#define SI4126_MAIN_CONF       0
+#define SI4126_PHASE_DET_GAIN  1
+#define SI4126_POWERDOWN       2
+#define SI4126_RF1_N_DIV       3 /* only Si4136 */
+#define SI4126_RF2_N_DIV       4
+#define SI4126_IF_N_DIV                5
+#define SI4126_RF1_R_DIV       6 /* only Si4136 */
+#define SI4126_RF2_R_DIV       7
+#define SI4126_IF_R_DIV                8
+
+/* Main Configuration */
+#define SI4126_MAIN_XINDIV2    (1 << 6)
+#define SI4126_MAIN_IFDIV      ((1 << 11) | (1 << 10))
+/* Powerdown */
+#define SI4126_POWERDOWN_PDIB  (1 << 1)
+#define SI4126_POWERDOWN_PDRB  (1 << 0)
+
+
+/* RF3000 BBP - Control Port Registers */
+/* 0x00 - reserved */
+#define RF3000_MODEM_CTRL__RX_STATUS 0x01
+#define RF3000_CCA_CTRL 0x02
+#define RF3000_DIVERSITY__RSSI 0x03
+#define RF3000_RX_SIGNAL_FIELD 0x04
+#define RF3000_RX_LEN_MSB 0x05
+#define RF3000_RX_LEN_LSB 0x06
+#define RF3000_RX_SERVICE_FIELD 0x07
+#define RF3000_TX_VAR_GAIN__TX_LEN_EXT 0x11
+#define RF3000_TX_LEN_MSB 0x12
+#define RF3000_TX_LEN_LSB 0x13
+#define RF3000_LOW_GAIN_CALIB 0x14
+#define RF3000_HIGH_GAIN_CALIB 0x15
+
+/* ADM8211 revisions */
+#define ADM8211_REV_AB 0x11
+#define ADM8211_REV_AF 0x15
+#define ADM8211_REV_BA 0x20
+#define ADM8211_REV_CA 0x30
+
+struct adm8211_desc {
+       __le32 status;
+       __le32 length;
+       __le32 buffer1;
+       __le32 buffer2;
+};
+
+#define RDES0_STATUS_OWN       (1 << 31)
+#define RDES0_STATUS_ES                (1 << 30)
+#define RDES0_STATUS_SQL       (1 << 29)
+#define RDES0_STATUS_DE                (1 << 28)
+#define RDES0_STATUS_FS                (1 << 27)
+#define RDES0_STATUS_LS                (1 << 26)
+#define RDES0_STATUS_PCF       (1 << 25)
+#define RDES0_STATUS_SFDE      (1 << 24)
+#define RDES0_STATUS_SIGE      (1 << 23)
+#define RDES0_STATUS_CRC16E    (1 << 22)
+#define RDES0_STATUS_RXTOE     (1 << 21)
+#define RDES0_STATUS_CRC32E    (1 << 20)
+#define RDES0_STATUS_ICVE      (1 << 19)
+#define RDES0_STATUS_DA1       (1 << 17)
+#define RDES0_STATUS_DA0       (1 << 16)
+#define RDES0_STATUS_RXDR      ((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12))
+#define RDES0_STATUS_FL                (0x00000fff)
+
+#define RDES1_CONTROL_RER      (1 << 25)
+#define RDES1_CONTROL_RCH      (1 << 24)
+#define RDES1_CONTROL_RBS2     (0x00fff000)
+#define RDES1_CONTROL_RBS1     (0x00000fff)
+
+#define RDES1_STATUS_RSSI      (0x0000007f)
+
+
+#define TDES0_CONTROL_OWN      (1 << 31)
+#define TDES0_CONTROL_DONE     (1 << 30)
+#define TDES0_CONTROL_TXDR     (0x0ff00000)
+
+#define TDES0_STATUS_OWN       (1 << 31)
+#define TDES0_STATUS_DONE      (1 << 30)
+#define TDES0_STATUS_ES                (1 << 29)
+#define TDES0_STATUS_TLT       (1 << 28)
+#define TDES0_STATUS_TRT       (1 << 27)
+#define TDES0_STATUS_TUF       (1 << 26)
+#define TDES0_STATUS_TRO       (1 << 25)
+#define TDES0_STATUS_SOFBR     (1 << 24)
+#define TDES0_STATUS_ACR       (0x00000fff)
+
+#define TDES1_CONTROL_IC       (1 << 31)
+#define TDES1_CONTROL_LS       (1 << 30)
+#define TDES1_CONTROL_FS       (1 << 29)
+#define TDES1_CONTROL_TER      (1 << 25)
+#define TDES1_CONTROL_TCH      (1 << 24)
+#define TDES1_CONTROL_RBS2     (0x00fff000)
+#define TDES1_CONTROL_RBS1     (0x00000fff)
+
+/* SRAM offsets */
+#define ADM8211_SRAM(x) (priv->revid < ADM8211_REV_BA ? \
+        ADM8211_SRAM_A_ ## x : ADM8211_SRAM_B_ ## x)
+
+#define ADM8211_SRAM_INDIV_KEY   0x0000
+#define ADM8211_SRAM_A_SHARE_KEY 0x0160
+#define ADM8211_SRAM_B_SHARE_KEY 0x00c0
+
+#define ADM8211_SRAM_A_SSID      0x0180
+#define ADM8211_SRAM_B_SSID      0x00d4
+#define ADM8211_SRAM_SSID ADM8211_SRAM(SSID)
+
+#define ADM8211_SRAM_A_SUPP_RATE 0x0191
+#define ADM8211_SRAM_B_SUPP_RATE 0x00dd
+#define ADM8211_SRAM_SUPP_RATE ADM8211_SRAM(SUPP_RATE)
+
+#define ADM8211_SRAM_A_SIZE      0x0200
+#define ADM8211_SRAM_B_SIZE      0x01c0
+#define ADM8211_SRAM_SIZE ADM8211_SRAM(SIZE)
+
+struct adm8211_rx_ring_info {
+       struct sk_buff *skb;
+       dma_addr_t mapping;
+};
+
+struct adm8211_tx_ring_info {
+       struct sk_buff *skb;
+       dma_addr_t mapping;
+       struct ieee80211_tx_control tx_control;
+       size_t hdrlen;
+};
+
+#define PLCP_SIGNAL_1M         0x0a
+#define PLCP_SIGNAL_2M         0x14
+#define PLCP_SIGNAL_5M5                0x37
+#define PLCP_SIGNAL_11M                0x6e
+
+struct adm8211_tx_hdr {
+       u8 da[6];
+       u8 signal; /* PLCP signal / TX rate in 100 Kbps */
+       u8 service;
+       __le16 frame_body_size;
+       __le16 frame_control;
+       __le16 plcp_frag_tail_len;
+       __le16 plcp_frag_head_len;
+       __le16 dur_frag_tail;
+       __le16 dur_frag_head;
+       u8 addr4[6];
+
+#define ADM8211_TXHDRCTL_SHORT_PREAMBLE                (1 <<  0)
+#define ADM8211_TXHDRCTL_MORE_FRAG             (1 <<  1)
+#define ADM8211_TXHDRCTL_MORE_DATA             (1 <<  2)
+#define ADM8211_TXHDRCTL_FRAG_NO               (1 <<  3) /* ? */
+#define ADM8211_TXHDRCTL_ENABLE_RTS            (1 <<  4)
+#define ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE     (1 <<  5)
+#define ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER  (1 << 15) /* ? */
+       __le16 header_control;
+       __le16 frag;
+       u8 reserved_0;
+       u8 retry_limit;
+
+       u32 wep2key0;
+       u32 wep2key1;
+       u32 wep2key2;
+       u32 wep2key3;
+
+       u8 keyid;
+       u8 entry_control;       // huh??
+       u16 reserved_1;
+       u32 reserved_2;
+} __attribute__ ((packed));
+
+
+#define RX_COPY_BREAK 128
+#define RX_PKT_SIZE 2500
+
+struct adm8211_eeprom {
+       __le16  signature;              /* 0x00 */
+       u8      major_version;          /* 0x02 */
+       u8      minor_version;          /* 0x03 */
+       u8      reserved_1[4];          /* 0x04 */
+       u8      hwaddr[6];              /* 0x08 */
+       u8      reserved_2[8];          /* 0x1E */
+       __le16  cr49;                   /* 0x16 */
+       u8      cr03;                   /* 0x18 */
+       u8      cr28;                   /* 0x19 */
+       u8      cr29;                   /* 0x1A */
+       u8      country_code;           /* 0x1B */
+
+/* specific bbp types */
+#define ADM8211_BBP_RFMD3000   0x00
+#define ADM8211_BBP_RFMD3002   0x01
+#define ADM8211_BBP_ADM8011    0x04
+       u8      specific_bbptype;       /* 0x1C */
+       u8      specific_rftype;        /* 0x1D */
+       u8      reserved_3[2];          /* 0x1E */
+       __le16  device_id;              /* 0x20 */
+       __le16  vendor_id;              /* 0x22 */
+       __le16  subsystem_id;           /* 0x24 */
+       __le16  subsystem_vendor_id;    /* 0x26 */
+       u8      maxlat;                 /* 0x28 */
+       u8      mingnt;                 /* 0x29 */
+       __le16  cis_pointer_low;        /* 0x2A */
+       __le16  cis_pointer_high;       /* 0x2C */
+       __le16  csr18;                  /* 0x2E */
+       u8      reserved_4[16];         /* 0x30 */
+       u8      d1_pwrdara;             /* 0x40 */
+       u8      d0_pwrdara;             /* 0x41 */
+       u8      d3_pwrdara;             /* 0x42 */
+       u8      d2_pwrdara;             /* 0x43 */
+       u8      antenna_power[14];      /* 0x44 */
+       __le16  cis_wordcnt;            /* 0x52 */
+       u8      tx_power[14];           /* 0x54 */
+       u8      lpf_cutoff[14];         /* 0x62 */
+       u8      lnags_threshold[14];    /* 0x70 */
+       __le16  checksum;               /* 0x7E */
+       u8      cis_data[0];            /* 0x80, 384 bytes */
+} __attribute__ ((packed));
+
+static const struct ieee80211_rate adm8211_rates[] = {
+       { .rate = 10,
+         .val = 10,
+         .val2 = -10,
+         .flags = IEEE80211_RATE_CCK_2 },
+       { .rate = 20,
+         .val = 20,
+         .val2 = -20,
+         .flags = IEEE80211_RATE_CCK_2 },
+       { .rate = 55,
+         .val = 55,
+         .val2 = -55,
+         .flags = IEEE80211_RATE_CCK_2 },
+       { .rate = 110,
+         .val = 110,
+         .val2 = -110,
+         .flags = IEEE80211_RATE_CCK_2 }
+};
+
+struct ieee80211_chan_range {
+       u8 min;
+       u8 max;
+};
+
+static const struct ieee80211_channel adm8211_channels[] = {
+       { .chan = 1,
+         .freq = 2412},
+       { .chan = 2,
+         .freq = 2417},
+       { .chan = 3,
+         .freq = 2422},
+       { .chan = 4,
+         .freq = 2427},
+       { .chan = 5,
+         .freq = 2432},
+       { .chan = 6,
+         .freq = 2437},
+       { .chan = 7,
+         .freq = 2442},
+       { .chan = 8,
+         .freq = 2447},
+       { .chan = 9,
+         .freq = 2452},
+       { .chan = 10,
+         .freq = 2457},
+       { .chan = 11,
+         .freq = 2462},
+       { .chan = 12,
+         .freq = 2467},
+       { .chan = 13,
+         .freq = 2472},
+       { .chan = 14,
+         .freq = 2484},
+};
+
+struct adm8211_priv {
+       struct pci_dev *pdev;
+       spinlock_t lock;
+       struct adm8211_csr __iomem *map;
+       struct adm8211_desc *rx_ring;
+       struct adm8211_desc *tx_ring;
+       dma_addr_t rx_ring_dma;
+       dma_addr_t tx_ring_dma;
+       struct adm8211_rx_ring_info *rx_buffers;
+       struct adm8211_tx_ring_info *tx_buffers;
+       unsigned int rx_ring_size, tx_ring_size;
+       unsigned int cur_tx, dirty_tx, cur_rx;
+
+       struct ieee80211_low_level_stats stats;
+       struct ieee80211_hw_mode modes[1];
+       struct ieee80211_channel channels[ARRAY_SIZE(adm8211_channels)];
+       struct ieee80211_rate rates[ARRAY_SIZE(adm8211_rates)];
+       int mode;
+
+       int channel;
+       u8 bssid[ETH_ALEN];
+       u8 ssid[32];
+       size_t ssid_len;
+       u8 *mac_addr;
+
+       u8 soft_rx_crc;
+       u8 retry_limit;
+
+       u8 ant_power;
+       u8 tx_power;
+       u8 lpf_cutoff;
+       u8 lnags_threshold;
+       struct adm8211_eeprom *eeprom;
+       size_t eeprom_len;
+
+       u8 revid;
+
+       u32 nar;
+
+#define ADM8211_TYPE_INTERSIL  0x00
+#define ADM8211_TYPE_RFMD      0x01
+#define ADM8211_TYPE_MARVEL    0x02
+#define ADM8211_TYPE_AIROHA    0x03
+#define ADM8211_TYPE_ADMTEK     0x05
+       unsigned int rf_type:3;
+       unsigned int bbp_type:3;
+
+       u8 specific_bbptype;
+       enum {
+               ADM8211_RFMD2948 = 0x0,
+               ADM8211_RFMD2958 = 0x1,
+               ADM8211_RFMD2958_RF3000_CONTROL_POWER = 0x2,
+               ADM8211_MAX2820 = 0x8,
+               ADM8211_AL2210L = 0xC,  /* Airoha */
+       } transceiver_type;
+};
+
+static const struct ieee80211_chan_range cranges[] = {
+       {1,  11},       /* FCC */
+       {1,  11},       /* IC */
+       {1,  13},       /* ETSI */
+       {10, 11},       /* SPAIN */
+       {10, 13},       /* FRANCE */
+       {14, 14},       /* MMK */
+       {1,  14},       /* MMK2 */
+};
+
+#endif /* ADM8211_H */