video: tegra: 2d: reset 2d clock to minimum
Bharat Nihalani [Mon, 23 Jul 2012 05:28:47 +0000 (10:28 +0530)]
This was accidently reverted to be set to max with commit 9774bbe31a.
With 2d clock at max, there is a hit on video power numbers.

Change-Id: Iaf73c6f7800d56229d35fb6a2b00f61d460e986d
Reviewed-on: http://git-master/r/117589
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Donghan Ryu <dryu@nvidia.com>

drivers/video/tegra/host/t30/t30.c

index 0c8d626..334d598 100644 (file)
@@ -142,7 +142,7 @@ static struct nvhost_device tegra_gr2d02_device = {
        .waitbases      = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
        .modulemutexes  = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
                          BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
-       .clocks         = { {"gr2d", UINT_MAX},
+       .clocks         = { {"gr2d", 0},
                          {"epp", 0},
                          {"emc", 300000000} },
        NVHOST_MODULE_NO_POWERGATE_IDS,