ARM: Tegra: Dalmore: Add E1613 EMC DVFS table
Graziano Misuraca [Tue, 29 Jan 2013 19:20:20 +0000 (11:20 -0800)]
Bug 1179719

Change-Id: I2a26e9897d424b857e5e08ee379349c90cd4915b
Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-on: http://git-master/r/195180
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/board-dalmore-memory.c

index 2e4ce63..c5a9981 100644 (file)
@@ -5525,8 +5525,598 @@ static struct tegra11_emc_table e1611_h5tc4g63mfr_pba_table[] = {
        },
 };
 
+static struct tegra11_emc_table e1613_h9ccnnn8jtmlar_ntm_table[] = {
+       {
+               0x40,       /* Rev 4.0.3 */
+               204000,     /* SDRAM frequency */
+               1100,       /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000002, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x0000000c, /* EMC_RC */
+                       0x0000001a, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000008, /* EMC_RAS */
+                       0x00000003, /* EMC_RP */
+                       0x00000008, /* EMC_R2W */
+                       0x00000008, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000a, /* EMC_W2P */
+                       0x00000003, /* EMC_RD_RCD */
+                       0x00000003, /* EMC_WR_RCD */
+                       0x00000002, /* EMC_RRD */
+                       0x00000002, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000003, /* EMC_WDV */
+                       0x00000003, /* EMC_WDV_MASK */
+                       0x00000005, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000e, /* EMC_RDV_MASK */
+                       0x00000303, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000003, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000001, /* EMC_AR2PDEN */
+                       0x0000000c, /* EMC_RW2PDEN */
+                       0x0000001d, /* EMC_TXSR */
+                       0x0000001d, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TCKESR */
+                       0x00000004, /* EMC_TPD */
+                       0x0000000b, /* EMC_TFAW */
+                       0x00000005, /* EMC_TRPAB */
+                       0x00000001, /* EMC_TCLKSTABLE */
+                       0x00000003, /* EMC_TCLKSTOP */
+                       0x00000351, /* EMC_TREFBW */
+                       0x00000000, /* EMC_QUSE_EXTRA */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00014286, /* EMC_FBIO_CFG5 */
+                       0x000000a0, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00038000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00010220, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0003003d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc004, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f008, /* EMC_XM2COMPPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000001f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000100, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00064000, /* EMC_ZCAL_INTERVAL */
+                       0x0000004a, /* EMC_ZCAL_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x01000003, /* MC_EMEM_ARB_CFG */
+                       0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x05050102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0506, /* MC_EMEM_ARB_DA_COVERS */
+                       0x71e40a07, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00038000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000a, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000e, /* EMC_RDV */
+                       0x007df7df, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00034000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00030000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00030000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00034000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00034000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00034000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT_DURATION */
+                       0x00038000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000a, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x0000000e, /* EMC_RDV */
+                       0x007df7df, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x00034000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00030000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00030000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00034000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00034000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00034000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x000000d0, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000017, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0xf320000e, /* EMC_CFG */
+               0x00000000, /* Mode Register 0 */
+               0x00010083, /* Mode Register 1 */
+               0x00020004, /* Mode Register 2 */
+               0x000b0000, /* Mode Register 4 */
+       },
+       {
+               0x40,       /* Rev 4.0.3 */
+               408000,     /* SDRAM frequency */
+               1100,       /* min voltage */
+               "pll_p",    /* clock source id */
+               0x40000000, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000018, /* EMC_RC */
+                       0x00000035, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000011, /* EMC_RAS */
+                       0x00000007, /* EMC_RP */
+                       0x0000000b, /* EMC_R2W */
+                       0x00000009, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000d, /* EMC_W2P */
+                       0x00000007, /* EMC_RD_RCD */
+                       0x00000007, /* EMC_WR_RCD */
+                       0x00000004, /* EMC_RRD */
+                       0x00000002, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000003, /* EMC_WDV */
+                       0x00000003, /* EMC_WDV_MASK */
+                       0x00000008, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000005, /* EMC_QRST */
+                       0x00000010, /* EMC_RDV_MASK */
+                       0x00000607, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000003, /* EMC_PDEX2WR */
+                       0x00000003, /* EMC_PDEX2RD */
+                       0x00000007, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000001, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x0000003a, /* EMC_TXSR */
+                       0x0000003a, /* EMC_TXSRDLL */
+                       0x00000007, /* EMC_TCKE */
+                       0x00000007, /* EMC_TCKESR */
+                       0x00000007, /* EMC_TPD */
+                       0x00000015, /* EMC_TFAW */
+                       0x00000009, /* EMC_TRPAB */
+                       0x00000001, /* EMC_TCLKSTABLE */
+                       0x00000003, /* EMC_TCLKSTOP */
+                       0x000006a2, /* EMC_TREFBW */
+                       0x00000008, /* EMC_QUSE_EXTRA */
+                       0x80000722, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0001aa86, /* EMC_FBIO_CFG5 */
+                       0x00580088, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00020000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00020000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00020000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00020000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00010220, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0003023d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc004, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f008, /* EMC_XM2COMPPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000100, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00064000, /* EMC_ZCAL_INTERVAL */
+                       0x00000093, /* EMC_ZCAL_WAIT_CNT */
+                       0x00120012, /* EMC_MRS_WAIT_CNT */
+                       0x00120012, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000d24, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x02000006, /* MC_EMEM_ARB_CFG */
+                       0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RP */
+                       0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06070102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x0010090c, /* MC_EMEM_ARB_DA_COVERS */
+                       0x71c7130d, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x0000000a, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000006, /* EMC_EINPUT_DURATION */
+                       0x00020000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000b, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000010, /* EMC_RDV */
+                       0x007df7df, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x0001c000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10606, /* EMC_AUTO_CAL_CONFIG */
+                       0x00010000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00010000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00020000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00020000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00020000, /* EMC_DLL_XFORM_DQS3 */
+                       0x0001c000, /* EMC_DLL_XFORM_DQ1 */
+                       0x0001c000, /* EMC_DLL_XFORM_DQ2 */
+                       0x0001c000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x0000000a, /* EMC_QUSE */
+                       0x00000005, /* EMC_EINPUT */
+                       0x00000006, /* EMC_EINPUT_DURATION */
+                       0x00020000, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000b, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000010, /* EMC_RDV */
+                       0x007df7df, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x0001c000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10606, /* EMC_AUTO_CAL_CONFIG */
+                       0x00010000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00010000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00020000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00020000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00020000, /* EMC_DLL_XFORM_DQS3 */
+                       0x0001c000, /* EMC_DLL_XFORM_DQ1 */
+                       0x0001c000, /* EMC_DLL_XFORM_DQ2 */
+                       0x0001c000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x000000d1, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x00000029, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0xf3200006, /* EMC_CFG */
+               0x00000000, /* Mode Register 0 */
+               0x000100c3, /* Mode Register 1 */
+               0x00020006, /* Mode Register 2 */
+               0x000b0000, /* Mode Register 4 */
+       },
+       {
+               0x40,       /* Rev 4.0.3 */
+               600000,     /* SDRAM frequency */
+               1100,       /* min voltage */
+               "pll_m",    /* clock source id */
+               0x80000000, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x00000023, /* EMC_RC */
+                       0x0000004d, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x00000019, /* EMC_RAS */
+                       0x0000000a, /* EMC_RP */
+                       0x0000000b, /* EMC_R2W */
+                       0x0000000b, /* EMC_W2R */
+                       0x00000004, /* EMC_R2P */
+                       0x0000000f, /* EMC_W2P */
+                       0x0000000a, /* EMC_RD_RCD */
+                       0x0000000a, /* EMC_WR_RCD */
+                       0x00000005, /* EMC_RRD */
+                       0x00000003, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000004, /* EMC_WDV */
+                       0x0000000f, /* EMC_WDV_MASK */
+                       0x0000000a, /* EMC_IBDLY */
+                       0x00010000, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x00000006, /* EMC_QRST */
+                       0x00000015, /* EMC_RDV_MASK */
+                       0x000008e4, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000239, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000004, /* EMC_PDEX2WR */
+                       0x00000004, /* EMC_PDEX2RD */
+                       0x0000000a, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000001, /* EMC_AR2PDEN */
+                       0x00000013, /* EMC_RW2PDEN */
+                       0x00000054, /* EMC_TXSR */
+                       0x00000054, /* EMC_TXSRDLL */
+                       0x00000009, /* EMC_TCKE */
+                       0x00000009, /* EMC_TCKESR */
+                       0x00000009, /* EMC_TPD */
+                       0x0000001e, /* EMC_TFAW */
+                       0x0000000d, /* EMC_TRPAB */
+                       0x00000001, /* EMC_TCLKSTABLE */
+                       0x00000003, /* EMC_TCLKSTOP */
+                       0x000009c0, /* EMC_TREFBW */
+                       0x0000000a, /* EMC_QUSE_EXTRA */
+                       0x00000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x0001aa86, /* EMC_FBIO_CFG5 */
+                       0xf00e0199, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0000000c, /* EMC_DLL_XFORM_DQS4 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQS5 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQS6 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00010220, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000003d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc005, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f008, /* EMC_XM2COMPPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000100, /* EMC_FBIO_SPARE */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00064000, /* EMC_ZCAL_INTERVAL */
+                       0x000000d8, /* EMC_ZCAL_WAIT_CNT */
+                       0x00130013, /* EMC_MRS_WAIT_CNT */
+                       0x00130013, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x800012d7, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x00000009, /* MC_EMEM_ARB_CFG */
+                       0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000012, /* MC_EMEM_ARB_TIMING_RC */
+                       0x0000000b, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x0000000e, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x0000000a, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x07070103, /* MC_EMEM_ARB_DA_TURNS */
+                       0x00140d12, /* MC_EMEM_ARB_DA_COVERS */
+                       0x71a91b13, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x0000000d, /* EMC_QUSE */
+                       0x00000008, /* EMC_EINPUT */
+                       0x00000006, /* EMC_EINPUT_DURATION */
+                       0x0000000c, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000f, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000013, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x0000000e, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f11f1f, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000010, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000909, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000010, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQS1 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQS2 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQS3 */
+                       0x0000000e, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000000e, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x0000000d, /* EMC_QUSE */
+                       0x00000008, /* EMC_EINPUT */
+                       0x00000006, /* EMC_EINPUT_DURATION */
+                       0x0000000c, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000f, /* EMC_QSAFE */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000013, /* EMC_RDV */
+                       0x00208208, /* EMC_XM2DQSPADCTRL4 */
+                       0x20820800, /* EMC_XM2DQSPADCTRL3 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f11f1f, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000010, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000909, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000010, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQS1 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQS2 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQS3 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000133, /* MC_PTSA_GRANT_DECREMENT */
+                       0x000c000c, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x000c000d, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x000e0010, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x00100010, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x00150010, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x00000015, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x00150015, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x00900044, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00900090, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x0000003a, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0xd3200000, /* EMC_CFG */
+               0x00000000, /* Mode Register 0 */
+               0x000100e3, /* Mode Register 1 */
+               0x00020007, /* Mode Register 2 */
+               0x000b0000, /* Mode Register 4 */
+       },
+};
+
 static struct tegra11_emc_pdata e1613_h9ccnnn8jtmlar_ntm_pdata = {
        .description = "e1613_h9ccnnn8jtmlar_ntm",
+       .tables = e1613_h9ccnnn8jtmlar_ntm_table,
+       .num_tables = ARRAY_SIZE(e1613_h9ccnnn8jtmlar_ntm_table),
 };
 
 static struct tegra11_emc_pdata e1611_h5tc4g63mfr_pba_pdata = {