MIPS: Enable GENERIC_HARDIRQS_NO__DO_IRQ for all platforms
Ralf Baechle [Mon, 30 Mar 2009 12:49:44 +0000 (14:49 +0200)]
__do_IRQ() is deprecated and will go away.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

12 files changed:
arch/mips/Kconfig
arch/mips/alchemy/Kconfig
arch/mips/kernel/irq-msc01.c
arch/mips/kernel/irq_cpu.c
arch/mips/sgi-ip32/ip32-irq.c
arch/mips/sibyte/bcm1480/irq.c
arch/mips/sibyte/sb1250/irq.c
arch/mips/sni/a20r.c
arch/mips/sni/pcimt.c
arch/mips/sni/pcit.c
arch/mips/sni/rm200.c
arch/mips/txx9/Kconfig

index 206cb79..dc78719 100644 (file)
@@ -77,7 +77,6 @@ config MIPS_COBALT
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_64BIT_KERNEL
        select SYS_SUPPORTS_LITTLE_ENDIAN
-       select GENERIC_HARDIRQS_NO__DO_IRQ
 
 config MACH_DECSTATION
        bool "DECstations"
@@ -132,7 +131,6 @@ config MACH_JAZZ
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
        select SYS_SUPPORTS_100HZ
-       select GENERIC_HARDIRQS_NO__DO_IRQ
        help
         This a family of machines based on the MIPS R4030 chipset which was
         used by several vendors to build RISC/os and Windows NT workstations.
@@ -154,7 +152,6 @@ config LASAT
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
        select SYS_SUPPORTS_LITTLE_ENDIAN
-       select GENERIC_HARDIRQS_NO__DO_IRQ
 
 config LEMOTE_FULONG
        bool "Lemote Fulong mini-PC"
@@ -175,7 +172,6 @@ config LEMOTE_FULONG
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select SYS_SUPPORTS_HIGHMEM
        select SYS_HAS_EARLY_PRINTK
-       select GENERIC_HARDIRQS_NO__DO_IRQ
        select GENERIC_ISA_DMA_SUPPORT_BROKEN
        select CPU_HAS_WB
        help
@@ -250,7 +246,6 @@ config MACH_VR41XX
        select CEVT_R4K
        select CSRC_R4K
        select SYS_HAS_CPU_VR41XX
-       select GENERIC_HARDIRQS_NO__DO_IRQ
 
 config NXP_STB220
        bool "NXP STB220 board"
@@ -364,7 +359,6 @@ config SGI_IP27
        select SYS_SUPPORTS_BIG_ENDIAN
        select SYS_SUPPORTS_NUMA
        select SYS_SUPPORTS_SMP
-       select GENERIC_HARDIRQS_NO__DO_IRQ
        help
          This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
          workstations.  To compile a Linux kernel that runs on these, say Y
@@ -563,7 +557,6 @@ config MIKROTIK_RB532
        select CEVT_R4K
        select CSRC_R4K
        select DMA_NONCOHERENT
-       select GENERIC_HARDIRQS_NO__DO_IRQ
        select HW_HAS_PCI
        select IRQ_CPU
        select SYS_HAS_CPU_MIPS32_R1
@@ -700,8 +693,7 @@ config SCHED_OMIT_FRAME_POINTER
        default y
 
 config GENERIC_HARDIRQS_NO__DO_IRQ
-       bool
-       default n
+       def_bool y
 
 #
 # Select some configuration options automatically based on user selections.
@@ -920,7 +912,6 @@ config SOC_PNX833X
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select SYS_SUPPORTS_BIG_ENDIAN
-       select GENERIC_HARDIRQS_NO__DO_IRQ
        select GENERIC_GPIO
        select CPU_MIPSR2_IRQ_VI
 
@@ -939,7 +930,6 @@ config SOC_PNX8550
        select SYS_HAS_CPU_MIPS32_R1
        select SYS_HAS_EARLY_PRINTK
        select SYS_SUPPORTS_32BIT_KERNEL
-       select GENERIC_HARDIRQS_NO__DO_IRQ
        select GENERIC_GPIO
 
 config SWAP_IO_SPACE
index 2fc5c13..8128aeb 100644 (file)
@@ -134,5 +134,4 @@ config SOC_AU1X00
        select SYS_HAS_CPU_MIPS32_R1
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_APM_EMULATION
-       select GENERIC_HARDIRQS_NO__DO_IRQ
        select ARCH_REQUIRE_GPIOLIB
index 963c16d..6a8cd28 100644 (file)
@@ -140,14 +140,16 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma
 
                switch (imp->im_type) {
                case MSC01_IRQ_EDGE:
-                       set_irq_chip(irqbase+n, &msc_edgeirq_type);
+                       set_irq_chip_and_handler_name(irqbase + n,
+                               &msc_edgeirq_type, handle_edge_irq, "edge");
                        if (cpu_has_veic)
                                MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
                        else
                                MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
                        break;
                case MSC01_IRQ_LEVEL:
-                       set_irq_chip(irqbase+n, &msc_levelirq_type);
+                       set_irq_chip_and_handler_name(irqbase+n,
+                               &msc_levelirq_type, handle_level_irq, "level");
                        if (cpu_has_veic)
                                MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
                        else
index 0ee2567..55c8a3c 100644 (file)
@@ -112,7 +112,8 @@ void __init mips_cpu_irq_init(void)
         */
        if (cpu_has_mipsmt)
                for (i = irq_base; i < irq_base + 2; i++)
-                       set_irq_chip(i, &mips_mt_cpu_irq_controller);
+                       set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
+                                                handle_percpu_irq);
 
        for (i = irq_base + 2; i < irq_base + 8; i++)
                set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
index 0d6b666..0aefc53 100644 (file)
@@ -325,16 +325,11 @@ static void mask_and_ack_maceisa_irq(unsigned int irq)
 {
        unsigned long mace_int;
 
-       switch (irq) {
-       case MACEISA_PARALLEL_IRQ:
-       case MACEISA_SERIAL1_TDMAPR_IRQ:
-       case MACEISA_SERIAL2_TDMAPR_IRQ:
-               /* edge triggered */
-               mace_int = mace->perif.ctrl.istat;
-               mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
-               mace->perif.ctrl.istat = mace_int;
-               break;
-       }
+       /* edge triggered */
+       mace_int = mace->perif.ctrl.istat;
+       mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
+       mace->perif.ctrl.istat = mace_int;
+
        disable_maceisa_irq(irq);
 }
 
@@ -344,7 +339,16 @@ static void end_maceisa_irq(unsigned irq)
                enable_maceisa_irq(irq);
 }
 
-static struct irq_chip ip32_maceisa_interrupt = {
+static struct irq_chip ip32_maceisa_level_interrupt = {
+       .name           = "IP32 MACE ISA",
+       .ack            = disable_maceisa_irq,
+       .mask           = disable_maceisa_irq,
+       .mask_ack       = disable_maceisa_irq,
+       .unmask         = enable_maceisa_irq,
+       .end            = end_maceisa_irq,
+};
+
+static struct irq_chip ip32_maceisa_edge_interrupt = {
        .name           = "IP32 MACE ISA",
        .ack            = mask_and_ack_maceisa_irq,
        .mask           = disable_maceisa_irq,
@@ -500,27 +504,50 @@ void __init arch_init_irq(void)
        for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
                switch (irq) {
                case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
-                       set_irq_chip(irq, &ip32_mace_interrupt);
+                       set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt,
+                               handle_level_irq, "level");
                        break;
+
                case MACEPCI_SCSI0_IRQ ...  MACEPCI_SHARED2_IRQ:
-                       set_irq_chip(irq, &ip32_macepci_interrupt);
+                       set_irq_chip_and_handler_name(irq,
+                               &ip32_macepci_interrupt, handle_level_irq,
+                               "level");
                        break;
+
                case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
-                       set_irq_chip(irq, &crime_edge_interrupt);
+                       set_irq_chip_and_handler_name(irq,
+                               &crime_edge_interrupt, handle_edge_irq, "edge");
                        break;
                case CRIME_CPUERR_IRQ:
                case CRIME_MEMERR_IRQ:
-                       set_irq_chip(irq, &crime_level_interrupt);
+                       set_irq_chip_and_handler_name(irq,
+                               &crime_level_interrupt, handle_level_irq,
+                               "level");
                        break;
+
                case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
                case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
-                       set_irq_chip(irq, &crime_edge_interrupt);
+                       set_irq_chip_and_handler_name(irq,
+                               &crime_edge_interrupt, handle_edge_irq, "edge");
                        break;
+
                case CRIME_VICE_IRQ:
-                       set_irq_chip(irq, &crime_edge_interrupt);
+                       set_irq_chip_and_handler_name(irq,
+                               &crime_edge_interrupt, handle_edge_irq, "edge");
+                       break;
+
+               case MACEISA_PARALLEL_IRQ:
+               case MACEISA_SERIAL1_TDMAPR_IRQ:
+               case MACEISA_SERIAL2_TDMAPR_IRQ:
+                       set_irq_chip_and_handler_name(irq,
+                               &ip32_maceisa_edge_interrupt, handle_edge_irq,
+                               "edge");
                        break;
+
                default:
-                       set_irq_chip(irq, &ip32_maceisa_interrupt);
+                       set_irq_chip_and_handler_name(irq,
+                               &ip32_maceisa_level_interrupt, handle_level_irq,
+                               "level");
                        break;
                }
        }
index 12b465d..352352b 100644 (file)
@@ -236,7 +236,7 @@ void __init init_bcm1480_irqs(void)
        int i;
 
        for (i = 0; i < BCM1480_NR_IRQS; i++) {
-               set_irq_chip(i, &bcm1480_irq_type);
+               set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq);
                bcm1480_irq_owner[i] = 0;
        }
 }
index 808ac29..c08ff58 100644 (file)
@@ -220,7 +220,7 @@ void __init init_sb1250_irqs(void)
        int i;
 
        for (i = 0; i < SB1250_NR_IRQS; i++) {
-               set_irq_chip(i, &sb1250_irq_type);
+               set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq);
                sb1250_irq_owner[i] = 0;
        }
 }
index 3f8cf5e..7dd76fb 100644 (file)
@@ -219,7 +219,7 @@ void __init sni_a20r_irq_init(void)
        int i;
 
        for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++)
-               set_irq_chip(i, &a20r_irq_type);
+               set_irq_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
        sni_hwint = a20r_hwint;
        change_c0_status(ST0_IM, IE_IRQ0);
        setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq);
index 834650f..74e6c67 100644 (file)
@@ -304,7 +304,7 @@ void __init sni_pcimt_irq_init(void)
        mips_cpu_irq_init();
        /* Actually we've got more interrupts to handle ...  */
        for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++)
-               set_irq_chip(i, &pcimt_irq_type);
+               set_irq_chip_and_handler(i, &pcimt_irq_type, handle_level_irq);
        sni_hwint = sni_pcimt_hwint;
        change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3);
 }
index e5f12cf..071a957 100644 (file)
@@ -246,7 +246,7 @@ void __init sni_pcit_irq_init(void)
 
        mips_cpu_irq_init();
        for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
-               set_irq_chip(i, &pcit_irq_type);
+               set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
        *(volatile u32 *)SNI_PCIT_INT_REG = 0;
        sni_hwint = sni_pcit_hwint;
        change_c0_status(ST0_IM, IE_IRQ1);
@@ -259,7 +259,7 @@ void __init sni_pcit_cplus_irq_init(void)
 
        mips_cpu_irq_init();
        for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
-               set_irq_chip(i, &pcit_irq_type);
+               set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
        *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
        sni_hwint = sni_pcit_hwint_cplus;
        change_c0_status(ST0_IM, IE_IRQ0);
index 5310aa7..b4352a0 100644 (file)
@@ -487,7 +487,7 @@ void __init sni_rm200_irq_init(void)
        mips_cpu_irq_init();
        /* Actually we've got more interrupts to handle ...  */
        for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++)
-               set_irq_chip(i, &rm200_irq_type);
+               set_irq_chip_and_handler(i, &rm200_irq_type, handle_level_irq);
        sni_hwint = sni_rm200_hwint;
        change_c0_status(ST0_IM, IE_IRQ0);
        setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq);
index 226e8bb..0db7cf3 100644 (file)
@@ -20,7 +20,6 @@ config MACH_TXX9
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select SYS_SUPPORTS_BIG_ENDIAN
-       select GENERIC_HARDIRQS_NO__DO_IRQ
 
 config TOSHIBA_JMR3927
        bool "Toshiba JMR-TX3927 board"