arm: tegra: cardhu: enabling wifi
Rakesh Goyal [Tue, 25 Jan 2011 16:08:58 +0000 (21:08 +0530)]
adding platform device for wifi

Original-Change-Id: I14a3f26098fd1c246a53e863ddab9a42efceb23d
Reviewed-on: http://git-master/r/16914
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Rakesh Kumar <krakesh@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I22aeeef067eac9acac1383e6e472db93b1647c85

Rebase-Id: R69b2ec8803520eacde3f3844987b445b1abe1fbb

arch/arm/mach-tegra/board-cardhu-pinmux.c
arch/arm/mach-tegra/board-cardhu.c

index 9deb72b..4389a33 100755 (executable)
@@ -92,8 +92,8 @@ static __initdata struct tegra_pingroup_config cardhu_pinmux[] = {
        DEFAULT_PINMUX(SDMMC3_DAT3,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
        DEFAULT_PINMUX(SDMMC3_DAT4,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
        DEFAULT_PINMUX(SDMMC3_DAT5,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
-       DEFAULT_PINMUX(SDMMC3_DAT6,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
-       DEFAULT_PINMUX(SDMMC3_DAT7,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT6,     RSVD1,           NORMAL,     NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT7,     RSVD1,           NORMAL,     NORMAL,     INPUT),
 
        /* SDMMC4 pinmux */
        DEFAULT_PINMUX(SDMMC4_CLK,      SDMMC4,          NORMAL,    NORMAL,     INPUT),
index f960b2d..709a1c3 100644 (file)
@@ -151,16 +151,16 @@ static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
        { "uartd",      "clk_m",        13000000,       true},
        { "uarte",      "clk_m",        13000000,       true},
        { "pll_m",      NULL,           0,              true},
-       { "blink",      "clk_32k",      32768,          false},
        { "pll_p_out4", "pll_p",        24000000,       true },
        { "pwm",        "clk_32k",      32768,          false},
-       { "blink",      "clk_32k",      32768,          false},
+       { "blink",      "clk_32k",      32768,          true},
        { "pll_a",      NULL,           56448000,       true},
        { "pll_a_out0", NULL,           11289600,       true},
        { "i2s1",       "pll_a_out0",   11289600,       true},
        { "i2s2",       "pll_a_out0",   11289600,       true},
        { "audio",      "pll_a_out0",   11289600,       true},
        { "audio_2x",   "audio",        22579200,       true},
+       { "sdmmc3",     "clk_m",        12000000,       true},
        { NULL,         NULL,           0,              0},
 };