arm: tegra: usb_phy: Hard code HSIC phy params
Venu Byravarasu [Mon, 30 Jul 2012 12:47:34 +0000 (17:47 +0530)]
As HSIC does not have any customizable phy params,
hard coding them in the phy driver.

bug 1024260

Change-Id: I64d5c7f91b077134b54b0aadaf44f129ceaa99e5
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-on: http://git-master/r/119299
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/tegra11x_usb_phy.c
arch/arm/mach-tegra/tegra2_usb_phy.c
arch/arm/mach-tegra/tegra3_usb_phy.c

index a165e50..fffccc5 100644 (file)
 #define DBG(stuff...)  do {} while (0)
 #endif
 
+/* define HSIC phy params */
+#define HSIC_SYNC_START_DELAY          9
+#define HSIC_IDLE_WAIT_DELAY           17
+#define HSIC_ELASTIC_UNDERRUN_LIMIT    16
+#define HSIC_ELASTIC_OVERRUN_LIMIT     16
+
 static u32 utmip_rctrl_val, utmip_tctrl_val;
 static DEFINE_SPINLOCK(utmip_pad_lock);
 static int utmip_pad_count;
@@ -1955,7 +1961,6 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
 {
        unsigned long val;
        void __iomem *base = phy->regs;
-       struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
 
        DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
 
@@ -1984,13 +1989,13 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
        writel(val, base + USB_SUSP_CTRL);
 
        val = readl(base + UHSIC_HSRX_CFG0);
-       val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
-       val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
-       val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
+       val |= UHSIC_IDLE_WAIT(HSIC_IDLE_WAIT_DELAY);
+       val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(HSIC_ELASTIC_UNDERRUN_LIMIT);
+       val |= UHSIC_ELASTIC_OVERRUN_LIMIT(HSIC_ELASTIC_OVERRUN_LIMIT);
        writel(val, base + UHSIC_HSRX_CFG0);
 
        val = readl(base + UHSIC_HSRX_CFG1);
-       val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
+       val |= UHSIC_HS_SYNC_START_DLY(HSIC_SYNC_START_DELAY);
        writel(val, base + UHSIC_HSRX_CFG1);
 
        /* WAR HSIC TX */
index 3377bd0..ddab299 100644 (file)
 #define DBG(stuff...)  do {} while (0)
 #endif
 
+/* define HSIC phy params */
+#define HSIC_SYNC_START_DELAY          9
+#define HSIC_IDLE_WAIT_DELAY           17
+#define HSIC_ELASTIC_UNDERRUN_LIMIT    16
+#define HSIC_ELASTIC_OVERRUN_LIMIT     16
 
 static DEFINE_SPINLOCK(utmip_pad_lock);
 static int utmip_pad_count;
@@ -1069,7 +1074,6 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
 {
        unsigned long val;
        void __iomem *base = phy->regs;
-       struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
 
        DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
        if (phy->phy_clk_on) {
@@ -1095,13 +1099,13 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
        writel(val, base + USB_SUSP_CTRL);
 
        val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
-       val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
-       val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
-       val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
+       val |= UHSIC_IDLE_WAIT(HSIC_IDLE_WAIT_DELAY);
+       val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(HSIC_ELASTIC_UNDERRUN_LIMIT);
+       val |= UHSIC_ELASTIC_OVERRUN_LIMIT(HSIC_ELASTIC_OVERRUN_LIMIT);
        writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0);
 
        val = readl(base + UHSIC_HSRX_CFG1);
-       val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
+       val |= UHSIC_HS_SYNC_START_DLY(HSIC_SYNC_START_DELAY);
        writel(val, base + UHSIC_HSRX_CFG1);
 
        val = readl(base + UHSIC_MISC_CFG0);
index 4c38932..e609720 100644 (file)
 #define PHY_DBG(stuff...)      do {} while (0)
 #endif
 
+/* define HSIC phy params */
+#define HSIC_SYNC_START_DELAY          9
+#define HSIC_IDLE_WAIT_DELAY           17
+#define HSIC_ELASTIC_UNDERRUN_LIMIT    16
+#define HSIC_ELASTIC_OVERRUN_LIMIT     16
 
 static u32 utmip_rctrl_val, utmip_tctrl_val;
 static DEFINE_SPINLOCK(utmip_pad_lock);
@@ -2224,7 +2229,6 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
 {
        unsigned long val;
        void __iomem *base = phy->regs;
-       struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic;
 
        DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst);
 
@@ -2250,13 +2254,13 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
        writel(val, base + USB_SUSP_CTRL);
 
        val = readl(base + UHSIC_HSRX_CFG0);
-       val |= UHSIC_IDLE_WAIT(config->idle_wait_delay);
-       val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit);
-       val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit);
+       val |= UHSIC_IDLE_WAIT(HSIC_IDLE_WAIT_DELAY);
+       val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(HSIC_ELASTIC_UNDERRUN_LIMIT);
+       val |= UHSIC_ELASTIC_OVERRUN_LIMIT(HSIC_ELASTIC_OVERRUN_LIMIT);
        writel(val, base + UHSIC_HSRX_CFG0);
 
        val = readl(base + UHSIC_HSRX_CFG1);
-       val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay);
+       val |= UHSIC_HS_SYNC_START_DLY(HSIC_SYNC_START_DELAY);
        writel(val, base + UHSIC_HSRX_CFG1);
 
        /* WAR HSIC TX */