video: tegra: host: Parameterize Tegra11 modules
Terje Bergstrom [Fri, 15 Jun 2012 13:41:01 +0000 (16:41 +0300)]
Tegra2 and Tegra3 host1x was parameterized and made to use generated hardware
headers. Adjust Tegra11 modules to do the same.

Bug 982965

Change-Id: Icc17a970cbaf419cabc41b5c475ae1a7a7851ac2
Reviewed-on: http://git-master/r/109268
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>
(cherry picked from commit 970f779f18e7bd498752c9f755cd530a2d8f157b)

drivers/video/tegra/host/gr3d/gr3d_t114.c
drivers/video/tegra/host/host1x/host1x_actmon.c
drivers/video/tegra/host/host1x/hw_host1x_sync.h
drivers/video/tegra/host/t114/t114.c

index b99beed..13cffe9 100644 (file)
@@ -110,11 +110,12 @@ static void save_push_v1(struct nvhost_hwctx *nctx, struct nvhost_cdma *cdma)
        /* wait for 3d idle */
        nvhost_cdma_push(cdma,
                        nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0),
-                       nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE,
-                                       p->syncpt));
+                       nvhost_opcode_imm_incr_syncpt(
+                               host1x_uclass_incr_syncpt_cond_op_done_v(),
+                               p->syncpt));
        nvhost_cdma_push(cdma,
                        nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-                                       NV_CLASS_HOST_WAIT_SYNCPT_BASE, 1),
+                                       host1x_uclass_wait_syncpt_base_r(), 1),
                        nvhost_class_host_wait_syncpt_base(NVSYNCPT_3D,
                                                        p->waitbase, 1));
        /* back to 3d */
@@ -147,11 +148,11 @@ static void __init save_direct_v1(u32 *ptr, u32 start_reg, u32 count,
        nvhost_3dctx_restore_direct(ptr + 1, rst_reg, count);
        ptr += RESTORE_DIRECT_SIZE;
        ptr[1] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-                                       NV_CLASS_HOST_INDOFF, 1);
+                                       host1x_uclass_indoff_r(), 1);
        ptr[2] = nvhost_class_host_indoff_reg_read(NV_HOST_MODULE_GR3D,
                                                start_reg, true);
        /* TODO could do this in the setclass if count < 6 */
-       ptr[3] = nvhost_opcode_nonincr(NV_CLASS_HOST_INDDATA, count);
+       ptr[3] = nvhost_opcode_nonincr(host1x_uclass_inddata_r(), count);
 }
 
 static void __init save_indirect_v1(u32 *ptr, u32 offset_reg, u32 offset,
@@ -165,10 +166,10 @@ static void __init save_indirect_v1(u32 *ptr, u32 offset_reg, u32 offset,
        ptr += RESTORE_INDIRECT_SIZE;
        ptr[2] = nvhost_opcode_imm(offset_reg, offset);
        ptr[3] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-                                       NV_CLASS_HOST_INDOFF, 1);
+                                       host1x_uclass_indoff_r(), 1);
        ptr[4] = nvhost_class_host_indoff_reg_read(NV_HOST_MODULE_GR3D,
                                                data_reg, false);
-       ptr[5] = nvhost_opcode_nonincr(NV_CLASS_HOST_INDDATA, count);
+       ptr[5] = nvhost_opcode_nonincr(host1x_uclass_inddata_r(), count);
 }
 
 static void __init save_end_v1(struct host1x_hwctx_handler *p, u32 *ptr)
@@ -178,13 +179,13 @@ static void __init save_end_v1(struct host1x_hwctx_handler *p, u32 *ptr)
        nvhost_3dctx_restore_end(p, ptr + 1);
        ptr += RESTORE_END_SIZE;
        /* op_done syncpt incr to flush FDC */
-       ptr[1] = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE, p->syncpt);
+       ptr[1] = nvhost_opcode_imm_incr_syncpt(host1x_uclass_incr_syncpt_cond_op_done_v(), p->syncpt);
        /* host wait for that syncpt incr, and advance the wait base */
        ptr[2] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
-                       NV_CLASS_HOST_WAIT_SYNCPT_BASE,
+                       host1x_uclass_wait_syncpt_base_r(),
                        nvhost_mask2(
-                               NV_CLASS_HOST_WAIT_SYNCPT_BASE,
-                               NV_CLASS_HOST_INCR_SYNCPT_BASE));
+                               host1x_uclass_wait_syncpt_base_r(),
+                               host1x_uclass_incr_syncpt_base_r()));
        ptr[3] = nvhost_class_host_wait_syncpt_base(p->syncpt,
                        p->waitbase, p->save_incrs - 1);
        ptr[4] = nvhost_class_host_incr_syncpt_base(p->waitbase,
index 82f944f..ce0faee 100644 (file)
@@ -37,37 +37,37 @@ int host1x_actmon_init(struct nvhost_master *host)
                return 0;
 
        /* Initialize average */
-       writel(0, sync_regs + HOST1X_SYNC_ACTMON_INIT_AVG_0);
+       writel(0, sync_regs + host1x_sync_actmon_init_avg_r());
 
        /* Default count weight - 1 for per unit actmons */
-       writel(1, sync_regs + HOST1X_SYNC_ACTMON_COUNT_WEIGHT_0);
+       writel(1, sync_regs + host1x_sync_actmon_count_weight_r());
 
        /*  Write sample period */
-       writel(HOST1X_CREATE(SYNC_ACTMON_STATUS, SAMPLE_PERIOD, 1),
-                       sync_regs + HOST1X_SYNC_ACTMON_STATUS_0);
+       writel(host1x_sync_actmon_status_sample_period_f(1),
+                       sync_regs + host1x_sync_actmon_status_r());
 
        /* Clear interrupt status */
-       writel(0xffffffff, sync_regs + HOST1X_SYNC_ACTMON_INTR_STATUS_0);
+       writel(0xffffffff, sync_regs + host1x_sync_actmon_intr_status_r());
 
        /* Set watermarks - arbitrary for now */
-       writel(0x100, sync_regs + HOST1X_SYNC_ACTMON_AVG_UPPER_WMARK_0);
-       writel(0x50, sync_regs + HOST1X_SYNC_ACTMON_AVG_LOWER_WMARK_0);
+       writel(0x100, sync_regs + host1x_sync_actmon_avg_upper_wmark_r());
+       writel(0x50, sync_regs + host1x_sync_actmon_avg_lower_wmark_r());
 
-       val = readl(sync_regs + HOST1X_SYNC_ACTMON_CTRL_0);
+       val = readl(sync_regs + host1x_sync_actmon_ctrl_r());
        /* Enable periodic mode */
-       val |= HOST1X_CREATE(SYNC_ACTMON_CTRL, ENB_PERIODIC, 1);
+       val |= host1x_sync_actmon_ctrl_enb_periodic_f(1);
        /* Enable watermark interrupts */
-       val |= HOST1X_CREATE(SYNC_ACTMON_CTRL, AVG_ABOVE_WMARK_EN, 1);
-       val |= HOST1X_CREATE(SYNC_ACTMON_CTRL, AVG_BELOW_WMARK_EN, 1);
+       val |= host1x_sync_actmon_ctrl_avg_above_wmark_en_f(1);
+       val |= host1x_sync_actmon_ctrl_avg_below_wmark_en_f(1);
        /* Number of upper wmark breaches before interrupt */
-       val |= HOST1X_CREATE(SYNC_ACTMON_CTRL, CONSECUTIVE_ABOVE_WMARK_NUM, 1);
+       val |= host1x_sync_actmon_ctrl_consecutive_above_wmark_num_f(1);
        /* Number of below wmark breaches before interrupt */
-       val |= HOST1X_CREATE(SYNC_ACTMON_CTRL, CONSECUTIVE_BELOW_WMARK_NUM, 1);
+       val |= host1x_sync_actmon_ctrl_consecutive_below_wmark_num_f(1);
        /* Moving avg IIR filter window size 2^6=128 */
-       val |= HOST1X_CREATE(SYNC_ACTMON_CTRL, K_VAL, 6);
+       val |= host1x_sync_actmon_ctrl_k_val_f(6);
        /* Enable ACTMON */
-       val |= HOST1X_CREATE(SYNC_ACTMON_CTRL, ENB, 1);
-       writel(val, sync_regs + HOST1X_SYNC_ACTMON_CTRL_0);
+       val |= host1x_sync_actmon_ctrl_enb_f(1);
+       writel(val, sync_regs + host1x_sync_actmon_ctrl_r());
 
        host1x_actmon_initialized = 1;
        return 0;
@@ -82,12 +82,12 @@ void host1x_actmon_deinit(struct nvhost_master *host)
                return;
 
        /* Disable actmon */
-       val = readl(sync_regs + HOST1X_SYNC_ACTMON_CTRL_0);
-       val |= HOST1X_CREATE(SYNC_ACTMON_CTRL, ENB, 1);
-       writel(val, sync_regs + HOST1X_SYNC_ACTMON_CTRL_0);
+       val = readl(sync_regs + host1x_sync_actmon_ctrl_r());
+       val |= host1x_sync_actmon_ctrl_enb_f(0);
+       writel(val, sync_regs + host1x_sync_actmon_ctrl_r());
 
        /* Clear interrupt status */
-       writel(0xffffffff, sync_regs + HOST1X_SYNC_ACTMON_INTR_STATUS_0);
+       writel(0xffffffff, sync_regs + host1x_sync_actmon_intr_status_r());
 
        host1x_actmon_initialized = 0;
 }
@@ -99,7 +99,7 @@ int host1x_actmon_avg(struct nvhost_master *host, u32 *val)
        if (!host1x_actmon_initialized)
                return -ENODEV;
 
-       *val = readl(sync_regs + HOST1X_SYNC_ACTMON_AVG_COUNT_0);
+       *val = readl(sync_regs + host1x_sync_actmon_avg_count_r());
        rmb();
 
        return 0;
index 67f0cbf..8414299 100644 (file)
@@ -66,6 +66,22 @@ static inline u32 host1x_sync_hintstatus_r(void)
 {
        return 0x20;
 }
+static inline u32 host1x_sync_hintstatus_gr3d_actmon_intr_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_hintstatus_gr3d_actmon_intr_f(u32 v)
+{
+       return (v & 0x1) << 9;
+}
+static inline u32 host1x_sync_hintstatus_gr3d_actmon_intr_m(void)
+{
+       return 0x1 << 9;
+}
+static inline u32 host1x_sync_hintstatus_gr3d_actmon_intr_v(u32 r)
+{
+       return (r >> 9) & 0x1;
+}
 static inline u32 host1x_sync_hintmask_r(void)
 {
        return 0x24;
@@ -394,5 +410,373 @@ static inline u32 host1x_sync_cbstat_0_cbclass0_v(u32 r)
 {
        return (r >> 16) & 0x3ff;
 }
+static inline u32 host1x_sync_actmon_ctrl_r(void)
+{
+       return 0x9d0;
+}
+static inline u32 host1x_sync_actmon_ctrl_enb_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_ctrl_enb_f(u32 v)
+{
+       return (v & 0x1) << 31;
+}
+static inline u32 host1x_sync_actmon_ctrl_enb_m(void)
+{
+       return 0x1 << 31;
+}
+static inline u32 host1x_sync_actmon_ctrl_enb_v(u32 r)
+{
+       return (r >> 31) & 0x1;
+}
+static inline u32 host1x_sync_actmon_ctrl_consecutive_above_wmark_en_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_ctrl_consecutive_above_wmark_en_f(u32 v)
+{
+       return (v & 0x1) << 30;
+}
+static inline u32 host1x_sync_actmon_ctrl_consecutive_above_wmark_en_m(void)
+{
+       return 0x1 << 30;
+}
+static inline u32 host1x_sync_actmon_ctrl_consecutive_above_wmark_en_v(u32 r)
+{
+       return (r >> 30) & 0x1;
+}
+static inline u32 host1x_sync_actmon_ctrl_consecutive_below_wmark_en_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_ctrl_consecutive_below_wmark_en_f(u32 v)
+{
+       return (v & 0x1) << 29;
+}
+static inline u32 host1x_sync_actmon_ctrl_consecutive_below_wmark_en_m(void)
+{
+       return 0x1 << 29;
+}
+static inline u32 host1x_sync_actmon_ctrl_consecutive_below_wmark_en_v(u32 r)
+{
+       return (r >> 29) & 0x1;
+}
+static inline u32 host1x_sync_actmon_ctrl_consecutive_above_wmark_num_s(void)
+{
+       return 3;
+}
+static inline u32 host1x_sync_actmon_ctrl_consecutive_above_wmark_num_f(u32 v)
+{
+       return (v & 0x7) << 26;
+}
+static inline u32 host1x_sync_actmon_ctrl_consecutive_above_wmark_num_m(void)
+{
+       return 0x7 << 26;
+}
+static inline u32 host1x_sync_actmon_ctrl_consecutive_above_wmark_num_v(u32 r)
+{
+       return (r >> 26) & 0x7;
+}
+static inline u32 host1x_sync_actmon_ctrl_consecutive_below_wmark_num_s(void)
+{
+       return 3;
+}
+static inline u32 host1x_sync_actmon_ctrl_consecutive_below_wmark_num_f(u32 v)
+{
+       return (v & 0x7) << 23;
+}
+static inline u32 host1x_sync_actmon_ctrl_consecutive_below_wmark_num_m(void)
+{
+       return 0x7 << 23;
+}
+static inline u32 host1x_sync_actmon_ctrl_consecutive_below_wmark_num_v(u32 r)
+{
+       return (r >> 23) & 0x7;
+}
+static inline u32 host1x_sync_actmon_ctrl_when_overflow_en_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_ctrl_when_overflow_en_f(u32 v)
+{
+       return (v & 0x1) << 22;
+}
+static inline u32 host1x_sync_actmon_ctrl_when_overflow_en_m(void)
+{
+       return 0x1 << 22;
+}
+static inline u32 host1x_sync_actmon_ctrl_when_overflow_en_v(u32 r)
+{
+       return (r >> 22) & 0x1;
+}
+static inline u32 host1x_sync_actmon_ctrl_avg_above_wmark_en_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_ctrl_avg_above_wmark_en_f(u32 v)
+{
+       return (v & 0x1) << 21;
+}
+static inline u32 host1x_sync_actmon_ctrl_avg_above_wmark_en_m(void)
+{
+       return 0x1 << 21;
+}
+static inline u32 host1x_sync_actmon_ctrl_avg_above_wmark_en_v(u32 r)
+{
+       return (r >> 21) & 0x1;
+}
+static inline u32 host1x_sync_actmon_ctrl_avg_below_wmark_en_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_ctrl_avg_below_wmark_en_f(u32 v)
+{
+       return (v & 0x1) << 20;
+}
+static inline u32 host1x_sync_actmon_ctrl_avg_below_wmark_en_m(void)
+{
+       return 0x1 << 20;
+}
+static inline u32 host1x_sync_actmon_ctrl_avg_below_wmark_en_v(u32 r)
+{
+       return (r >> 20) & 0x1;
+}
+static inline u32 host1x_sync_actmon_ctrl_at_end_en_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_ctrl_at_end_en_f(u32 v)
+{
+       return (v & 0x1) << 19;
+}
+static inline u32 host1x_sync_actmon_ctrl_at_end_en_m(void)
+{
+       return 0x1 << 19;
+}
+static inline u32 host1x_sync_actmon_ctrl_at_end_en_v(u32 r)
+{
+       return (r >> 19) & 0x1;
+}
+static inline u32 host1x_sync_actmon_ctrl_enb_periodic_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_ctrl_enb_periodic_f(u32 v)
+{
+       return (v & 0x1) << 18;
+}
+static inline u32 host1x_sync_actmon_ctrl_enb_periodic_m(void)
+{
+       return 0x1 << 18;
+}
+static inline u32 host1x_sync_actmon_ctrl_enb_periodic_v(u32 r)
+{
+       return (r >> 18) & 0x1;
+}
+static inline u32 host1x_sync_actmon_ctrl_k_val_s(void)
+{
+       return 3;
+}
+static inline u32 host1x_sync_actmon_ctrl_k_val_f(u32 v)
+{
+       return (v & 0x7) << 10;
+}
+static inline u32 host1x_sync_actmon_ctrl_k_val_m(void)
+{
+       return 0x7 << 10;
+}
+static inline u32 host1x_sync_actmon_ctrl_k_val_v(u32 r)
+{
+       return (r >> 10) & 0x7;
+}
+static inline u32 host1x_sync_actmon_init_avg_r(void)
+{
+       return 0x9dc;
+}
+static inline u32 host1x_sync_actmon_avg_upper_wmark_r(void)
+{
+       return 0x9e0;
+}
+static inline u32 host1x_sync_actmon_avg_lower_wmark_r(void)
+{
+       return 0x9e4;
+}
+static inline u32 host1x_sync_actmon_count_weight_r(void)
+{
+       return 0x9e8;
+}
+static inline u32 host1x_sync_actmon_avg_count_r(void)
+{
+       return 0x9f0;
+}
+static inline u32 host1x_sync_actmon_status_r(void)
+{
+       return 0x9f4;
+}
+static inline u32 host1x_sync_actmon_status_sample_period_s(void)
+{
+       return 8;
+}
+static inline u32 host1x_sync_actmon_status_sample_period_f(u32 v)
+{
+       return (v & 0xff) << 3;
+}
+static inline u32 host1x_sync_actmon_status_sample_period_m(void)
+{
+       return 0xff << 3;
+}
+static inline u32 host1x_sync_actmon_status_sample_period_v(u32 r)
+{
+       return (r >> 3) & 0xff;
+}
+static inline u32 host1x_sync_actmon_status_status_source_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_status_status_source_f(u32 v)
+{
+       return (v & 0x1) << 2;
+}
+static inline u32 host1x_sync_actmon_status_status_source_m(void)
+{
+       return 0x1 << 2;
+}
+static inline u32 host1x_sync_actmon_status_status_source_v(u32 r)
+{
+       return (r >> 2) & 0x1;
+}
+static inline u32 host1x_sync_actmon_status_status_source_msec_v(void)
+{
+       return 0;
+}
+static inline u32 host1x_sync_actmon_status_status_source_usec_v(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_status_gr3d_mon_act_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_status_gr3d_mon_act_f(u32 v)
+{
+       return (v & 0x1) << 0;
+}
+static inline u32 host1x_sync_actmon_status_gr3d_mon_act_m(void)
+{
+       return 0x1 << 0;
+}
+static inline u32 host1x_sync_actmon_status_gr3d_mon_act_v(u32 r)
+{
+       return (r >> 0) & 0x1;
+}
+static inline u32 host1x_sync_actmon_status_gr3d_mon_act_inactive_v(void)
+{
+       return 0;
+}
+static inline u32 host1x_sync_actmon_status_gr3d_mon_act_active_v(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_intr_status_r(void)
+{
+       return 0x9f8;
+}
+static inline u32 host1x_sync_actmon_intr_status_consecutive_upper_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_intr_status_consecutive_upper_f(u32 v)
+{
+       return (v & 0x1) << 31;
+}
+static inline u32 host1x_sync_actmon_intr_status_consecutive_upper_m(void)
+{
+       return 0x1 << 31;
+}
+static inline u32 host1x_sync_actmon_intr_status_consecutive_upper_v(u32 r)
+{
+       return (r >> 31) & 0x1;
+}
+static inline u32 host1x_sync_actmon_intr_status_consecutive_lower_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_intr_status_consecutive_lower_f(u32 v)
+{
+       return (v & 0x1) << 30;
+}
+static inline u32 host1x_sync_actmon_intr_status_consecutive_lower_m(void)
+{
+       return 0x1 << 30;
+}
+static inline u32 host1x_sync_actmon_intr_status_consecutive_lower_v(u32 r)
+{
+       return (r >> 30) & 0x1;
+}
+static inline u32 host1x_sync_actmon_intr_status_at_end_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_intr_status_at_end_f(u32 v)
+{
+       return (v & 0x1) << 29;
+}
+static inline u32 host1x_sync_actmon_intr_status_at_end_m(void)
+{
+       return 0x1 << 29;
+}
+static inline u32 host1x_sync_actmon_intr_status_at_end_v(u32 r)
+{
+       return (r >> 29) & 0x1;
+}
+static inline u32 host1x_sync_actmon_intr_status_when_overflow_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_intr_status_when_overflow_f(u32 v)
+{
+       return (v & 0x1) << 26;
+}
+static inline u32 host1x_sync_actmon_intr_status_when_overflow_m(void)
+{
+       return 0x1 << 26;
+}
+static inline u32 host1x_sync_actmon_intr_status_when_overflow_v(u32 r)
+{
+       return (r >> 26) & 0x1;
+}
+static inline u32 host1x_sync_actmon_intr_status_avg_below_wmark_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_intr_status_avg_below_wmark_f(u32 v)
+{
+       return (v & 0x1) << 25;
+}
+static inline u32 host1x_sync_actmon_intr_status_avg_below_wmark_m(void)
+{
+       return 0x1 << 25;
+}
+static inline u32 host1x_sync_actmon_intr_status_avg_below_wmark_v(u32 r)
+{
+       return (r >> 25) & 0x1;
+}
+static inline u32 host1x_sync_actmon_intr_status_avg_above_wmark_s(void)
+{
+       return 1;
+}
+static inline u32 host1x_sync_actmon_intr_status_avg_above_wmark_f(u32 v)
+{
+       return (v & 0x1) << 24;
+}
+static inline u32 host1x_sync_actmon_intr_status_avg_above_wmark_m(void)
+{
+       return 0x1 << 24;
+}
+static inline u32 host1x_sync_actmon_intr_status_avg_above_wmark_v(u32 r)
+{
+       return (r >> 24) & 0x1;
+}
 
 #endif /* __hw_host1x_sync_host1x_h__ */
index 75143cd..3e86ee8 100644 (file)
 
 static int t114_num_alloc_channels = 0;
 
+static struct resource tegra_host1x02_resources[] = {
+       {
+               .start = TEGRA_HOST1X_BASE,
+               .end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       {
+               .start = INT_SYNCPT_THRESH_BASE,
+               .end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1,
+               .flags = IORESOURCE_IRQ,
+       },
+       {
+               .start = INT_HOST1X_MPCORE_GENERAL,
+               .end = INT_HOST1X_MPCORE_GENERAL,
+               .flags = IORESOURCE_IRQ,
+       },
+};
+
+static const char *s_syncpt_names[32] = {
+       "gfx_host",
+       "", "", "", "", "", "", "",
+       "disp0_a", "disp1_a", "avp_0",
+       "csi_vi_0", "csi_vi_1",
+       "vi_isp_0", "vi_isp_1", "vi_isp_2", "vi_isp_3", "vi_isp_4",
+       "2d_0", "2d_1",
+       "disp0_b", "disp1_b",
+       "3d",
+       "mpe",
+       "disp0_c", "disp1_c",
+       "vblank0", "vblank1",
+       "mpe_ebm_eof", "mpe_wr_safe",
+       "2d_tinyblt",
+       "dsi"
+};
+
+static struct host1x_device_info host1x02_info = {
+       .nb_channels    = 9,
+       .nb_pts         = 32,
+       .nb_mlocks      = 16,
+       .nb_bases       = 8,
+       .syncpt_names   = s_syncpt_names,
+       .client_managed = NVSYNCPTS_CLIENT_MANAGED,
+};
+
+static struct nvhost_device tegra_host1x02_device = {
+       .dev            = {.platform_data = &host1x02_info},
+       .name           = "host1x",
+       .id             = -1,
+       .resource       = tegra_host1x02_resources,
+       .num_resources  = ARRAY_SIZE(tegra_host1x02_resources),
+       .clocks         = {{"host1x", UINT_MAX}, {} },
+       NVHOST_MODULE_NO_POWERGATE_IDS,
+};
+
 static struct nvhost_device tegra_display01_device = {
        .name          = "display",
        .id            = -1,
@@ -212,7 +266,7 @@ static struct nvhost_device tegra_tsec01_device = {
 };
 
 static struct nvhost_device *t11_devices[] = {
-       &tegra_host1x01_device,
+       &tegra_host1x02_device,
        &tegra_display01_device,
        &tegra_gr3d03_device,
        &tegra_gr2d03_device,
@@ -249,7 +303,6 @@ static inline int t114_nvhost_hwctx_handler_init(struct nvhost_channel *ch)
 
 static inline void __iomem *t114_channel_aperture(void __iomem *p, int ndx)
 {
-       p += NV_HOST1X_CHANNEL0_BASE;
        p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES;
        return p;
 }
@@ -281,10 +334,12 @@ static void t114_free_nvhost_channel(struct nvhost_channel *ch)
        nvhost_free_channel_internal(ch, &t114_num_alloc_channels);
 }
 
-static struct nvhost_channel *t114_alloc_nvhost_channel(int chindex)
+static struct nvhost_channel *t114_alloc_nvhost_channel(
+               struct nvhost_device *dev)
 {
-       return nvhost_alloc_channel_internal(chindex,
-               NV_HOST1X_CHANNELS_T114, &t114_num_alloc_channels);
+       return nvhost_alloc_channel_internal(dev->index,
+               nvhost_get_host(dev)->info.nb_channels,
+               &t114_num_alloc_channels);
 }
 
 int nvhost_init_t114_support(struct nvhost_master *host,