ARM: tegra11: clock: Put PLLU under h/w control
Alex Frid [Mon, 8 Oct 2012 23:14:26 +0000 (16:14 -0700)]
Put PLLU under h/w control, let s/w enable bits for secondary PLLU
dividers to be cleared.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142507
(cherry picked from commit 971e348d8317416b4f51d32c3515087c7c6dc18a)

Change-Id: I0b3692f1ba653eaea31c4cdd329ee5e5ed01f0d7
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146273
Reviewed-by: Automatic_Commit_Validation_User

arch/arm/mach-tegra/common.c
arch/arm/mach-tegra/tegra11_clocks.c

index dae6ad8..0a09a35 100644 (file)
@@ -340,10 +340,6 @@ static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
        { "csite",      NULL,           0,              true },
 #endif
        { "pll_u",      NULL,           480000000,      true },
-       { "pll_u_12M",  NULL,           0,              true },
-       { "pll_u_48M",  NULL,           0,              true },
-       { "pll_u_60M",  NULL,           0,              true },
-       { "pll_u_480M", NULL,           0,              true },
        { "sdmmc1",     "pll_p",        48000000,       false},
        { "sdmmc3",     "pll_p",        48000000,       true},
        { "sdmmc4",     "pll_p",        48000000,       false},
index c589f57..e880555 100644 (file)
 #define PLL_FIXED_MDIV(c, ref)         ((ref) > (c)->u.pll.cf_max ? 2 : 1)
 
 /* PLLU */
+#define PLLU_BASE_OVERRIDE             (1<<24)
 #define PLLU_BASE_POST_DIV             (1<<20)
 
 /* PLLD */
@@ -1780,7 +1781,13 @@ static void tegra11_pll_clk_init(struct clk *c)
        }
 
        if (c->flags & PLLU) {
+               /* Configure UTMI PLL power management, and put PLLU under
+                  h/w control */
                tegra11_utmi_param_configure(c);
+               usb_plls_hw_control_enable(PLLU_HW_PWRDN_CFG0);
+               val = clk_readl(c->reg + PLL_BASE);
+               val &= ~PLLU_BASE_OVERRIDE;
+               clk_writel(val, c->reg + PLL_BASE);
        }
 }