Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
Linus Torvalds [Tue, 3 Aug 2010 21:31:24 +0000 (14:31 -0700)]
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (291 commits)
  ARM: AMBA: Add pclk support to AMBA bus infrastructure
  ARM: 6278/2: fix regression in RealView after the introduction of pclk
  ARM: 6277/1: mach-shmobile: Allow users to select HZ, default to 128
  ARM: 6276/1: mach-shmobile: remove duplicate NR_IRQS_LEGACY
  ARM: 6246/1: mmci: support larger MMCIDATALENGTH register
  ARM: 6245/1: mmci: enable hardware flow control on Ux500 variants
  ARM: 6244/1: mmci: add variant data and default MCICLOCK support
  ARM: 6243/1: mmci: pass power_mode to the translate_vdd callback
  ARM: 6274/1: add global control registers definition header file for nuc900
  mx2_camera: fix type of dma buffer virtual address pointer
  mx2_camera: Add soc_camera support for i.MX25/i.MX27
  arm/imx/gpio: add spinlock protection
  ARM: Add support for the LPC32XX arch
  ARM: LPC32XX: Arch config menu supoport and makefiles
  ARM: LPC32XX: Phytec 3250 platform support
  ARM: LPC32XX: Misc support functions
  ARM: LPC32XX: Serial support code
  ARM: LPC32XX: System suspend support
  ARM: LPC32XX: GPIO, timer, and IRQ drivers
  ARM: LPC32XX: Clock driver
  ...

514 files changed:
Documentation/arm/memory.txt
Documentation/arm/tcm.txt
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/boot/Makefile
arch/arm/boot/compressed/Makefile
arch/arm/boot/compressed/Makefile.debug [deleted file]
arch/arm/boot/compressed/head-l7200.S [deleted file]
arch/arm/boot/compressed/head.S
arch/arm/boot/compressed/misc.c
arch/arm/common/gic.c
arch/arm/common/sa1111.c
arch/arm/configs/kirkwood_defconfig
arch/arm/configs/lusl7200_defconfig [deleted file]
arch/arm/include/asm/elf.h
arch/arm/include/asm/hwcap.h
arch/arm/include/asm/irq.h
arch/arm/include/asm/kexec.h
arch/arm/include/asm/mach/arch.h
arch/arm/include/asm/mach/irq.h
arch/arm/include/asm/mach/map.h
arch/arm/include/asm/mach/pci.h
arch/arm/include/asm/memblock.h [new file with mode: 0644]
arch/arm/include/asm/memory.h
arch/arm/include/asm/mmzone.h [deleted file]
arch/arm/include/asm/ptrace.h
arch/arm/include/asm/setup.h
arch/arm/include/asm/stackprotector.h [new file with mode: 0644]
arch/arm/include/asm/system.h
arch/arm/include/asm/tls.h [new file with mode: 0644]
arch/arm/include/asm/vfpmacros.h
arch/arm/kernel/Makefile
arch/arm/kernel/asm-offsets.c
arch/arm/kernel/compat.c
arch/arm/kernel/compat.h
arch/arm/kernel/crash_dump.c [new file with mode: 0644]
arch/arm/kernel/entry-armv.S
arch/arm/kernel/irq.c
arch/arm/kernel/machine_kexec.c
arch/arm/kernel/process.c
arch/arm/kernel/ptrace.c
arch/arm/kernel/relocate_kernel.S
arch/arm/kernel/setup.c
arch/arm/kernel/smp.c
arch/arm/kernel/smp_twd.c
arch/arm/kernel/tcm.c
arch/arm/kernel/traps.c
arch/arm/lib/Makefile
arch/arm/mach-aaec2000/include/mach/memory.h
arch/arm/mach-at91/Kconfig
arch/arm/mach-at91/Makefile
arch/arm/mach-at91/at91sam9g45.c
arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
arch/arm/mach-at91/board-sam9g20ek.c
arch/arm/mach-at91/board-snapper9260.c [new file with mode: 0644]
arch/arm/mach-at91/include/mach/at91cap9.h
arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
arch/arm/mach-at91/include/mach/at91sam9260.h
arch/arm/mach-at91/include/mach/at91sam9261.h
arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h [new file with mode: 0644]
arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
arch/arm/mach-at91/include/mach/at91sam9rl.h
arch/arm/mach-at91/include/mach/board.h
arch/arm/mach-at91/include/mach/cpu.h
arch/arm/mach-at91/include/mach/gpio.h
arch/arm/mach-at91/pm.h
arch/arm/mach-at91/pm_slowclock.S
arch/arm/mach-bcmring/core.c
arch/arm/mach-clps711x/Kconfig
arch/arm/mach-clps711x/clep7312.c
arch/arm/mach-clps711x/edb7211-arch.c
arch/arm/mach-clps711x/fortunet.c
arch/arm/mach-clps711x/include/mach/memory.h
arch/arm/mach-cns3xxx/Makefile
arch/arm/mach-cns3xxx/cns3420vb.c
arch/arm/mach-cns3xxx/devices.c [new file with mode: 0644]
arch/arm/mach-cns3xxx/devices.h [new file with mode: 0644]
arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
arch/arm/mach-cns3xxx/pcie.c [new file with mode: 0644]
arch/arm/mach-cns3xxx/pm.c
arch/arm/mach-davinci/include/mach/memory.h
arch/arm/mach-dove/common.c
arch/arm/mach-dove/common.h
arch/arm/mach-dove/dove-db-setup.c
arch/arm/mach-ep93xx/adssphere.c
arch/arm/mach-ep93xx/clock.c
arch/arm/mach-ep93xx/core.c
arch/arm/mach-ep93xx/edb93xx.c
arch/arm/mach-ep93xx/gesbc9312.c
arch/arm/mach-ep93xx/include/mach/platform.h
arch/arm/mach-ep93xx/micro9.c
arch/arm/mach-ep93xx/simone.c
arch/arm/mach-ep93xx/ts72xx.c
arch/arm/mach-imx/Kconfig [new file with mode: 0644]
arch/arm/mach-imx/Makefile [moved from arch/arm/mach-mx2/Makefile with 55% similarity]
arch/arm/mach-imx/Makefile.boot [moved from arch/arm/mach-mx2/Makefile.boot with 67% similarity]
arch/arm/mach-imx/clock-imx1.c [moved from arch/arm/mach-mx1/clock.c with 90% similarity]
arch/arm/mach-imx/clock-imx21.c [moved from arch/arm/mach-mx2/clock_imx21.c with 100% similarity]
arch/arm/mach-imx/clock-imx27.c [moved from arch/arm/mach-mx2/clock_imx27.c with 99% similarity]
arch/arm/mach-imx/cpu-imx27.c [moved from arch/arm/mach-mx2/cpu_imx27.c with 100% similarity]
arch/arm/mach-imx/devices-imx1.h [new file with mode: 0644]
arch/arm/mach-imx/devices-imx21.h [new file with mode: 0644]
arch/arm/mach-imx/devices-imx27.h [new file with mode: 0644]
arch/arm/mach-imx/devices.c [moved from arch/arm/mach-mx2/devices.c with 67% similarity]
arch/arm/mach-imx/devices.h [moved from arch/arm/mach-mx2/devices.h with 54% similarity]
arch/arm/mach-imx/dma-v1.c [moved from arch/arm/plat-mxc/dma-mx1-mx2.c with 99% similarity]
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c [new file with mode: 0644]
arch/arm/mach-imx/include/mach/dma-mx1-mx2.h [new file with mode: 0644]
arch/arm/mach-imx/include/mach/dma-v1.h [moved from arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h with 93% similarity]
arch/arm/mach-imx/mach-cpuimx27.c [moved from arch/arm/mach-mx2/mach-cpuimx27.c with 66% similarity]
arch/arm/mach-imx/mach-imx27lite.c [moved from arch/arm/mach-mx2/mach-imx27lite.c with 86% similarity]
arch/arm/mach-imx/mach-mx1ads.c [moved from arch/arm/mach-mx1/mach-mx1ads.c with 81% similarity]
arch/arm/mach-imx/mach-mx21ads.c [moved from arch/arm/mach-mx2/mach-mx21ads.c with 77% similarity]
arch/arm/mach-imx/mach-mx27_3ds.c [moved from arch/arm/mach-mx2/mach-mx27_3ds.c with 74% similarity]
arch/arm/mach-imx/mach-mx27ads.c [moved from arch/arm/mach-mx2/mach-mx27ads.c with 82% similarity]
arch/arm/mach-imx/mach-mxt_td60.c [moved from arch/arm/mach-mx2/mach-mxt_td60.c with 86% similarity]
arch/arm/mach-imx/mach-pca100.c [moved from arch/arm/mach-mx2/mach-pca100.c with 80% similarity]
arch/arm/mach-imx/mach-pcm038.c [moved from arch/arm/mach-mx2/mach-pcm038.c with 91% similarity]
arch/arm/mach-imx/mach-scb9328.c [moved from arch/arm/mach-mx1/mach-scb9328.c with 89% similarity]
arch/arm/mach-imx/mm-imx1.c [moved from arch/arm/mach-mx1/generic.c with 68% similarity]
arch/arm/mach-imx/mm-imx21.c [moved from arch/arm/mach-mx2/mm-imx21.c with 95% similarity]
arch/arm/mach-imx/mm-imx27.c [moved from arch/arm/mach-mx2/mm-imx27.c with 95% similarity]
arch/arm/mach-imx/mx1-camera-fiq-ksym.c [moved from arch/arm/mach-mx1/ksym_mx1.c with 100% similarity]
arch/arm/mach-imx/mx1-camera-fiq.S [moved from arch/arm/mach-mx1/mx1_camera_fiq.S with 100% similarity]
arch/arm/mach-imx/pcm970-baseboard.c [moved from arch/arm/mach-mx2/pcm970-baseboard.c with 100% similarity]
arch/arm/mach-imx/pm-imx27.c [new file with mode: 0644]
arch/arm/mach-integrator/common.h [new file with mode: 0644]
arch/arm/mach-integrator/core.c
arch/arm/mach-integrator/integrator_ap.c
arch/arm/mach-integrator/integrator_cp.c
arch/arm/mach-integrator/pci_v3.c
arch/arm/mach-iop13xx/include/mach/memory.h
arch/arm/mach-iop13xx/pci.c
arch/arm/mach-ixp2000/pci.c
arch/arm/mach-ixp23xx/pci.c
arch/arm/mach-ixp4xx/common-pci.c
arch/arm/mach-ixp4xx/include/mach/memory.h
arch/arm/mach-kirkwood/Kconfig
arch/arm/mach-kirkwood/Makefile
arch/arm/mach-kirkwood/addr-map.c
arch/arm/mach-kirkwood/common.c
arch/arm/mach-kirkwood/common.h
arch/arm/mach-kirkwood/db88f6281-bp-setup.c
arch/arm/mach-kirkwood/include/mach/bridge-regs.h
arch/arm/mach-kirkwood/include/mach/irqs.h
arch/arm/mach-kirkwood/include/mach/kirkwood.h
arch/arm/mach-kirkwood/include/mach/leds-ns2.h [new file with mode: 0644]
arch/arm/mach-kirkwood/mpp.c
arch/arm/mach-kirkwood/mpp.h
arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
arch/arm/mach-kirkwood/netspace_v2-setup.c
arch/arm/mach-kirkwood/netxbig_v2-setup.c
arch/arm/mach-kirkwood/openrd-setup.c
arch/arm/mach-kirkwood/pcie.c
arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
arch/arm/mach-kirkwood/rd88f6281-setup.c
arch/arm/mach-kirkwood/t5325-setup.c [new file with mode: 0644]
arch/arm/mach-kirkwood/ts219-setup.c
arch/arm/mach-kirkwood/ts41x-setup.c
arch/arm/mach-ks8695/pci.c
arch/arm/mach-l7200/Makefile [deleted file]
arch/arm/mach-l7200/Makefile.boot [deleted file]
arch/arm/mach-l7200/core.c [deleted file]
arch/arm/mach-l7200/include/mach/aux_reg.h [deleted file]
arch/arm/mach-l7200/include/mach/debug-macro.S [deleted file]
arch/arm/mach-l7200/include/mach/entry-macro.S [deleted file]
arch/arm/mach-l7200/include/mach/gp_timers.h [deleted file]
arch/arm/mach-l7200/include/mach/gpio.h [deleted file]
arch/arm/mach-l7200/include/mach/hardware.h [deleted file]
arch/arm/mach-l7200/include/mach/io.h [deleted file]
arch/arm/mach-l7200/include/mach/irqs.h [deleted file]
arch/arm/mach-l7200/include/mach/memory.h [deleted file]
arch/arm/mach-l7200/include/mach/pmpcon.h [deleted file]
arch/arm/mach-l7200/include/mach/pmu.h [deleted file]
arch/arm/mach-l7200/include/mach/serial.h [deleted file]
arch/arm/mach-l7200/include/mach/serial_l7200.h [deleted file]
arch/arm/mach-l7200/include/mach/sib.h [deleted file]
arch/arm/mach-l7200/include/mach/sys-clock.h [deleted file]
arch/arm/mach-l7200/include/mach/system.h [deleted file]
arch/arm/mach-l7200/include/mach/time.h [deleted file]
arch/arm/mach-l7200/include/mach/timex.h [deleted file]
arch/arm/mach-l7200/include/mach/uncompress.h [deleted file]
arch/arm/mach-l7200/include/mach/vmalloc.h [deleted file]
arch/arm/mach-lh7a40x/include/mach/memory.h
arch/arm/mach-lpc32xx/Kconfig [new file with mode: 0644]
arch/arm/mach-lpc32xx/Makefile [new file with mode: 0644]
arch/arm/mach-lpc32xx/Makefile.boot [new file with mode: 0644]
arch/arm/mach-lpc32xx/clock.c [new file with mode: 0644]
arch/arm/mach-lpc32xx/clock.h [new file with mode: 0644]
arch/arm/mach-lpc32xx/common.c [new file with mode: 0644]
arch/arm/mach-lpc32xx/common.h [new file with mode: 0644]
arch/arm/mach-lpc32xx/gpiolib.c [new file with mode: 0644]
arch/arm/mach-lpc32xx/include/mach/clkdev.h [copied from arch/arm/plat-mxc/include/mach/board-pcm037.h with 57% similarity]
arch/arm/mach-lpc32xx/include/mach/debug-macro.S [moved from arch/arm/plat-mxc/include/mach/board-mx35pdk.h with 55% similarity]
arch/arm/mach-lpc32xx/include/mach/entry-macro.S [new file with mode: 0644]
arch/arm/mach-lpc32xx/include/mach/gpio.h [new file with mode: 0644]
arch/arm/mach-lpc32xx/include/mach/hardware.h [new file with mode: 0644]
arch/arm/mach-lpc32xx/include/mach/i2c.h [new file with mode: 0644]
arch/arm/mach-lpc32xx/include/mach/io.h [copied from arch/arm/plat-mxc/include/mach/board-pcm043.h with 57% similarity]
arch/arm/mach-lpc32xx/include/mach/irqs.h [new file with mode: 0644]
arch/arm/mach-lpc32xx/include/mach/memory.h [moved from arch/arm/plat-mxc/include/mach/board-pcm043.h with 57% similarity]
arch/arm/mach-lpc32xx/include/mach/platform.h [new file with mode: 0644]
arch/arm/mach-lpc32xx/include/mach/system.h [new file with mode: 0644]
arch/arm/mach-lpc32xx/include/mach/timex.h [copied from arch/arm/plat-mxc/include/mach/board-pcm037.h with 57% similarity]
arch/arm/mach-lpc32xx/include/mach/uncompress.h [new file with mode: 0644]
arch/arm/mach-lpc32xx/include/mach/vmalloc.h [moved from arch/arm/plat-mxc/include/mach/board-pcm037.h with 57% similarity]
arch/arm/mach-lpc32xx/irq.c [new file with mode: 0644]
arch/arm/mach-lpc32xx/phy3250.c [new file with mode: 0644]
arch/arm/mach-lpc32xx/pm.c [new file with mode: 0644]
arch/arm/mach-lpc32xx/serial.c [new file with mode: 0644]
arch/arm/mach-lpc32xx/suspend.S [new file with mode: 0644]
arch/arm/mach-lpc32xx/timer.c [new file with mode: 0644]
arch/arm/mach-msm/Makefile
arch/arm/mach-msm/board-trout-gpio.c [new file with mode: 0644]
arch/arm/mach-msm/board-trout.c
arch/arm/mach-msm/board-trout.h
arch/arm/mach-msm/include/mach/gpio.h
arch/arm/mach-mx1/Kconfig [deleted file]
arch/arm/mach-mx1/Makefile [deleted file]
arch/arm/mach-mx1/Makefile.boot [deleted file]
arch/arm/mach-mx1/crm_regs.h [deleted file]
arch/arm/mach-mx1/devices.c [deleted file]
arch/arm/mach-mx1/devices.h [deleted file]
arch/arm/mach-mx2/Kconfig [deleted file]
arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c [deleted file]
arch/arm/mach-mx2/serial.c [deleted file]
arch/arm/mach-mx25/Kconfig
arch/arm/mach-mx25/Makefile
arch/arm/mach-mx25/clock.c
arch/arm/mach-mx25/devices-imx25.h [new file with mode: 0644]
arch/arm/mach-mx25/devices.c
arch/arm/mach-mx25/devices.h
arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c [new file with mode: 0644]
arch/arm/mach-mx25/mach-cpuimx25.c [new file with mode: 0644]
arch/arm/mach-mx25/mach-mx25_3ds.c [moved from arch/arm/mach-mx25/mach-mx25pdk.c with 76% similarity]
arch/arm/mach-mx25/mm.c
arch/arm/mach-mx3/Kconfig
arch/arm/mach-mx3/Makefile
arch/arm/mach-mx3/clock-imx35.c
arch/arm/mach-mx3/devices-imx31.h [new file with mode: 0644]
arch/arm/mach-mx3/devices-imx35.h [new file with mode: 0644]
arch/arm/mach-mx3/devices.c
arch/arm/mach-mx3/devices.h
arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c [new file with mode: 0644]
arch/arm/mach-mx3/mach-armadillo5x0.c
arch/arm/mach-mx3/mach-cpuimx35.c [new file with mode: 0644]
arch/arm/mach-mx3/mach-kzm_arm11_01.c
arch/arm/mach-mx3/mach-mx31_3ds.c
arch/arm/mach-mx3/mach-mx31ads.c
arch/arm/mach-mx3/mach-mx31lilly.c
arch/arm/mach-mx3/mach-mx31lite.c
arch/arm/mach-mx3/mach-mx31moboard.c
arch/arm/mach-mx3/mach-mx35_3ds.c [moved from arch/arm/mach-mx3/mach-mx35pdk.c with 89% similarity]
arch/arm/mach-mx3/mach-pcm037.c
arch/arm/mach-mx3/mach-pcm037_eet.c
arch/arm/mach-mx3/mach-pcm043.c
arch/arm/mach-mx3/mach-qong.c
arch/arm/mach-mx3/mm.c
arch/arm/mach-mx3/mx31lilly-db.c
arch/arm/mach-mx3/mx31lite-db.c
arch/arm/mach-mx3/mx31moboard-devboard.c
arch/arm/mach-mx3/mx31moboard-marxbot.c
arch/arm/mach-mx3/mx31moboard-smartbot.c
arch/arm/mach-mx5/Kconfig
arch/arm/mach-mx5/Makefile
arch/arm/mach-mx5/board-cpuimx51.c [new file with mode: 0644]
arch/arm/mach-mx5/board-mx51_3ds.c [new file with mode: 0644]
arch/arm/mach-mx5/board-mx51_babbage.c
arch/arm/mach-mx5/clock-mx51.c
arch/arm/mach-mx5/devices.c
arch/arm/mach-mx5/devices.h
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c [new file with mode: 0644]
arch/arm/mach-mx5/mm.c
arch/arm/mach-mxc91231/crm_regs.h
arch/arm/mach-mxc91231/devices.c
arch/arm/mach-mxc91231/mm.c
arch/arm/mach-nomadik/clock.c
arch/arm/mach-omap1/board-ams-delta.c
arch/arm/mach-omap1/board-fsample.c
arch/arm/mach-omap1/board-generic.c
arch/arm/mach-omap1/board-h2.c
arch/arm/mach-omap1/board-h3.c
arch/arm/mach-omap1/board-htcherald.c
arch/arm/mach-omap1/board-innovator.c
arch/arm/mach-omap1/board-nokia770.c
arch/arm/mach-omap1/board-osk.c
arch/arm/mach-omap1/board-palmte.c
arch/arm/mach-omap1/board-palmtt.c
arch/arm/mach-omap1/board-palmz71.c
arch/arm/mach-omap1/board-perseus2.c
arch/arm/mach-omap1/board-sx1.c
arch/arm/mach-omap1/board-voiceblue.c
arch/arm/mach-omap1/io.c
arch/arm/mach-omap2/board-2430sdp.c
arch/arm/mach-omap2/board-3430sdp.c
arch/arm/mach-omap2/board-3630sdp.c
arch/arm/mach-omap2/board-4430sdp.c
arch/arm/mach-omap2/board-am3517evm.c
arch/arm/mach-omap2/board-apollon.c
arch/arm/mach-omap2/board-cm-t35.c
arch/arm/mach-omap2/board-devkit8000.c
arch/arm/mach-omap2/board-generic.c
arch/arm/mach-omap2/board-h4.c
arch/arm/mach-omap2/board-igep0020.c
arch/arm/mach-omap2/board-ldp.c
arch/arm/mach-omap2/board-n8x0.c
arch/arm/mach-omap2/board-omap3beagle.c
arch/arm/mach-omap2/board-omap3evm.c
arch/arm/mach-omap2/board-omap3pandora.c
arch/arm/mach-omap2/board-omap3touchbook.c
arch/arm/mach-omap2/board-overo.c
arch/arm/mach-omap2/board-rx51.c
arch/arm/mach-omap2/board-zoom2.c
arch/arm/mach-omap2/board-zoom3.c
arch/arm/mach-omap2/clock3xxx_data.c
arch/arm/mach-omap2/io.c
arch/arm/mach-orion5x/Kconfig
arch/arm/mach-orion5x/dns323-setup.c
arch/arm/mach-orion5x/include/mach/system.h
arch/arm/mach-pxa/cm-x2xx-pci.c
arch/arm/mach-pxa/corgi.c
arch/arm/mach-pxa/eseries.c
arch/arm/mach-pxa/generic.h
arch/arm/mach-pxa/include/mach/memory.h
arch/arm/mach-pxa/palmt5.c
arch/arm/mach-pxa/palmtreo.c
arch/arm/mach-pxa/poodle.c
arch/arm/mach-pxa/spitz.c
arch/arm/mach-pxa/tosa.c
arch/arm/mach-realview/core.c
arch/arm/mach-realview/include/mach/board-pb1176.h
arch/arm/mach-realview/include/mach/irqs-pb1176.h
arch/arm/mach-realview/include/mach/memory.h
arch/arm/mach-realview/realview_eb.c
arch/arm/mach-realview/realview_pb1176.c
arch/arm/mach-realview/realview_pb11mp.c
arch/arm/mach-realview/realview_pba8.c
arch/arm/mach-realview/realview_pbx.c
arch/arm/mach-s3c2410/mach-h1940.c
arch/arm/mach-s3c2412/mach-smdk2413.c
arch/arm/mach-s3c2412/mach-vstms.c
arch/arm/mach-s3c2440/mach-rx1950.c
arch/arm/mach-s3c2440/mach-rx3715.c
arch/arm/mach-sa1100/generic.h
arch/arm/mach-sa1100/include/mach/memory.h
arch/arm/mach-shark/include/mach/memory.h
arch/arm/mach-shmobile/Kconfig
arch/arm/mach-shmobile/include/mach/irqs.h
arch/arm/mach-spear3xx/clock.c
arch/arm/mach-spear6xx/clock.c
arch/arm/mach-u300/clock.c
arch/arm/mach-u300/include/mach/memory.h
arch/arm/mach-u300/u300.c
arch/arm/mach-ux500/board-mop500.c
arch/arm/mach-ux500/clock.c
arch/arm/mach-ux500/devices-db8500.c
arch/arm/mach-ux500/include/mach/irqs-board-mop500.h [new file with mode: 0644]
arch/arm/mach-ux500/include/mach/irqs-db5500.h [new file with mode: 0644]
arch/arm/mach-ux500/include/mach/irqs-db8500.h [new file with mode: 0644]
arch/arm/mach-ux500/include/mach/irqs.h
arch/arm/mach-ux500/pins-db8500.h [new file with mode: 0644]
arch/arm/mach-versatile/core.c
arch/arm/mach-versatile/pci.c
arch/arm/mach-vexpress/ct-ca9x4.c
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
arch/arm/mach-vexpress/v2m.c
arch/arm/mach-w90x900/dev.c
arch/arm/mach-w90x900/include/mach/regs-gcr.h [new file with mode: 0644]
arch/arm/mach-w90x900/mach-nuc950evb.c
arch/arm/mach-w90x900/nuc910.c
arch/arm/mach-w90x900/nuc950.c
arch/arm/mm/Kconfig
arch/arm/mm/Makefile
arch/arm/mm/alignment.c
arch/arm/mm/discontig.c [deleted file]
arch/arm/mm/dma-mapping.c
arch/arm/mm/fault.c
arch/arm/mm/init.c
arch/arm/mm/ioremap.c
arch/arm/mm/mm.h
arch/arm/mm/mmap.c
arch/arm/mm/mmu.c
arch/arm/mm/nommu.c
arch/arm/mm/proc-arm1020.S
arch/arm/mm/proc-arm1020e.S
arch/arm/mm/proc-arm1022.S
arch/arm/mm/proc-arm1026.S
arch/arm/mm/proc-arm6_7.S
arch/arm/mm/proc-arm720.S
arch/arm/mm/proc-arm740.S
arch/arm/mm/proc-arm7tdmi.S
arch/arm/mm/proc-arm920.S
arch/arm/mm/proc-arm922.S
arch/arm/mm/proc-arm925.S
arch/arm/mm/proc-arm926.S
arch/arm/mm/proc-arm940.S
arch/arm/mm/proc-arm946.S
arch/arm/mm/proc-arm9tdmi.S
arch/arm/mm/proc-fa526.S
arch/arm/mm/proc-feroceon.S
arch/arm/mm/proc-mohawk.S
arch/arm/mm/proc-sa110.S
arch/arm/mm/proc-sa1100.S
arch/arm/mm/proc-v6.S
arch/arm/mm/proc-v7.S
arch/arm/mm/proc-xsc3.S
arch/arm/mm/proc-xscale.S
arch/arm/mm/vmregion.c
arch/arm/mm/vmregion.h
arch/arm/plat-iop/pci.c
arch/arm/plat-iop/time.c
arch/arm/plat-mxc/3ds_debugboard.c [new file with mode: 0644]
arch/arm/plat-mxc/Kconfig
arch/arm/plat-mxc/Makefile
arch/arm/plat-mxc/audmux-v1.c
arch/arm/plat-mxc/audmux-v2.c
arch/arm/plat-mxc/clock.c
arch/arm/plat-mxc/devices.c
arch/arm/plat-mxc/devices/Kconfig [new file with mode: 0644]
arch/arm/plat-mxc/devices/Makefile [new file with mode: 0644]
arch/arm/plat-mxc/devices/platform-flexcan.c [new file with mode: 0644]
arch/arm/plat-mxc/devices/platform-imx-i2c.c [new file with mode: 0644]
arch/arm/plat-mxc/devices/platform-imx-uart.c [new file with mode: 0644]
arch/arm/plat-mxc/devices/platform-mxc_nand.c [new file with mode: 0644]
arch/arm/plat-mxc/devices/platform-spi_imx.c [new file with mode: 0644]
arch/arm/plat-mxc/ehci.c
arch/arm/plat-mxc/gpio.c
arch/arm/plat-mxc/include/mach/3ds_debugboard.h [new file with mode: 0644]
arch/arm/plat-mxc/include/mach/board-armadillo5x0.h [deleted file]
arch/arm/plat-mxc/include/mach/board-kzmarm11.h [deleted file]
arch/arm/plat-mxc/include/mach/board-mx21ads.h [deleted file]
arch/arm/plat-mxc/include/mach/board-mx27ads.h [deleted file]
arch/arm/plat-mxc/include/mach/board-mx27lite.h [deleted file]
arch/arm/plat-mxc/include/mach/board-mx27pdk.h [deleted file]
arch/arm/plat-mxc/include/mach/board-mx31_3ds.h [deleted file]
arch/arm/plat-mxc/include/mach/board-mx31ads.h [deleted file]
arch/arm/plat-mxc/include/mach/board-mx31lilly.h
arch/arm/plat-mxc/include/mach/board-mx31lite.h
arch/arm/plat-mxc/include/mach/board-mx31moboard.h
arch/arm/plat-mxc/include/mach/board-pcm038.h
arch/arm/plat-mxc/include/mach/board-qong.h [deleted file]
arch/arm/plat-mxc/include/mach/debug-macro.S
arch/arm/plat-mxc/include/mach/devices-common.h [new file with mode: 0644]
arch/arm/plat-mxc/include/mach/eukrea-baseboards.h [moved from arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h with 64% similarity]
arch/arm/plat-mxc/include/mach/gpio.h
arch/arm/plat-mxc/include/mach/iomux-mx25.h
arch/arm/plat-mxc/include/mach/iomux-mx51.h
arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
arch/arm/plat-mxc/include/mach/iomux-v3.h
arch/arm/plat-mxc/include/mach/memory.h
arch/arm/plat-mxc/include/mach/mmc.h
arch/arm/plat-mxc/include/mach/mx1.h
arch/arm/plat-mxc/include/mach/mx25.h
arch/arm/plat-mxc/include/mach/mx27.h
arch/arm/plat-mxc/include/mach/mx2_cam.h [new file with mode: 0644]
arch/arm/plat-mxc/include/mach/mx31.h
arch/arm/plat-mxc/include/mach/mx35.h
arch/arm/plat-mxc/include/mach/mx3_camera.h
arch/arm/plat-mxc/include/mach/mxc91231.h
arch/arm/plat-mxc/include/mach/mxc_nand.h
arch/arm/plat-mxc/include/mach/system.h
arch/arm/plat-mxc/include/mach/timex.h
arch/arm/plat-mxc/include/mach/uncompress.h
arch/arm/plat-mxc/include/mach/vmalloc.h
arch/arm/plat-mxc/irq.c
arch/arm/plat-mxc/system.c
arch/arm/plat-mxc/tzic.c
arch/arm/plat-nomadik/gpio.c
arch/arm/plat-nomadik/include/plat/gpio.h
arch/arm/plat-nomadik/include/plat/mtu.h
arch/arm/plat-nomadik/include/plat/pincfg.h [new file with mode: 0644]
arch/arm/plat-nomadik/timer.c
arch/arm/plat-omap/common.c
arch/arm/plat-omap/fb.c
arch/arm/plat-omap/include/plat/common.h
arch/arm/plat-omap/include/plat/vram.h
arch/arm/plat-orion/pcie.c
arch/arm/plat-spear/time.c
arch/arm/plat-versatile/Makefile
arch/arm/plat-versatile/leds.c [new file with mode: 0644]
arch/arm/vfp/vfpmodule.c
drivers/amba/bus.c
drivers/gpio/pl061.c
drivers/leds/Kconfig
drivers/leds/Makefile
drivers/leds/leds-ns2.c [new file with mode: 0644]
drivers/media/video/Kconfig
drivers/media/video/Makefile
drivers/media/video/mx2_camera.c [new file with mode: 0644]
drivers/misc/Kconfig
drivers/misc/Makefile
drivers/misc/arm-charlcd.c [new file with mode: 0644]
drivers/mmc/host/mmci.c
drivers/mmc/host/mmci.h
drivers/mmc/host/mxcmmc.c
drivers/mtd/nand/mxc_nand.c
drivers/net/phy/marvell.c
drivers/rtc/rtc-pl031.c
drivers/serial/amba-pl010.c
drivers/serial/amba-pl011.c
drivers/usb/gadget/at91_udc.c
drivers/usb/gadget/at91_udc.h
drivers/usb/gadget/fsl_mxc_udc.c
drivers/usb/host/ehci-mxc.c
drivers/video/imxfb.c
drivers/video/omap2/vram.c
include/linux/amba/bus.h
include/linux/amba/mmci.h
include/linux/amba/serial.h
include/linux/marvell_phy.h [new file with mode: 0644]
include/linux/omapfb.h
lib/atomic64_test.c
tools/perf/arch/arm/Makefile [new file with mode: 0644]
tools/perf/arch/arm/util/dwarf-regs.c [new file with mode: 0644]

index eb0fae1..771d48d 100644 (file)
@@ -33,7 +33,13 @@ ffff0000     ffff0fff        CPU vector page.
 
 fffe0000       fffeffff        XScale cache flush area.  This is used
                                in proc-xscale.S to flush the whole data
-                               cache.  Free for other usage on non-XScale.
+                               cache. (XScale does not have TCM.)
+
+fffe8000       fffeffff        DTCM mapping area for platforms with
+                               DTCM mounted inside the CPU.
+
+fffe0000       fffe7fff        ITCM mapping area for platforms with
+                               ITCM mounted inside the CPU.
 
 fff00000       fffdffff        Fixmap mapping region.  Addresses provided
                                by fix_to_virt() will be located here.
index 77fd937..7c15871 100644 (file)
@@ -19,8 +19,8 @@ defines a CPUID_TCM register that you can read out from the
 system control coprocessor. Documentation from ARM can be found
 at http://infocenter.arm.com, search for "TCM Status Register"
 to see documents for all CPUs. Reading this register you can
-determine if ITCM (bit 0) and/or DTCM (bit 16) is present in the
-machine.
+determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
+in the machine.
 
 There is further a TCM region register (search for "TCM Region
 Registers" at the ARM site) that can report and modify the location
@@ -35,7 +35,15 @@ The TCM memory can then be remapped to another address again using
 the MMU, but notice that the TCM if often used in situations where
 the MMU is turned off. To avoid confusion the current Linux
 implementation will map the TCM 1 to 1 from physical to virtual
-memory in the location specified by the machine.
+memory in the location specified by the kernel. Currently Linux
+will map ITCM to 0xfffe0000 and on, and DTCM to 0xfffe8000 and
+on, supporting a maximum of 32KiB of ITCM and 32KiB of DTCM.
+
+Newer versions of the region registers also support dividing these
+TCMs in two separate banks, so for example an 8KiB ITCM is divided
+into two 4KiB banks with its own control registers. The idea is to
+be able to lock and hide one of the banks for use by the secure
+world (TrustZone).
 
 TCM is used for a few things:
 
@@ -65,18 +73,18 @@ in <asm/tcm.h>. Using this interface it is possible to:
   memory. Such a heap is great for things like saving
   device state when shutting off device power domains.
 
-A machine that has TCM memory shall select HAVE_TCM in
-arch/arm/Kconfig for itself, and then the
-rest of the functionality will depend on the physical
-location and size of ITCM and DTCM to be defined in
-mach/memory.h for the machine. Code that needs to use
-TCM shall #include <asm/tcm.h> If the TCM is not located
-at the place given in memory.h it will be moved using
-the TCM Region registers.
+A machine that has TCM memory shall select HAVE_TCM from
+arch/arm/Kconfig for itself. Code that needs to use TCM shall
+#include <asm/tcm.h>
 
 Functions to go into itcm can be tagged like this:
 int __tcmfunc foo(int bar);
 
+Since these are marked to become long_calls and you may want
+to have functions called locally inside the TCM without
+wasting space, there is also the __tcmlocalfunc prefix that
+will make the call relative.
+
 Variables to go into dtcm can be tagged like this:
 int __tcmdata foo;
 
index 98922f7..e39caa8 100644 (file)
@@ -10,6 +10,7 @@ config ARM
        default y
        select HAVE_AOUT
        select HAVE_IDE
+       select HAVE_MEMBLOCK
        select RTC_LIB
        select SYS_SUPPORTS_APM_EMULATION
        select GENERIC_ATOMIC64 if (!CPU_32v6K)
@@ -24,6 +25,7 @@ config ARM
        select HAVE_KERNEL_LZMA
        select HAVE_PERF_EVENTS
        select PERF_USE_VMALLOC
+       select HAVE_REGS_AND_STACK_ACCESS_API
        help
          The ARM series is a line of low-power-consumption RISC chip designs
          licensed by ARM Ltd and targeted at embedded applications and
@@ -55,7 +57,7 @@ config GENERIC_CLOCKEVENTS
 config GENERIC_CLOCKEVENTS_BROADCAST
        bool
        depends on GENERIC_CLOCKEVENTS
-       default y if SMP && !LOCAL_TIMERS
+       default y if SMP
 
 config HAVE_TCM
        bool
@@ -301,6 +303,7 @@ config ARCH_CNS3XXX
        select CPU_V6
        select GENERIC_CLOCKEVENTS
        select ARM_GIC
+       select PCI_DOMAINS if PCI
        help
          Support for Cavium Networks CNS3XXX platform.
 
@@ -439,21 +442,6 @@ config ARCH_IXP4XX
        help
          Support for Intel's IXP4XX (XScale) family of processors.
 
-config ARCH_L7200
-       bool "LinkUp-L7200"
-       select CPU_ARM720T
-       select FIQ
-       select ARCH_USES_GETTIMEOFFSET
-       help
-         Say Y here if you intend to run this kernel on a LinkUp Systems
-         L7200 Software Development Board which uses an ARM720T processor.
-         Information on this board can be obtained at:
-
-         <http://www.linkupsys.com/>
-
-         If you have any questions or comments about the Linux kernel port
-         to this board, send e-mail to <sjhill@cotw.com>.
-
 config ARCH_DOVE
        bool "Marvell Dove"
        select PCI
@@ -482,6 +470,19 @@ config ARCH_LOKI
        help
          Support for the Marvell Loki (88RC8480) SoC.
 
+config ARCH_LPC32XX
+       bool "NXP LPC32XX"
+       select CPU_ARM926T
+       select ARCH_REQUIRE_GPIOLIB
+       select HAVE_IDE
+       select ARM_AMBA
+       select USB_ARCH_HAS_OHCI
+       select COMMON_CLKDEV
+       select GENERIC_TIME
+       select GENERIC_CLOCKEVENTS
+       help
+         Support for the NXP LPC32XX family of processors
+
 config ARCH_MV78XX0
        bool "Marvell MV78xx0"
        select CPU_FEROCEON
@@ -586,6 +587,7 @@ config ARCH_MSM
        bool "Qualcomm MSM"
        select HAVE_CLK
        select GENERIC_CLOCKEVENTS
+       select ARCH_REQUIRE_GPIOLIB
        help
          Support for Qualcomm MSM/QSD based systems.  This runs on the
          apps processor of the MSM/QSD and depends on a shared memory
@@ -719,7 +721,6 @@ config ARCH_SHARK
 config ARCH_LH7A40X
        bool "Sharp LH7A40X"
        select CPU_ARM922T
-       select ARCH_DISCONTIGMEM_ENABLE if !LH7A40X_CONTIGMEM
        select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
        select ARCH_USES_GETTIMEOFFSET
        help
@@ -845,6 +846,8 @@ source "arch/arm/mach-lh7a40x/Kconfig"
 
 source "arch/arm/mach-loki/Kconfig"
 
+source "arch/arm/mach-lpc32xx/Kconfig"
+
 source "arch/arm/mach-msm/Kconfig"
 
 source "arch/arm/mach-mv78xx0/Kconfig"
@@ -1031,11 +1034,6 @@ endmenu
 
 source "arch/arm/common/Kconfig"
 
-config FORCE_MAX_ZONEORDER
-       int
-       depends on SA1111
-       default "9"
-
 menu "Bus support"
 
 config ARM_AMBA
@@ -1060,7 +1058,7 @@ config ISA_DMA_API
        bool
 
 config PCI
-       bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
+       bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
        help
          Find out whether you have a PCI motherboard. PCI is the name of a
          bus system, i.e. the way the CPU talks to the other stuff inside
@@ -1172,9 +1170,10 @@ config HOTPLUG_CPU
 config LOCAL_TIMERS
        bool "Use local timer interrupts"
        depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
-               REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500)
+               REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
+               ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
        default y
-       select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500)
+       select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_VEXPRESS || ARCH_OMAP4 || ARCH_U8500)
        help
          Enable support for local timers on SMP platforms, rather then the
          legacy IPI broadcast method.  Local timers allows the system
@@ -1185,10 +1184,10 @@ source kernel/Kconfig.preempt
 
 config HZ
        int
-       default 128 if ARCH_L7200
        default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210
        default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
        default AT91_TIMER_HZ if ARCH_AT91
+       default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
        default 100
 
 config THUMB2_KERNEL
@@ -1241,10 +1240,6 @@ config OABI_COMPAT
 config ARCH_HAS_HOLES_MEMORYMODEL
        bool
 
-# Discontigmem is deprecated
-config ARCH_DISCONTIGMEM_ENABLE
-       bool
-
 config ARCH_SPARSEMEM_ENABLE
        bool
 
@@ -1252,13 +1247,7 @@ config ARCH_SPARSEMEM_DEFAULT
        def_bool ARCH_SPARSEMEM_ENABLE
 
 config ARCH_SELECT_MEMORY_MODEL
-       def_bool ARCH_DISCONTIGMEM_ENABLE && ARCH_SPARSEMEM_ENABLE
-
-config NODES_SHIFT
-       int
-       default "4" if ARCH_LH7A40X
-       default "2"
-       depends on NEED_MULTIPLE_NODES
+       def_bool ARCH_SPARSEMEM_ENABLE
 
 config HIGHMEM
        bool "High Memory Support (EXPERIMENTAL)"
@@ -1290,8 +1279,33 @@ config HW_PERF_EVENTS
          Enable hardware performance counter support for perf events. If
          disabled, perf events will use software events only.
 
+config SPARSE_IRQ
+       def_bool n
+       help
+         This enables support for sparse irqs. This is useful in general
+         as most CPUs have a fairly sparse array of IRQ vectors, which
+         the irq_desc then maps directly on to. Systems with a high
+         number of off-chip IRQs will want to treat this as
+         experimental until they have been independently verified.
+
 source "mm/Kconfig"
 
+config FORCE_MAX_ZONEORDER
+       int "Maximum zone order" if ARCH_SHMOBILE
+       range 11 64 if ARCH_SHMOBILE
+       default "9" if SA1111
+       default "11"
+       help
+         The kernel memory allocator divides physically contiguous memory
+         blocks into "zones", where each zone is a power of two number of
+         pages.  This option selects the largest power of two that the kernel
+         keeps in the memory allocator.  If you need to allocate very large
+         blocks of physically contiguous memory, then you may need to
+         increase this value.
+
+         This config option is actually maximum order plus one. For example,
+         a value of 11 means that the largest free memory block is 2^10 pages.
+
 config LEDS
        bool "Timer and CPU usage LEDs"
        depends on ARCH_CDB89712 || ARCH_EBSA110 || \
@@ -1375,6 +1389,24 @@ config UACCESS_WITH_MEMCPY
          However, if the CPU data cache is using a write-allocate mode,
          this option is unlikely to provide any performance gain.
 
+config CC_STACKPROTECTOR
+       bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
+       help
+         This option turns on the -fstack-protector GCC feature. This
+         feature puts, at the beginning of functions, a canary value on
+         the stack just before the return address, and validates
+         the value just before actually returning.  Stack based buffer
+         overflows (that need to overwrite this return address) now also
+         overwrite the canary, which gets detected and the attack is then
+         neutralized via a kernel panic.
+         This feature requires gcc version 4.2 or above.
+
+config DEPRECATED_PARAM_STRUCT
+       bool "Provide old way to pass kernel parameters"
+       help
+         This was deprecated in 2001 and announced to live on for 5 years.
+         Some old boot loaders still use this way.
+
 endmenu
 
 menu "Boot options"
@@ -1485,6 +1517,105 @@ config ATAGS_PROC
          Should the atags used to boot the kernel be exported in an "atags"
          file in procfs. Useful with kexec.
 
+config AUTO_ZRELADDR
+       bool "Auto calculation of the decompressed kernel image address"
+       depends on !ZBOOT_ROM && !ARCH_U300
+       help
+         ZRELADDR is the physical address where the decompressed kernel
+         image will be placed. If AUTO_ZRELADDR is selected, the address
+         will be determined at run-time by masking the current IP with
+         0xf8000000. This assumes the zImage being placed in the first 128MB
+         from start of memory.
+
+config ZRELADDR
+       hex "Physical address of the decompressed kernel image"
+       depends on !AUTO_ZRELADDR
+       default 0x00008000 if ARCH_BCMRING ||\
+               ARCH_CNS3XXX ||\
+               ARCH_DOVE ||\
+               ARCH_EBSA110 ||\
+               ARCH_FOOTBRIDGE ||\
+               ARCH_INTEGRATOR ||\
+               ARCH_IOP13XX ||\
+               ARCH_IOP33X ||\
+               ARCH_IXP2000 ||\
+               ARCH_IXP23XX ||\
+               ARCH_IXP4XX ||\
+               ARCH_KIRKWOOD ||\
+               ARCH_KS8695 ||\
+               ARCH_LOKI ||\
+               ARCH_MMP ||\
+               ARCH_MV78XX0 ||\
+               ARCH_NOMADIK ||\
+               ARCH_NUC93X ||\
+               ARCH_NS9XXX ||\
+               ARCH_ORION5X ||\
+               ARCH_SPEAR3XX ||\
+               ARCH_SPEAR6XX ||\
+               ARCH_U8500 ||\
+               ARCH_VERSATILE ||\
+               ARCH_W90X900
+       default 0x08008000 if ARCH_MX1 ||\
+               ARCH_SHARK
+       default 0x10008000 if ARCH_MSM ||\
+               ARCH_OMAP1 ||\
+               ARCH_RPC
+       default 0x20008000 if ARCH_S5P6440 ||\
+               ARCH_S5P6442 ||\
+               ARCH_S5PC100 ||\
+               ARCH_S5PV210
+       default 0x30008000 if ARCH_S3C2410 ||\
+               ARCH_S3C2400 ||\
+               ARCH_S3C2412 ||\
+               ARCH_S3C2416 ||\
+               ARCH_S3C2440 ||\
+               ARCH_S3C2443
+       default 0x40008000 if ARCH_STMP378X ||\
+               ARCH_STMP37XX ||\
+               ARCH_SH7372 ||\
+               ARCH_SH7377
+       default 0x50008000 if ARCH_S3C64XX ||\
+               ARCH_SH7367
+       default 0x60008000 if ARCH_VEXPRESS
+       default 0x80008000 if ARCH_MX25 ||\
+               ARCH_MX3 ||\
+               ARCH_NETX ||\
+               ARCH_OMAP2PLUS ||\
+               ARCH_PNX4008
+       default 0x90008000 if ARCH_MX5 ||\
+               ARCH_MX91231
+       default 0xa0008000 if ARCH_IOP32X ||\
+               ARCH_PXA ||\
+               MACH_MX27
+       default 0xc0008000 if ARCH_LH7A40X ||\
+               MACH_MX21
+       default 0xf0008000 if ARCH_AAEC2000 ||\
+               ARCH_L7200
+       default 0xc0028000 if ARCH_CLPS711X
+       default 0x70008000 if ARCH_AT91 && (ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
+       default 0x20008000 if ARCH_AT91 && !(ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
+       default 0xc0008000 if ARCH_DAVINCI && ARCH_DAVINCI_DA8XX
+       default 0x80008000 if ARCH_DAVINCI && !ARCH_DAVINCI_DA8XX
+       default 0x00008000 if ARCH_EP93XX && EP93XX_SDCE3_SYNC_PHYS_OFFSET
+       default 0xc0008000 if ARCH_EP93XX && EP93XX_SDCE0_PHYS_OFFSET
+       default 0xd0008000 if ARCH_EP93XX && EP93XX_SDCE1_PHYS_OFFSET
+       default 0xe0008000 if ARCH_EP93XX && EP93XX_SDCE2_PHYS_OFFSET
+       default 0xf0008000 if ARCH_EP93XX && EP93XX_SDCE3_ASYNC_PHYS_OFFSET
+       default 0x00008000 if ARCH_GEMINI && GEMINI_MEM_SWAP
+       default 0x10008000 if ARCH_GEMINI && !GEMINI_MEM_SWAP
+       default 0x70008000 if ARCH_REALVIEW && REALVIEW_HIGH_PHYS_OFFSET
+       default 0x00008000 if ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET
+       default 0xc0208000 if ARCH_SA1100 && SA1111
+       default 0xc0008000 if ARCH_SA1100 && !SA1111
+       default 0x30108000 if ARCH_S3C2410 && PM_H1940
+       default 0x28E08000 if ARCH_U300 && MACH_U300_SINGLE_RAM
+       default 0x48008000 if ARCH_U300 && !MACH_U300_SINGLE_RAM
+       help
+         ZRELADDR is the physical address where the decompressed kernel
+         image will be placed. ZRELADDR has to be specified when the
+         assumption of AUTO_ZRELADDR is not valid, or when ZBOOT_ROM is
+         selected.
+
 endmenu
 
 menu "CPU Power Management"
index 64ba313..63d998e 100644 (file)
@@ -34,6 +34,10 @@ ifeq ($(CONFIG_FRAME_POINTER),y)
 KBUILD_CFLAGS  +=-fno-omit-frame-pointer -mapcs -mno-sched-prolog
 endif
 
+ifeq ($(CONFIG_CC_STACKPROTECTOR),y)
+KBUILD_CFLAGS  +=-fstack-protector
+endif
+
 ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
 KBUILD_CPPFLAGS        += -mbig-endian
 AS             += -EB
@@ -139,14 +143,14 @@ machine-$(CONFIG_ARCH_IXP23XX)            := ixp23xx
 machine-$(CONFIG_ARCH_IXP4XX)          := ixp4xx
 machine-$(CONFIG_ARCH_KIRKWOOD)                := kirkwood
 machine-$(CONFIG_ARCH_KS8695)          := ks8695
-machine-$(CONFIG_ARCH_L7200)           := l7200
 machine-$(CONFIG_ARCH_LH7A40X)         := lh7a40x
 machine-$(CONFIG_ARCH_LOKI)            := loki
+machine-$(CONFIG_ARCH_LPC32XX)         := lpc32xx
 machine-$(CONFIG_ARCH_MMP)             := mmp
 machine-$(CONFIG_ARCH_MSM)             := msm
 machine-$(CONFIG_ARCH_MV78XX0)         := mv78xx0
-machine-$(CONFIG_ARCH_MX1)             := mx1
-machine-$(CONFIG_ARCH_MX2)             := mx2
+machine-$(CONFIG_ARCH_MX1)             := imx
+machine-$(CONFIG_ARCH_MX2)             := imx
 machine-$(CONFIG_ARCH_MX25)            := mx25
 machine-$(CONFIG_ARCH_MX3)             := mx3
 machine-$(CONFIG_ARCH_MX5)             := mx5
index 4a590f4..f705213 100644 (file)
 MKIMAGE         := $(srctree)/scripts/mkuboot.sh
 
 ifneq ($(MACHINE),)
-include $(srctree)/$(MACHINE)/Makefile.boot
+-include $(srctree)/$(MACHINE)/Makefile.boot
 endif
 
 # Note: the following conditions must always be true:
-#   ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
 #   PARAMS_PHYS must be within 4MB of ZRELADDR
 #   INITRD_PHYS must be in RAM
-ZRELADDR    := $(zreladdr-y)
 PARAMS_PHYS := $(params_phys-y)
 INITRD_PHYS := $(initrd_phys-y)
 
-export ZRELADDR INITRD_PHYS PARAMS_PHYS
+export INITRD_PHYS PARAMS_PHYS
 
 targets := Image zImage xipImage bootpImage uImage
 
@@ -67,7 +65,7 @@ quiet_cmd_uimage = UIMAGE  $@
 ifeq ($(CONFIG_ZBOOT_ROM),y)
 $(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
 else
-$(obj)/uImage: LOADADDR=$(ZRELADDR)
+$(obj)/uImage: LOADADDR=$(CONFIG_ZRELADDR)
 endif
 
 ifeq ($(CONFIG_THUMB2_KERNEL),y)
index 864a002..7636c9b 100644 (file)
@@ -4,6 +4,7 @@
 # create a compressed vmlinuz image from the original vmlinux
 #
 
+AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
 HEAD   = head.o
 OBJS   = misc.o decompress.o
 FONTC  = $(srctree)/drivers/video/console/font_acorn_8x8.c
@@ -19,10 +20,6 @@ ifeq ($(CONFIG_ARCH_SHARK),y)
 OBJS           += head-shark.o ofw-shark.o
 endif
 
-ifeq ($(CONFIG_ARCH_L7200),y)
-OBJS           += head-l7200.o
-endif
-
 ifeq ($(CONFIG_ARCH_P720T),y)
 # Borrow this code from SA1100
 OBJS           += head-sa1100.o
@@ -82,19 +79,9 @@ endif
 EXTRA_CFLAGS  := -fpic -fno-builtin
 EXTRA_AFLAGS  := -Wa,-march=all
 
-# Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via
-# linker symbols.  We only define initrd_phys and params_phys if the
-# machine class defined the corresponding makefile variable.
-LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux += --be8
 endif
-ifneq ($(INITRD_PHYS),)
-LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS)
-endif
-ifneq ($(PARAMS_PHYS),)
-LDFLAGS_vmlinux += --defsym params_phys=$(PARAMS_PHYS)
-endif
 # ?
 LDFLAGS_vmlinux += -p
 # Report unresolved symbol references
diff --git a/arch/arm/boot/compressed/Makefile.debug b/arch/arm/boot/compressed/Makefile.debug
deleted file mode 100644 (file)
index 491a037..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# linux/arch/arm/boot/compressed/Makefile
-#
-# create a compressed vmlinux image from the original vmlinux
-#
-
-COMPRESSED_EXTRA=../../lib/ll_char_wr.o
-OBJECTS=misc-debug.o ll_char_wr.aout.o
-
-CFLAGS=-D__KERNEL__ -O2 -DSTDC_HEADERS -DSTANDALONE_DEBUG -Wall -I../../../../include -c
-
-test-gzip: piggy.aout.o $(OBJECTS)
-       $(CC) -o $@ $(OBJECTS) piggy.aout.o
-
-misc-debug.o: misc.c
-       $(CC) $(CFLAGS) -o $@ misc.c
-
-piggy.aout.o: piggy.o
-       arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux piggy.o piggy.aout.o
-
-ll_char_wr.aout.o: $(COMPRESSED_EXTRA)
-       arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux $(COMPRESSED_EXTRA) ll_char_wr.aout.o
-
diff --git a/arch/arm/boot/compressed/head-l7200.S b/arch/arm/boot/compressed/head-l7200.S
deleted file mode 100644 (file)
index d0e3b20..0000000
+++ /dev/null
@@ -1,29 +0,0 @@
-/* 
- * linux/arch/arm/boot/compressed/head-l7200.S
- * 
- * Copyright (C) 2000 Steve Hill <sjhill@cotw.com>
- * 
- * Some code borrowed from Nicolas Pitre's 'head-sa1100.S' file. This
- * is merged with head.S by the linker.
- */
-
-#include <asm/mach-types.h>
-
-#ifndef CONFIG_ARCH_L7200
-#error What am I doing here...
-#endif
-
-               .section        ".start", "ax"
-
-__L7200_start:
-               mov     r0, #0x00100000         @ FLASH address of initrd
-               mov     r2, #0xf1000000         @ RAM address of initrd
-               add     r3, r2, #0x00700000     @ Size of initrd 
-1:
-               ldmia   r0!, {r4, r5, r6, r7}
-               stmia   r2!, {r4, r5, r6, r7}
-               cmp     r2, r3
-               ble     1b
-
-               mov     r8, #0                  @ Zero it out
-               mov     r7, #MACH_TYPE_L7200    @ Set architecture ID
index c5191b1..abf4d65 100644 (file)
@@ -170,9 +170,16 @@ not_angel:
 
                .text
                adr     r0, LC0
- ARM(          ldmia   r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp})
- THUMB(                ldmia   r0, {r1, r2, r3, r4, r5, r6, r11, ip}   )
+ ARM(          ldmia   r0, {r1, r2, r3, r5, r6, r11, ip, sp})
+ THUMB(                ldmia   r0, {r1, r2, r3, r5, r6, r11, ip}       )
  THUMB(                ldr     sp, [r0, #32]                           )
+#ifdef CONFIG_AUTO_ZRELADDR
+               @ determine final kernel image address
+               and     r4, pc, #0xf8000000
+               add     r4, r4, #TEXT_OFFSET
+#else
+               ldr     r4, =CONFIG_ZRELADDR
+#endif
                subs    r0, r0, r1              @ calculate the delta offset
 
                                                @ if delta is zero, we are
@@ -310,18 +317,17 @@ wont_overwrite:   mov     r0, r4
 LC0:           .word   LC0                     @ r1
                .word   __bss_start             @ r2
                .word   _end                    @ r3
-               .word   zreladdr                @ r4
                .word   _start                  @ r5
                .word   _image_size             @ r6
                .word   _got_start              @ r11
                .word   _got_end                @ ip
-               .word   user_stack+4096         @ sp
+               .word   user_stack_end          @ sp
 LC1:           .word   reloc_end - reloc_start
                .size   LC0, . - LC0
 
 #ifdef CONFIG_ARCH_RPC
                .globl  params
-params:                ldr     r0, =params_phys
+params:                ldr     r0, =0x10000100         @ params_phys for RPC
                mov     pc, lr
                .ltorg
                .align
@@ -339,9 +345,8 @@ params:             ldr     r0, =params_phys
  *  r4 = kernel execution address
  *  r7 = architecture number
  *  r8 = atags pointer
- *  r9 = run-time address of "start"  (???)
  * On exit,
- *  r1, r2, r3, r9, r10, r12 corrupted
+ *  r0, r1, r2, r3, r9, r10, r12 corrupted
  * This routine must preserve:
  *  r4, r5, r6, r7, r8
  */
@@ -396,12 +401,18 @@ __armv3_mpu_cache_on:
 
                mov     r0, #0
                mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
+               /*
+                * ?? ARMv3 MMU does not allow reading the control register,
+                * does this really work on ARMv3 MPU?
+                */
                mrc     p15, 0, r0, c1, c0, 0   @ read control reg
                                                @ .... .... .... WC.M
                orr     r0, r0, #0x000d         @ .... .... .... 11.1
+               /* ?? this overwrites the value constructed above? */
                mov     r0, #0
                mcr     p15, 0, r0, c1, c0, 0   @ write control reg
 
+               /* ?? invalidate for the second time? */
                mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
                mov     pc, lr
 
@@ -771,8 +782,10 @@ proc_types:
  * Turn off the Cache and MMU.  ARMv3 does not support
  * reading the control register, but ARMv4 does.
  *
- * On exit, r0, r1, r2, r3, r9, r12 corrupted
- * This routine must preserve: r4, r6, r7
+ * On exit,
+ *  r0, r1, r2, r3, r9, r12 corrupted
+ * This routine must preserve:
+ *  r4, r6, r7
  */
                .align  5
 cache_off:     mov     r3, #12                 @ cache_off function
@@ -845,7 +858,7 @@ __armv3_mmu_cache_off:
  * Clean and flush the cache to maintain consistency.
  *
  * On exit,
- *  r1, r2, r3, r9, r11, r12 corrupted
+ *  r1, r2, r3, r9, r10, r11, r12 corrupted
  * This routine must preserve:
  *  r0, r4, r5, r6, r7
  */
@@ -988,7 +1001,7 @@ no_cache_id:
 __armv3_mmu_cache_flush:
 __armv3_mpu_cache_flush:
                mov     r1, #0
-               mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
+               mcr     p15, 0, r1, c7, c0, 0   @ invalidate whole cache v3
                mov     pc, lr
 
 /*
@@ -1001,6 +1014,7 @@ __armv3_mpu_cache_flush:
 phexbuf:       .space  12
                .size   phexbuf, . - phexbuf
 
+@ phex corrupts {r0, r1, r2, r3}
 phex:          adr     r3, phexbuf
                mov     r2, #0
                strb    r2, [r3, r1]
@@ -1015,6 +1029,7 @@ phex:             adr     r3, phexbuf
                strb    r2, [r3, r1]
                b       1b
 
+@ puts corrupts {r0, r1, r2, r3}
 puts:          loadsp  r3, r1
 1:             ldrb    r2, [r0], #1
                teq     r2, #0
@@ -1029,12 +1044,14 @@ puts:           loadsp  r3, r1
                teq     r0, #0
                bne     1b
                mov     pc, lr
+@ putc corrupts {r0, r1, r2, r3}
 putc:
                mov     r2, r0
                mov     r0, #0
                loadsp  r3, r1
                b       2b
 
+@ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
 memdump:       mov     r12, r0
                mov     r10, lr
                mov     r11, #0
@@ -1070,3 +1087,4 @@ reloc_end:
                .align
                .section ".stack", "w"
 user_stack:    .space  4096
+user_stack_end:
index d2b2ef4..e653a6d 100644 (file)
@@ -28,9 +28,6 @@ unsigned int __machine_arch_type;
 
 #include <asm/unaligned.h>
 
-#ifdef STANDALONE_DEBUG
-#define putstr printf
-#else
 
 static void putstr(const char *ptr);
 extern void error(char *x);
@@ -116,7 +113,6 @@ static void putstr(const char *ptr)
        flush();
 }
 
-#endif
 
 void *memcpy(void *__dest, __const void *__src, size_t __n)
 {
@@ -186,7 +182,6 @@ asmlinkage void __div0(void)
 
 extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
 
-#ifndef STANDALONE_DEBUG
 
 unsigned long
 decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
@@ -211,18 +206,3 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
        putstr(" done, booting the kernel.\n");
        return output_ptr;
 }
-#else
-
-char output_buffer[1500*1024];
-
-int main()
-{
-       output_data = output_buffer;
-
-       putstr("Uncompressing Linux...");
-       decompress(input_data, input_data_end - input_data,
-                       NULL, NULL, output_data, NULL, error);
-       putstr("done.\n");
-       return 0;
-}
-#endif
index 337741f..7dfa9a8 100644 (file)
@@ -108,6 +108,51 @@ static void gic_unmask_irq(unsigned int irq)
        spin_unlock(&irq_controller_lock);
 }
 
+static int gic_set_type(unsigned int irq, unsigned int type)
+{
+       void __iomem *base = gic_dist_base(irq);
+       unsigned int gicirq = gic_irq(irq);
+       u32 enablemask = 1 << (gicirq % 32);
+       u32 enableoff = (gicirq / 32) * 4;
+       u32 confmask = 0x2 << ((gicirq % 16) * 2);
+       u32 confoff = (gicirq / 16) * 4;
+       bool enabled = false;
+       u32 val;
+
+       /* Interrupt configuration for SGIs can't be changed */
+       if (gicirq < 16)
+               return -EINVAL;
+
+       if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
+               return -EINVAL;
+
+       spin_lock(&irq_controller_lock);
+
+       val = readl(base + GIC_DIST_CONFIG + confoff);
+       if (type == IRQ_TYPE_LEVEL_HIGH)
+               val &= ~confmask;
+       else if (type == IRQ_TYPE_EDGE_RISING)
+               val |= confmask;
+
+       /*
+        * As recommended by the spec, disable the interrupt before changing
+        * the configuration
+        */
+       if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
+               writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
+               enabled = true;
+       }
+
+       writel(val, base + GIC_DIST_CONFIG + confoff);
+
+       if (enabled)
+               writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
+
+       spin_unlock(&irq_controller_lock);
+
+       return 0;
+}
+
 #ifdef CONFIG_SMP
 static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
 {
@@ -161,6 +206,7 @@ static struct irq_chip gic_chip = {
        .ack            = gic_ack_irq,
        .mask           = gic_mask_irq,
        .unmask         = gic_unmask_irq,
+       .set_type       = gic_set_type,
 #ifdef CONFIG_SMP
        .set_affinity   = gic_set_cpu,
 #endif
index 9eaf65f..517d50d 100644 (file)
@@ -185,13 +185,10 @@ static struct sa1111_dev_info sa1111_devices[] = {
        },
 };
 
-void __init sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes)
+void __init sa1111_adjust_zones(unsigned long *size, unsigned long *holes)
 {
        unsigned int sz = SZ_1M >> PAGE_SHIFT;
 
-       if (node != 0)
-               sz = 0;
-
        size[1] = size[0] - sz;
        size[0] = sz;
 }
index f2e3a90..ccc9c99 100644 (file)
@@ -13,11 +13,19 @@ CONFIG_MACH_RD88F6192_NAS=y
 CONFIG_MACH_RD88F6281=y
 CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
+CONFIG_MACH_ESATA_SHEEVAPLUG=y
+CONFIG_MACH_GURUPLUG=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
 CONFIG_MACH_OPENRD_BASE=y
 CONFIG_MACH_OPENRD_CLIENT=y
+CONFIG_MACH_OPENRD_ULTIMATE=y
 CONFIG_MACH_NETSPACE_V2=y
+CONFIG_MACH_INETSPACE_V2=y
+CONFIG_MACH_NETSPACE_MAX_V2=y
+CONFIG_MACH_NET2BIG_V2=y
+CONFIG_MACH_NET5BIG_V2=y
+CONFIG_MACH_T5325=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/configs/lusl7200_defconfig b/arch/arm/configs/lusl7200_defconfig
deleted file mode 100644 (file)
index 816fc42..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_HOTPLUG is not set
-CONFIG_MODULES=y
-CONFIG_ARCH_L7200=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x00010000
-CONFIG_ZBOOT_ROM_BSS=0xf03e0000
-CONFIG_ZBOOT_ROM=y
-CONFIG_CMDLINE="console=tty0 console=ttyLU1,115200 root=/dev/ram initrd=0xf1000000,0x005dac7b mem=32M"
-CONFIG_BINFMT_AOUT=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_EXT2_FS=y
-CONFIG_DEBUG_USER=y
-# CONFIG_CRC32 is not set
index 51662fe..6750b8e 100644 (file)
@@ -121,4 +121,8 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs);
 extern void elf_set_personality(const struct elf32_hdr *);
 #define SET_PERSONALITY(ex)    elf_set_personality(&(ex))
 
+struct mm_struct;
+extern unsigned long arch_randomize_brk(struct mm_struct *mm);
+#define arch_randomize_brk arch_randomize_brk
+
 #endif
index f7bd52b..c1062c3 100644 (file)
@@ -19,6 +19,7 @@
 #define HWCAP_NEON     4096
 #define HWCAP_VFPv3    8192
 #define HWCAP_VFPv3D16 16384
+#define HWCAP_TLS      32768
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 /*
index 237282f..2721a58 100644 (file)
@@ -7,6 +7,8 @@
 #define irq_canonicalize(i)    (i)
 #endif
 
+#define NR_IRQS_LEGACY 16
+
 /*
  * Use this value to indicate lack of interrupt
  * capability
index df15a0d..8ec9ef5 100644 (file)
 
 #ifndef __ASSEMBLY__
 
-struct kimage;
-/* Provide a dummy definition to avoid build failures. */
+/**
+ * crash_setup_regs() - save registers for the panic kernel
+ * @newregs: registers are saved here
+ * @oldregs: registers to be saved (may be %NULL)
+ *
+ * Function copies machine registers from @oldregs to @newregs. If @oldregs is
+ * %NULL then current registers are stored there.
+ */
 static inline void crash_setup_regs(struct pt_regs *newregs,
-                                        struct pt_regs *oldregs) { }
+                                   struct pt_regs *oldregs)
+{
+       if (oldregs) {
+               memcpy(newregs, oldregs, sizeof(*newregs));
+       } else {
+               __asm__ __volatile__ ("stmia %0, {r0 - r15}"
+                                     : : "r" (&newregs->ARM_r0));
+               __asm__ __volatile__ ("mrs %0, cpsr"
+                                     : "=r" (newregs->ARM_cpsr));
+       }
+}
 
 #endif /* __ASSEMBLY__ */
 
index c59842d..8a0dd18 100644 (file)
@@ -20,6 +20,7 @@ struct machine_desc {
         * by assembler code in head.S, head-common.S
         */
        unsigned int            nr;             /* architecture number  */
+       unsigned int            nr_irqs;        /* number of IRQs */
        unsigned int            phys_io;        /* start of physical io */
        unsigned int            io_pg_offst;    /* byte offset for io 
                                                 * page tabe entry      */
@@ -37,6 +38,7 @@ struct machine_desc {
        void                    (*fixup)(struct machine_desc *,
                                         struct tag *, char **,
                                         struct meminfo *);
+       void                    (*reserve)(void);/* reserve mem blocks  */
        void                    (*map_io)(void);/* IO mapping function  */
        void                    (*init_irq)(void);
        struct sys_timer        *timer;         /* system tick timer    */
index 8920b2d..ce3eee9 100644 (file)
@@ -17,6 +17,7 @@ struct seq_file;
 /*
  * This is internal.  Do not use it.
  */
+extern unsigned int arch_nr_irqs;
 extern void (*init_arch_irq)(void);
 extern void init_FIQ(void);
 extern int show_fiq_list(struct seq_file *, void *);
index 742c2aa..d2fedb5 100644 (file)
@@ -27,6 +27,8 @@ struct map_desc {
 #define MT_MEMORY              9
 #define MT_ROM                 10
 #define MT_MEMORY_NONCACHED    11
+#define MT_MEMORY_DTCM         12
+#define MT_MEMORY_ITCM         13
 
 #ifdef CONFIG_MMU
 extern void iotable_init(struct map_desc *, int);
index 52f0da1..16330bd 100644 (file)
@@ -46,6 +46,7 @@ struct pci_sys_data {
                                        /* IRQ mapping                          */
        int             (*map_irq)(struct pci_dev *, u8, u8);
        struct hw_pci   *hw;
+       void            *private_data;  /* platform controller private data     */
 };
 
 /*
diff --git a/arch/arm/include/asm/memblock.h b/arch/arm/include/asm/memblock.h
new file mode 100644 (file)
index 0000000..fdbc43b
--- /dev/null
@@ -0,0 +1,16 @@
+#ifndef _ASM_ARM_MEMBLOCK_H
+#define _ASM_ARM_MEMBLOCK_H
+
+#ifdef CONFIG_MMU
+extern phys_addr_t lowmem_end_addr;
+#define MEMBLOCK_REAL_LIMIT    lowmem_end_addr
+#else
+#define MEMBLOCK_REAL_LIMIT    0
+#endif
+
+struct meminfo;
+struct machine_desc;
+
+extern void arm_memblock_init(struct meminfo *, struct machine_desc *);
+
+#endif
index 4312ee5..23c2e8e 100644 (file)
 #endif /* !CONFIG_MMU */
 
 /*
+ * We fix the TCM memories max 32 KiB ITCM resp DTCM at these
+ * locations
+ */
+#ifdef CONFIG_HAVE_TCM
+#define ITCM_OFFSET    UL(0xfffe0000)
+#define DTCM_OFFSET    UL(0xfffe8000)
+#endif
+
+/*
  * Physical vs virtual RAM address space conversion.  These are
  * private definitions which should NOT be used outside memory.h
  * files.  Use virt_to_phys/phys_to_virt/__pa/__va instead.
 #endif
 
 #ifndef arch_adjust_zones
-#define arch_adjust_zones(node,size,holes) do { } while (0)
+#define arch_adjust_zones(size,holes) do { } while (0)
 #elif !defined(CONFIG_ZONE_DMA)
 #error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA"
 #endif
@@ -234,76 +243,11 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
  *  virt_to_page(k)    convert a _valid_ virtual address to struct page *
  *  virt_addr_valid(k) indicates whether a virtual address is valid
  */
-#ifndef CONFIG_DISCONTIGMEM
-
 #define ARCH_PFN_OFFSET                PHYS_PFN_OFFSET
 
 #define virt_to_page(kaddr)    pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 #define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
 
-#define PHYS_TO_NID(addr)      (0)
-
-#else /* CONFIG_DISCONTIGMEM */
-
-/*
- * This is more complex.  We have a set of mem_map arrays spread
- * around in memory.
- */
-#include <linux/numa.h>
-
-#define arch_pfn_to_nid(pfn)   PFN_TO_NID(pfn)
-#define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT)
-
-#define virt_to_page(kaddr)                                    \
-       (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
-
-#define virt_addr_valid(kaddr) (KVADDR_TO_NID(kaddr) < MAX_NUMNODES)
-
-/*
- * Common discontigmem stuff.
- *  PHYS_TO_NID is used by the ARM kernel/setup.c
- */
-#define PHYS_TO_NID(addr)      PFN_TO_NID((addr) >> PAGE_SHIFT)
-
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
-
-/*
- * Given a page frame number, find the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define PFN_TO_MAPBASE(pfn)    NODE_MEM_MAP(PFN_TO_NID(pfn))
-
-#ifdef NODE_MEM_SIZE_BITS
-#define NODE_MEM_SIZE_MASK     ((1 << NODE_MEM_SIZE_BITS) - 1)
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) \
-       (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MEM_SIZE_BITS)
-
-/*
- * Given a page frame number, convert it to a node id.
- */
-#define PFN_TO_NID(pfn) \
-       (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MEM_SIZE_BITS - PAGE_SHIFT))
-
-/*
- * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-#define LOCAL_MAP_NR(addr) \
-       (((unsigned long)(addr) & NODE_MEM_SIZE_MASK) >> PAGE_SHIFT)
-
-#endif /* NODE_MEM_SIZE_BITS */
-
-#endif /* !CONFIG_DISCONTIGMEM */
-
 /*
  * Optional coherency support.  Currently used only by selected
  * Intel XSC3-based systems.
diff --git a/arch/arm/include/asm/mmzone.h b/arch/arm/include/asm/mmzone.h
deleted file mode 100644 (file)
index ae63a4f..0000000
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- *  arch/arm/include/asm/mmzone.h
- *
- *  1999-12-29 Nicolas Pitre           Created
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_MMZONE_H
-#define __ASM_MMZONE_H
-
-/*
- * Currently defined in arch/arm/mm/discontig.c
- */
-extern pg_data_t discontig_node_data[];
-
-/*
- * Return a pointer to the node data for node n.
- */
-#define NODE_DATA(nid)         (&discontig_node_data[nid])
-
-/*
- * NODE_MEM_MAP gives the kaddr for the mem_map of the node.
- */
-#define NODE_MEM_MAP(nid)      (NODE_DATA(nid)->node_mem_map)
-
-#include <mach/memory.h>
-
-#endif
index 9dcb11e..c974be8 100644 (file)
@@ -184,6 +184,42 @@ extern unsigned long profile_pc(struct pt_regs *regs);
 #define predicate(x)           ((x) & 0xf0000000)
 #define PREDICATE_ALWAYS       0xe0000000
 
+/*
+ * kprobe-based event tracer support
+ */
+#include <linux/stddef.h>
+#include <linux/types.h>
+#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))
+
+extern int regs_query_register_offset(const char *name);
+extern const char *regs_query_register_name(unsigned int offset);
+extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
+extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
+                                              unsigned int n);
+
+/**
+ * regs_get_register() - get register value from its offset
+ * @regs:         pt_regs from which register value is gotten
+ * @offset:    offset number of the register.
+ *
+ * regs_get_register returns the value of a register whose offset from @regs.
+ * The @offset is the offset of the register in struct pt_regs.
+ * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
+ */
+static inline unsigned long regs_get_register(struct pt_regs *regs,
+                                             unsigned int offset)
+{
+       if (unlikely(offset > MAX_REG_OFFSET))
+               return 0;
+       return *(unsigned long *)((unsigned long)regs + offset);
+}
+
+/* Valid only for Kernel mode traps. */
+static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
+{
+       return regs->ARM_sp;
+}
+
 #endif /* __KERNEL__ */
 
 #endif /* __ASSEMBLY__ */
index f392fb4..f1e5a9b 100644 (file)
@@ -201,8 +201,7 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn }
 struct membank {
        unsigned long start;
        unsigned long size;
-       unsigned short node;
-       unsigned short highmem;
+       unsigned int highmem;
 };
 
 struct meminfo {
@@ -212,9 +211,8 @@ struct meminfo {
 
 extern struct meminfo meminfo;
 
-#define for_each_nodebank(iter,mi,no)                  \
-       for (iter = 0; iter < (mi)->nr_banks; iter++)   \
-               if ((mi)->bank[iter].node == no)
+#define for_each_bank(iter,mi)                         \
+       for (iter = 0; iter < (mi)->nr_banks; iter++)
 
 #define bank_pfn_start(bank)   __phys_to_pfn((bank)->start)
 #define bank_pfn_end(bank)     __phys_to_pfn((bank)->start + (bank)->size)
diff --git a/arch/arm/include/asm/stackprotector.h b/arch/arm/include/asm/stackprotector.h
new file mode 100644 (file)
index 0000000..de00332
--- /dev/null
@@ -0,0 +1,38 @@
+/*
+ * GCC stack protector support.
+ *
+ * Stack protector works by putting predefined pattern at the start of
+ * the stack frame and verifying that it hasn't been overwritten when
+ * returning from the function.  The pattern is called stack canary
+ * and gcc expects it to be defined by a global variable called
+ * "__stack_chk_guard" on ARM.  This unfortunately means that on SMP
+ * we cannot have a different canary value per task.
+ */
+
+#ifndef _ASM_STACKPROTECTOR_H
+#define _ASM_STACKPROTECTOR_H 1
+
+#include <linux/random.h>
+#include <linux/version.h>
+
+extern unsigned long __stack_chk_guard;
+
+/*
+ * Initialize the stackprotector canary value.
+ *
+ * NOTE: this must only be called from functions that never return,
+ * and it must always be inlined.
+ */
+static __always_inline void boot_init_stack_canary(void)
+{
+       unsigned long canary;
+
+       /* Try to get a semi random initial value. */
+       get_random_bytes(&canary, sizeof(canary));
+       canary ^= LINUX_VERSION_CODE;
+
+       current->stack_canary = canary;
+       __stack_chk_guard = current->stack_canary;
+}
+
+#endif /* _ASM_STACKPROTECTOR_H */
index 5f4f480..8ba1ccf 100644 (file)
@@ -83,7 +83,7 @@ void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
 
 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
                                       struct pt_regs *),
-                    int sig, const char *name);
+                    int sig, int code, const char *name);
 
 #define xchg(ptr,x) \
        ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
new file mode 100644 (file)
index 0000000..e71d6ff
--- /dev/null
@@ -0,0 +1,46 @@
+#ifndef __ASMARM_TLS_H
+#define __ASMARM_TLS_H
+
+#ifdef __ASSEMBLY__
+       .macro set_tls_none, tp, tmp1, tmp2
+       .endm
+
+       .macro set_tls_v6k, tp, tmp1, tmp2
+       mcr     p15, 0, \tp, c13, c0, 3         @ set TLS register
+       .endm
+
+       .macro set_tls_v6, tp, tmp1, tmp2
+       ldr     \tmp1, =elf_hwcap
+       ldr     \tmp1, [\tmp1, #0]
+       mov     \tmp2, #0xffff0fff
+       tst     \tmp1, #HWCAP_TLS               @ hardware TLS available?
+       mcrne   p15, 0, \tp, c13, c0, 3         @ yes, set TLS register
+       streq   \tp, [\tmp2, #-15]              @ set TLS value at 0xffff0ff0
+       .endm
+
+       .macro set_tls_software, tp, tmp1, tmp2
+       mov     \tmp1, #0xffff0fff
+       str     \tp, [\tmp1, #-15]              @ set TLS value at 0xffff0ff0
+       .endm
+#endif
+
+#ifdef CONFIG_TLS_REG_EMUL
+#define tls_emu                1
+#define has_tls_reg            1
+#define set_tls                set_tls_none
+#elif __LINUX_ARM_ARCH__ >= 7 ||                                       \
+       (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
+#define tls_emu                0
+#define has_tls_reg            1
+#define set_tls                set_tls_v6k
+#elif __LINUX_ARM_ARCH__ == 6
+#define tls_emu                0
+#define has_tls_reg            (elf_hwcap & HWCAP_TLS)
+#define set_tls                set_tls_v6
+#else
+#define tls_emu                0
+#define has_tls_reg            0
+#define set_tls                set_tls_software
+#endif
+
+#endif /* __ASMARM_TLS_H */
index 422f3cc..3d5fc41 100644 (file)
@@ -3,6 +3,8 @@
  *
  * Assembler-only file containing VFP macros and register definitions.
  */
+#include <asm/hwcap.h>
+
 #include "vfp.h"
 
 @ Macros to allow building with old toolkits (with no VFP support)
        LDC     p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d0-d15}
 #endif
 #ifdef CONFIG_VFPv3
+#if __LINUX_ARM_ARCH__ <= 6
+       ldr     \tmp, =elf_hwcap                    @ may not have MVFR regs
+       ldr     \tmp, [\tmp, #0]
+       tst     \tmp, #HWCAP_VFPv3D16
+       ldceq   p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
+       addne   \base, \base, #32*4                 @ step over unused register space
+#else
        VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
        and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
        cmp     \tmp, #2                            @ 32 x 64bit registers?
        ldceql  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
        addne   \base, \base, #32*4                 @ step over unused register space
 #endif
+#endif
        .endm
 
        @ write all the working registers out of the VFP
        STC     p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d0-d15}
 #endif
 #ifdef CONFIG_VFPv3
+#if __LINUX_ARM_ARCH__ <= 6
+       ldr     \tmp, =elf_hwcap                    @ may not have MVFR regs
+       ldr     \tmp, [\tmp, #0]
+       tst     \tmp, #HWCAP_VFPv3D16
+       stceq   p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
+       addne   \base, \base, #32*4                 @ step over unused register space
+#else
        VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
        and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
        cmp     \tmp, #2                            @ 32 x 64bit registers?
        stceql  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
        addne   \base, \base, #32*4                 @ step over unused register space
 #endif
+#endif
        .endm
index 26d302c..980b78e 100644 (file)
@@ -13,10 +13,12 @@ CFLAGS_REMOVE_return_address.o = -pg
 
 # Object file lists.
 
-obj-y          := compat.o elf.o entry-armv.o entry-common.o irq.o \
+obj-y          := elf.o entry-armv.o entry-common.o irq.o \
                   process.o ptrace.o return_address.o setup.o signal.o \
                   sys_arm.o stacktrace.o time.o traps.o
 
+obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
+
 obj-$(CONFIG_LEDS)             += leds.o
 obj-$(CONFIG_OC_ETM)           += etm.o
 
@@ -39,6 +41,7 @@ obj-$(CONFIG_ARM_THUMBEE)     += thumbee.o
 obj-$(CONFIG_KGDB)             += kgdb.o
 obj-$(CONFIG_ARM_UNWIND)       += unwind.o
 obj-$(CONFIG_HAVE_TCM)         += tcm.o
+obj-$(CONFIG_CRASH_DUMP)       += crash_dump.o
 
 obj-$(CONFIG_CRUNCH)           += crunch.o crunch-bits.o
 AFLAGS_crunch-bits.o           := -Wa,-mcpu=ep9312
index 8835115..85f2a01 100644 (file)
@@ -40,6 +40,9 @@
 int main(void)
 {
   DEFINE(TSK_ACTIVE_MM,                offsetof(struct task_struct, active_mm));
+#ifdef CONFIG_CC_STACKPROTECTOR
+  DEFINE(TSK_STACK_CANARY,     offsetof(struct task_struct, stack_canary));
+#endif
   BLANK();
   DEFINE(TI_FLAGS,             offsetof(struct thread_info, flags));
   DEFINE(TI_PREEMPT,           offsetof(struct thread_info, preempt_count));
index 0a13854..9256523 100644 (file)
@@ -217,10 +217,3 @@ void __init convert_to_tag_list(struct tag *tags)
        struct param_struct *params = (struct param_struct *)tags;
        build_tag_list(params, &params->u2);
 }
-
-void __init squash_mem_tags(struct tag *tag)
-{
-       for (; tag->hdr.size; tag = tag_next(tag))
-               if (tag->hdr.tag == ATAG_MEM)
-                       tag->hdr.tag = ATAG_NONE;
-}
index 27e61a6..39264ab 100644 (file)
@@ -9,5 +9,3 @@
 */
 
 extern void convert_to_tag_list(struct tag *tags);
-
-extern void squash_mem_tags(struct tag *tag);
diff --git a/arch/arm/kernel/crash_dump.c b/arch/arm/kernel/crash_dump.c
new file mode 100644 (file)
index 0000000..cd3b853
--- /dev/null
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/kernel/crash_dump.c
+ *
+ * Copyright (C) 2010 Nokia Corporation.
+ * Author: Mika Westerberg
+ *
+ * This code is taken from arch/x86/kernel/crash_dump_64.c
+ *   Created by: Hariprasad Nellitheertha (hari@in.ibm.com)
+ *   Copyright (C) IBM Corporation, 2004. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/errno.h>
+#include <linux/crash_dump.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+
+/* stores the physical address of elf header of crash image */
+unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX;
+
+/**
+ * copy_oldmem_page() - copy one page from old kernel memory
+ * @pfn: page frame number to be copied
+ * @buf: buffer where the copied page is placed
+ * @csize: number of bytes to copy
+ * @offset: offset in bytes into the page
+ * @userbuf: if set, @buf is int he user address space
+ *
+ * This function copies one page from old kernel memory into buffer pointed by
+ * @buf. If @buf is in userspace, set @userbuf to %1. Returns number of bytes
+ * copied or negative error in case of failure.
+ */
+ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
+                        size_t csize, unsigned long offset,
+                        int userbuf)
+{
+       void *vaddr;
+
+       if (!csize)
+               return 0;
+
+       vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
+       if (!vaddr)
+               return -ENOMEM;
+
+       if (userbuf) {
+               if (copy_to_user(buf, vaddr + offset, csize)) {
+                       iounmap(vaddr);
+                       return -EFAULT;
+               }
+       } else {
+               memcpy(buf, vaddr + offset, csize);
+       }
+
+       iounmap(vaddr);
+       return csize;
+}
index 3fd7861..bb8e93a 100644 (file)
@@ -22,6 +22,7 @@
 #include <asm/thread_notify.h>
 #include <asm/unwind.h>
 #include <asm/unistd.h>
+#include <asm/tls.h>
 
 #include "entry-header.S"
 
@@ -735,11 +736,11 @@ ENTRY(__switch_to)
 #ifdef CONFIG_MMU
        ldr     r6, [r2, #TI_CPU_DOMAIN]
 #endif
-#if defined(CONFIG_HAS_TLS_REG)
-       mcr     p15, 0, r3, c13, c0, 3          @ set TLS register
-#elif !defined(CONFIG_TLS_REG_EMUL)
-       mov     r4, #0xffff0fff
-       str     r3, [r4, #-15]                  @ TLS val at 0xffff0ff0
+       set_tls r3, r4, r5
+#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
+       ldr     r7, [r2, #TI_TASK]
+       ldr     r8, =__stack_chk_guard
+       ldr     r7, [r7, #TSK_STACK_CANARY]
 #endif
 #ifdef CONFIG_MMU
        mcr     p15, 0, r6, c3, c0, 0           @ Set domain register
@@ -749,6 +750,9 @@ ENTRY(__switch_to)
        ldr     r0, =thread_notify_head
        mov     r1, #THREAD_NOTIFY_SWITCH
        bl      atomic_notifier_call_chain
+#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
+       str     r7, [r8]
+#endif
  THUMB(        mov     ip, r4                     )
        mov     r0, r5
  ARM(  ldmia   r4, {r4 - sl, fp, sp, pc}  )    @ Load all regs saved previously
@@ -1005,17 +1009,12 @@ kuser_cmpxchg_fixup:
  */
 
 __kuser_get_tls:                               @ 0xffff0fe0
-
-#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
-       ldr     r0, [pc, #(16 - 8)]             @ TLS stored at 0xffff0ff0
-#else
-       mrc     p15, 0, r0, c13, c0, 3          @ read TLS register
-#endif
+       ldr     r0, [pc, #(16 - 8)]     @ read TLS, set in kuser_get_tls_init
        usr_ret lr
-
-       .rep    5
-       .word   0                       @ pad up to __kuser_helper_version
-       .endr
+       mrc     p15, 0, r0, c13, c0, 3  @ 0xffff0fe8 hardware TLS code
+       .rep    4
+       .word   0                       @ 0xffff0ff0 software TLS value, then
+       .endr                           @ pad up to __kuser_helper_version
 
 /*
  * Reference declaration:
index 3b3d2c8..c0d5c3b 100644 (file)
 #define irq_finish(irq) do { } while (0)
 #endif
 
+unsigned int arch_nr_irqs;
 void (*init_arch_irq)(void) __initdata = NULL;
 unsigned long irq_err_count;
 
 int show_interrupts(struct seq_file *p, void *v)
 {
        int i = *(loff_t *) v, cpu;
+       struct irq_desc *desc;
        struct irqaction * action;
        unsigned long flags;
 
@@ -67,24 +69,25 @@ int show_interrupts(struct seq_file *p, void *v)
                seq_putc(p, '\n');
        }
 
-       if (i < NR_IRQS) {
-               raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
-               action = irq_desc[i].action;
+       if (i < nr_irqs) {
+               desc = irq_to_desc(i);
+               raw_spin_lock_irqsave(&desc->lock, flags);
+               action = desc->action;
                if (!action)
                        goto unlock;
 
                seq_printf(p, "%3d: ", i);
                for_each_present_cpu(cpu)
                        seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
-               seq_printf(p, " %10s", irq_desc[i].chip->name ? : "-");
+               seq_printf(p, " %10s", desc->chip->name ? : "-");
                seq_printf(p, "  %s", action->name);
                for (action = action->next; action; action = action->next)
                        seq_printf(p, ", %s", action->name);
 
                seq_putc(p, '\n');
 unlock:
-               raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
-       } else if (i == NR_IRQS) {
+               raw_spin_unlock_irqrestore(&desc->lock, flags);
+       } else if (i == nr_irqs) {
 #ifdef CONFIG_FIQ
                show_fiq_list(p, v);
 #endif
@@ -112,7 +115,7 @@ asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
         * Some hardware gives randomly wrong interrupts.  Rather
         * than crashing, do something sensible.
         */
-       if (unlikely(irq >= NR_IRQS)) {
+       if (unlikely(irq >= nr_irqs)) {
                if (printk_ratelimit())
                        printk(KERN_WARNING "Bad IRQ%u\n", irq);
                ack_bad_irq(irq);
@@ -132,12 +135,12 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
        struct irq_desc *desc;
        unsigned long flags;
 
-       if (irq >= NR_IRQS) {
+       if (irq >= nr_irqs) {
                printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq);
                return;
        }
 
-       desc = irq_desc + irq;
+       desc = irq_to_desc(irq);
        raw_spin_lock_irqsave(&desc->lock, flags);
        desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
        if (iflags & IRQF_VALID)
@@ -151,14 +154,25 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
 
 void __init init_IRQ(void)
 {
+       struct irq_desc *desc;
        int irq;
 
-       for (irq = 0; irq < NR_IRQS; irq++)
-               irq_desc[irq].status |= IRQ_NOREQUEST | IRQ_NOPROBE;
+       for (irq = 0; irq < nr_irqs; irq++) {
+               desc = irq_to_desc_alloc_node(irq, 0);
+               desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE;
+       }
 
        init_arch_irq();
 }
 
+#ifdef CONFIG_SPARSE_IRQ
+int __init arch_probe_nr_irqs(void)
+{
+       nr_irqs = arch_nr_irqs ? arch_nr_irqs : NR_IRQS;
+       return 0;
+}
+#endif
+
 #ifdef CONFIG_HOTPLUG_CPU
 
 static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
@@ -178,10 +192,9 @@ static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
 void migrate_irqs(void)
 {
        unsigned int i, cpu = smp_processor_id();
+       struct irq_desc *desc;
 
-       for (i = 0; i < NR_IRQS; i++) {
-               struct irq_desc *desc = irq_desc + i;
-
+       for_each_irq_desc(i, desc) {
                if (desc->node == cpu) {
                        unsigned int newcpu = cpumask_any_and(desc->affinity,
                                                              cpu_online_mask);
index 598ca61..1fc74cb 100644 (file)
@@ -37,12 +37,12 @@ void machine_kexec_cleanup(struct kimage *image)
 {
 }
 
-void machine_shutdown(void)
-{
-}
-
 void machine_crash_shutdown(struct pt_regs *regs)
 {
+       local_irq_disable();
+       crash_save_cpu(regs, smp_processor_id());
+
+       printk(KERN_INFO "Loading crashdump kernel...\n");
 }
 
 void machine_kexec(struct kimage *image)
@@ -74,7 +74,11 @@ void machine_kexec(struct kimage *image)
                           (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
        printk(KERN_INFO "Bye!\n");
 
-       cpu_proc_fin();
+       local_irq_disable();
+       local_fiq_disable();
        setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
+       flush_cache_all();
+       cpu_proc_fin();
+       flush_cache_all();
        cpu_reset(reboot_code_buffer_phys);
 }
index a4a9cc8..401e38b 100644 (file)
@@ -28,7 +28,9 @@
 #include <linux/tick.h>
 #include <linux/utsname.h>
 #include <linux/uaccess.h>
+#include <linux/random.h>
 
+#include <asm/cacheflush.h>
 #include <asm/leds.h>
 #include <asm/processor.h>
 #include <asm/system.h>
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
 
+#ifdef CONFIG_CC_STACKPROTECTOR
+#include <linux/stackprotector.h>
+unsigned long __stack_chk_guard __read_mostly;
+EXPORT_SYMBOL(__stack_chk_guard);
+#endif
+
 static const char *processor_modes[] = {
   "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
   "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
@@ -84,10 +92,9 @@ __setup("hlt", hlt_setup);
 
 void arm_machine_restart(char mode, const char *cmd)
 {
-       /*
-        * Clean and disable cache, and turn off interrupts
-        */
-       cpu_proc_fin();
+       /* Disable interrupts first */
+       local_irq_disable();
+       local_fiq_disable();
 
        /*
         * Tell the mm system that we are going to reboot -
@@ -96,6 +103,15 @@ void arm_machine_restart(char mode, const char *cmd)
         */
        setup_mm_for_reboot(mode);
 
+       /* Clean and invalidate caches */
+       flush_cache_all();
+
+       /* Turn off caching */
+       cpu_proc_fin();
+
+       /* Push out any further dirty data, and ensure cache is empty */
+       flush_cache_all();
+
        /*
         * Now call the architecture specific reboot code.
         */
@@ -189,19 +205,29 @@ int __init reboot_setup(char *str)
 
 __setup("reboot=", reboot_setup);
 
-void machine_halt(void)
+void machine_shutdown(void)
 {
+#ifdef CONFIG_SMP
+       smp_send_stop();
+#endif
 }
 
+void machine_halt(void)
+{
+       machine_shutdown();
+       while (1);
+}
 
 void machine_power_off(void)
 {
+       machine_shutdown();
        if (pm_power_off)
                pm_power_off();
 }
 
 void machine_restart(char *cmd)
 {
+       machine_shutdown();
        arm_pm_restart(reboot_mode, cmd);
 }
 
@@ -426,3 +452,9 @@ unsigned long get_wchan(struct task_struct *p)
        } while (count ++ < 16);
        return 0;
 }
+
+unsigned long arch_randomize_brk(struct mm_struct *mm)
+{
+       unsigned long range_end = mm->brk + 0x02000000;
+       return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
+}
index 3f562a7..f99d489 100644 (file)
 #define BREAKINST_THUMB        0xde01
 #endif
 
+struct pt_regs_offset {
+       const char *name;
+       int offset;
+};
+
+#define REG_OFFSET_NAME(r) \
+       {.name = #r, .offset = offsetof(struct pt_regs, ARM_##r)}
+#define REG_OFFSET_END {.name = NULL, .offset = 0}
+
+static const struct pt_regs_offset regoffset_table[] = {
+       REG_OFFSET_NAME(r0),
+       REG_OFFSET_NAME(r1),
+       REG_OFFSET_NAME(r2),
+       REG_OFFSET_NAME(r3),
+       REG_OFFSET_NAME(r4),
+       REG_OFFSET_NAME(r5),
+       REG_OFFSET_NAME(r6),
+       REG_OFFSET_NAME(r7),
+       REG_OFFSET_NAME(r8),
+       REG_OFFSET_NAME(r9),
+       REG_OFFSET_NAME(r10),
+       REG_OFFSET_NAME(fp),
+       REG_OFFSET_NAME(ip),
+       REG_OFFSET_NAME(sp),
+       REG_OFFSET_NAME(lr),
+       REG_OFFSET_NAME(pc),
+       REG_OFFSET_NAME(cpsr),
+       REG_OFFSET_NAME(ORIG_r0),
+       REG_OFFSET_END,
+};
+
+/**
+ * regs_query_register_offset() - query register offset from its name
+ * @name:      the name of a register
+ *
+ * regs_query_register_offset() returns the offset of a register in struct
+ * pt_regs from its name. If the name is invalid, this returns -EINVAL;
+ */
+int regs_query_register_offset(const char *name)
+{
+       const struct pt_regs_offset *roff;
+       for (roff = regoffset_table; roff->name != NULL; roff++)
+               if (!strcmp(roff->name, name))
+                       return roff->offset;
+       return -EINVAL;
+}
+
+/**
+ * regs_query_register_name() - query register name from its offset
+ * @offset:    the offset of a register in struct pt_regs.
+ *
+ * regs_query_register_name() returns the name of a register from its
+ * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
+ */
+const char *regs_query_register_name(unsigned int offset)
+{
+       const struct pt_regs_offset *roff;
+       for (roff = regoffset_table; roff->name != NULL; roff++)
+               if (roff->offset == offset)
+                       return roff->name;
+       return NULL;
+}
+
+/**
+ * regs_within_kernel_stack() - check the address in the stack
+ * @regs:      pt_regs which contains kernel stack pointer.
+ * @addr:      address which is checked.
+ *
+ * regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
+ * If @addr is within the kernel stack, it returns true. If not, returns false.
+ */
+bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr)
+{
+       return ((addr & ~(THREAD_SIZE - 1))  ==
+               (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
+}
+
+/**
+ * regs_get_kernel_stack_nth() - get Nth entry of the stack
+ * @regs:      pt_regs which contains kernel stack pointer.
+ * @n:         stack entry number.
+ *
+ * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
+ * is specified by @regs. If the @n th entry is NOT in the kernel stack,
+ * this returns 0.
+ */
+unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n)
+{
+       unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
+       addr += n;
+       if (regs_within_kernel_stack(regs, (unsigned long)addr))
+               return *addr;
+       else
+               return 0;
+}
+
 /*
  * this routine will get a word off of the processes privileged stack.
  * the offset is how far from the base addr as stored in the THREAD.
index 61930eb..fd26f8d 100644 (file)
@@ -10,6 +10,12 @@ relocate_new_kernel:
        ldr     r0,kexec_indirection_page
        ldr     r1,kexec_start_address
 
+       /*
+        * If there is no indirection page (we are doing crashdumps)
+        * skip any relocation.
+        */
+       cmp     r0, #0
+       beq     2f
 
 0:     /* top, read another word for the indirection page */
        ldr     r3, [r0],#4
index 122d999..d5231ae 100644 (file)
 #include <linux/seq_file.h>
 #include <linux/screen_info.h>
 #include <linux/init.h>
+#include <linux/kexec.h>
+#include <linux/crash_dump.h>
 #include <linux/root_dev.h>
 #include <linux/cpu.h>
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 #include <linux/fs.h>
 #include <linux/proc_fs.h>
+#include <linux/memblock.h>
 
 #include <asm/unified.h>
 #include <asm/cpu.h>
@@ -44,7 +47,9 @@
 #include <asm/traps.h>
 #include <asm/unwind.h>
 
+#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
 #include "compat.h"
+#endif
 #include "atags.h"
 #include "tcm.h"
 
@@ -269,6 +274,21 @@ static void __init cacheid_init(void)
 extern struct proc_info_list *lookup_processor_type(unsigned int);
 extern struct machine_desc *lookup_machine_type(unsigned int);
 
+static void __init feat_v6_fixup(void)
+{
+       int id = read_cpuid_id();
+
+       if ((id & 0xff0f0000) != 0x41070000)
+               return;
+
+       /*
+        * HWCAP_TLS is available only on 1136 r1p0 and later,
+        * see also kuser_get_tls_init.
+        */
+       if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0))
+               elf_hwcap &= ~HWCAP_TLS;
+}
+
 static void __init setup_processor(void)
 {
        struct proc_info_list *list;
@@ -311,6 +331,8 @@ static void __init setup_processor(void)
        elf_hwcap &= ~HWCAP_THUMB;
 #endif
 
+       feat_v6_fixup();
+
        cacheid_init();
        cpu_proc_init();
 }
@@ -402,13 +424,12 @@ static int __init arm_add_memory(unsigned long start, unsigned long size)
        size -= start & ~PAGE_MASK;
        bank->start = PAGE_ALIGN(start);
        bank->size  = size & PAGE_MASK;
-       bank->node  = PHYS_TO_NID(start);
 
        /*
         * Check whether this memory region has non-zero size or
         * invalid node number.
         */
-       if (bank->size == 0 || bank->node >= MAX_NUMNODES)
+       if (bank->size == 0)
                return -EINVAL;
 
        meminfo.nr_banks++;
@@ -663,6 +684,86 @@ static int __init customize_machine(void)
 }
 arch_initcall(customize_machine);
 
+#ifdef CONFIG_KEXEC
+static inline unsigned long long get_total_mem(void)
+{
+       unsigned long total;
+
+       total = max_low_pfn - min_low_pfn;
+       return total << PAGE_SHIFT;
+}
+
+/**
+ * reserve_crashkernel() - reserves memory are for crash kernel
+ *
+ * This function reserves memory area given in "crashkernel=" kernel command
+ * line parameter. The memory reserved is used by a dump capture kernel when
+ * primary kernel is crashing.
+ */
+static void __init reserve_crashkernel(void)
+{
+       unsigned long long crash_size, crash_base;
+       unsigned long long total_mem;
+       int ret;
+
+       total_mem = get_total_mem();
+       ret = parse_crashkernel(boot_command_line, total_mem,
+                               &crash_size, &crash_base);
+       if (ret)
+               return;
+
+       ret = reserve_bootmem(crash_base, crash_size, BOOTMEM_EXCLUSIVE);
+       if (ret < 0) {
+               printk(KERN_WARNING "crashkernel reservation failed - "
+                      "memory is in use (0x%lx)\n", (unsigned long)crash_base);
+               return;
+       }
+
+       printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
+              "for crashkernel (System RAM: %ldMB)\n",
+              (unsigned long)(crash_size >> 20),
+              (unsigned long)(crash_base >> 20),
+              (unsigned long)(total_mem >> 20));
+
+       crashk_res.start = crash_base;
+       crashk_res.end = crash_base + crash_size - 1;
+       insert_resource(&iomem_resource, &crashk_res);
+}
+#else
+static inline void reserve_crashkernel(void) {}
+#endif /* CONFIG_KEXEC */
+
+/*
+ * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by
+ * is_kdump_kernel() to determine if we are booting after a panic. Hence
+ * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE.
+ */
+
+#ifdef CONFIG_CRASH_DUMP
+/*
+ * elfcorehdr= specifies the location of elf core header stored by the crashed
+ * kernel. This option will be passed by kexec loader to the capture kernel.
+ */
+static int __init setup_elfcorehdr(char *arg)
+{
+       char *end;
+
+       if (!arg)
+               return -EINVAL;
+
+       elfcorehdr_addr = memparse(arg, &end);
+       return end > arg ? 0 : -EINVAL;
+}
+early_param("elfcorehdr", setup_elfcorehdr);
+#endif /* CONFIG_CRASH_DUMP */
+
+static void __init squash_mem_tags(struct tag *tag)
+{
+       for (; tag->hdr.size; tag = tag_next(tag))
+               if (tag->hdr.tag == ATAG_MEM)
+                       tag->hdr.tag = ATAG_NONE;
+}
+
 void __init setup_arch(char **cmdline_p)
 {
        struct tag *tags = (struct tag *)&init_tags;
@@ -683,12 +784,14 @@ void __init setup_arch(char **cmdline_p)
        else if (mdesc->boot_params)
                tags = phys_to_virt(mdesc->boot_params);
 
+#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
        /*
         * If we have the old style parameters, convert them to
         * a tag list.
         */
        if (tags->hdr.tag != ATAG_CORE)
                convert_to_tag_list(tags);
+#endif
        if (tags->hdr.tag != ATAG_CORE)
                tags = (struct tag *)&init_tags;
 
@@ -716,12 +819,15 @@ void __init setup_arch(char **cmdline_p)
 
        parse_early_param();
 
+       arm_memblock_init(&meminfo, mdesc);
+
        paging_init(mdesc);
        request_standard_resources(&meminfo, mdesc);
 
 #ifdef CONFIG_SMP
        smp_init_cpus();
 #endif
+       reserve_crashkernel();
 
        cpu_init();
        tcm_init();
@@ -729,6 +835,7 @@ void __init setup_arch(char **cmdline_p)
        /*
         * Set up various architecture-specific pointers
         */
+       arch_nr_irqs = mdesc->nr_irqs;
        init_arch_irq = mdesc->init_irq;
        system_timer = mdesc->timer;
        init_machine = mdesc->init_machine;
index b8c3d0f..40dc74f 100644 (file)
@@ -429,7 +429,11 @@ static void smp_timer_broadcast(const struct cpumask *mask)
 {
        send_ipi_message(mask, IPI_TIMER);
 }
+#else
+#define smp_timer_broadcast    NULL
+#endif
 
+#ifndef CONFIG_LOCAL_TIMERS
 static void broadcast_timer_set_mode(enum clock_event_mode mode,
        struct clock_event_device *evt)
 {
@@ -444,7 +448,6 @@ static void local_timer_setup(struct clock_event_device *evt)
        evt->rating     = 400;
        evt->mult       = 1;
        evt->set_mode   = broadcast_timer_set_mode;
-       evt->broadcast  = smp_timer_broadcast;
 
        clockevents_register_device(evt);
 }
@@ -456,6 +459,7 @@ void __cpuinit percpu_timer_setup(void)
        struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
 
        evt->cpumask = cpumask_of(cpu);
+       evt->broadcast = smp_timer_broadcast;
 
        local_timer_setup(evt);
 }
@@ -467,10 +471,13 @@ static DEFINE_SPINLOCK(stop_lock);
  */
 static void ipi_cpu_stop(unsigned int cpu)
 {
-       spin_lock(&stop_lock);
-       printk(KERN_CRIT "CPU%u: stopping\n", cpu);
-       dump_stack();
-       spin_unlock(&stop_lock);
+       if (system_state == SYSTEM_BOOTING ||
+           system_state == SYSTEM_RUNNING) {
+               spin_lock(&stop_lock);
+               printk(KERN_CRIT "CPU%u: stopping\n", cpu);
+               dump_stack();
+               spin_unlock(&stop_lock);
+       }
 
        set_cpu_online(cpu, false);
 
index 7c5f0c0..35882fb 100644 (file)
@@ -132,7 +132,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
        twd_calibrate_rate();
 
        clk->name = "local_timer";
-       clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+       clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
+                       CLOCK_EVT_FEAT_C3STOP;
        clk->rating = 350;
        clk->set_mode = twd_set_mode;
        clk->set_next_event = twd_set_next_event;
index e503038..26685c2 100644 (file)
 #include <linux/ioport.h>
 #include <linux/genalloc.h>
 #include <linux/string.h> /* memcpy */
-#include <asm/page.h> /* PAGE_SHIFT */
 #include <asm/cputype.h>
 #include <asm/mach/map.h>
 #include <mach/memory.h>
 #include "tcm.h"
 
-/* Scream and warn about misuse */
-#if !defined(ITCM_OFFSET) || !defined(ITCM_END) || \
-    !defined(DTCM_OFFSET) || !defined(DTCM_END)
-#error "TCM support selected but offsets not defined!"
-#endif
-
 static struct gen_pool *tcm_pool;
 
 /* TCM section definitions from the linker */
 extern char __itcm_start, __sitcm_text, __eitcm_text;
 extern char __dtcm_start, __sdtcm_data, __edtcm_data;
 
+/* These will be increased as we run */
+u32 dtcm_end = DTCM_OFFSET;
+u32 itcm_end = ITCM_OFFSET;
+
 /*
  * TCM memory resources
  */
 static struct resource dtcm_res = {
        .name = "DTCM RAM",
        .start = DTCM_OFFSET,
-       .end = DTCM_END,
+       .end = DTCM_OFFSET,
        .flags = IORESOURCE_MEM
 };
 
 static struct resource itcm_res = {
        .name = "ITCM RAM",
        .start = ITCM_OFFSET,
-       .end = ITCM_END,
+       .end = ITCM_OFFSET,
        .flags = IORESOURCE_MEM
 };
 
@@ -52,8 +49,8 @@ static struct map_desc dtcm_iomap[] __initdata = {
        {
                .virtual        = DTCM_OFFSET,
                .pfn            = __phys_to_pfn(DTCM_OFFSET),
-               .length         = (DTCM_END - DTCM_OFFSET + 1),
-               .type           = MT_UNCACHED
+               .length         = 0,
+               .type           = MT_MEMORY_DTCM
        }
 };
 
@@ -61,8 +58,8 @@ static struct map_desc itcm_iomap[] __initdata = {
        {
                .virtual        = ITCM_OFFSET,
                .pfn            = __phys_to_pfn(ITCM_OFFSET),
-               .length         = (ITCM_END - ITCM_OFFSET + 1),
-               .type           = MT_UNCACHED
+               .length         = 0,
+               .type           = MT_MEMORY_ITCM
        }
 };
 
@@ -93,14 +90,24 @@ void tcm_free(void *addr, size_t len)
 }
 EXPORT_SYMBOL(tcm_free);
 
-
-static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
+static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks,
+                                 u32 *offset)
 {
        const int tcm_sizes[16] = { 0, -1, -1, 4, 8, 16, 32, 64, 128,
                                    256, 512, 1024, -1, -1, -1, -1 };
        u32 tcm_region;
        int tcm_size;
 
+       /*
+        * If there are more than one TCM bank of this type,
+        * select the TCM bank to operate on in the TCM selection
+        * register.
+        */
+       if (banks > 1)
+               asm("mcr        p15, 0, %0, c9, c2, 0"
+                   : /* No output operands */
+                   : "r" (bank));
+
        /* Read the special TCM region register c9, 0 */
        if (!type)
                asm("mrc        p15, 0, %0, c9, c1, 0"
@@ -111,26 +118,24 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
 
        tcm_size = tcm_sizes[(tcm_region >> 2) & 0x0f];
        if (tcm_size < 0) {
-               pr_err("CPU: %sTCM of unknown size!\n",
-                       type ? "I" : "D");
+               pr_err("CPU: %sTCM%d of unknown size\n",
+                      type ? "I" : "D", bank);
+               return -EINVAL;
+       } else if (tcm_size > 32) {
+               pr_err("CPU: %sTCM%d larger than 32k found\n",
+                      type ? "I" : "D", bank);
+               return -EINVAL;
        } else {
-               pr_info("CPU: found %sTCM %dk @ %08x, %senabled\n",
+               pr_info("CPU: found %sTCM%d %dk @ %08x, %senabled\n",
                        type ? "I" : "D",
+                       bank,
                        tcm_size,
                        (tcm_region & 0xfffff000U),
                        (tcm_region & 1) ? "" : "not ");
        }
 
-       if (tcm_size != expected_size) {
-               pr_crit("CPU: %sTCM was detected %dk but expected %dk!\n",
-                      type ? "I" : "D",
-                      tcm_size,
-                      expected_size);
-               /* Adjust to the expected size? what can we do... */
-       }
-
        /* Force move the TCM bank to where we want it, enable */
-       tcm_region = offset | (tcm_region & 0x00000ffeU) | 1;
+       tcm_region = *offset | (tcm_region & 0x00000ffeU) | 1;
 
        if (!type)
                asm("mcr        p15, 0, %0, c9, c1, 0"
@@ -141,10 +146,15 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
                    : /* No output operands */
                    : "r" (tcm_region));
 
-       pr_debug("CPU: moved %sTCM %dk to %08x, enabled\n",
-                type ? "I" : "D",
-                tcm_size,
-                (tcm_region & 0xfffff000U));
+       /* Increase offset */
+       *offset += (tcm_size << 10);
+
+       pr_info("CPU: moved %sTCM%d %dk to %08x, enabled\n",
+               type ? "I" : "D",
+               bank,
+               tcm_size,
+               (tcm_region & 0xfffff000U));
+       return 0;
 }
 
 /*
@@ -153,34 +163,52 @@ static void __init setup_tcm_bank(u8 type, u32 offset, u32 expected_size)
 void __init tcm_init(void)
 {
        u32 tcm_status = read_cpuid_tcmstatus();
+       u8 dtcm_banks = (tcm_status >> 16) & 0x03;
+       u8 itcm_banks = (tcm_status & 0x03);
        char *start;
        char *end;
        char *ram;
+       int ret;
+       int i;
 
        /* Setup DTCM if present */
-       if (tcm_status & (1 << 16)) {
-               setup_tcm_bank(0, DTCM_OFFSET,
-                              (DTCM_END - DTCM_OFFSET + 1) >> 10);
+       if (dtcm_banks > 0) {
+               for (i = 0; i < dtcm_banks; i++) {
+                       ret = setup_tcm_bank(0, i, dtcm_banks, &dtcm_end);
+                       if (ret)
+                               return;
+               }
+               dtcm_res.end = dtcm_end - 1;
                request_resource(&iomem_resource, &dtcm_res);
+               dtcm_iomap[0].length = dtcm_end - DTCM_OFFSET;
                iotable_init(dtcm_iomap, 1);
                /* Copy data from RAM to DTCM */
                start = &__sdtcm_data;
                end   = &__edtcm_data;
                ram   = &__dtcm_start;
+               /* This means you compiled more code than fits into DTCM */
+               BUG_ON((end - start) > (dtcm_end - DTCM_OFFSET));
                memcpy(start, ram, (end-start));
                pr_debug("CPU DTCM: copied data from %p - %p\n", start, end);
        }
 
        /* Setup ITCM if present */
-       if (tcm_status & 1) {
-               setup_tcm_bank(1, ITCM_OFFSET,
-                              (ITCM_END - ITCM_OFFSET + 1) >> 10);
+       if (itcm_banks > 0) {
+               for (i = 0; i < itcm_banks; i++) {
+                       ret = setup_tcm_bank(1, i, itcm_banks, &itcm_end);
+                       if (ret)
+                               return;
+               }
+               itcm_res.end = itcm_end - 1;
                request_resource(&iomem_resource, &itcm_res);
+               itcm_iomap[0].length = itcm_end - ITCM_OFFSET;
                iotable_init(itcm_iomap, 1);
                /* Copy code from RAM to ITCM */
                start = &__sitcm_text;
                end   = &__eitcm_text;
                ram   = &__itcm_start;
+               /* This means you compiled more code than fits into ITCM */
+               BUG_ON((end - start) > (itcm_end - ITCM_OFFSET));
                memcpy(start, ram, (end-start));
                pr_debug("CPU ITCM: copied code from %p - %p\n", start, end);
        }
@@ -208,10 +236,10 @@ static int __init setup_tcm_pool(void)
        pr_debug("Setting up TCM memory pool\n");
 
        /* Add the rest of DTCM to the TCM pool */
-       if (tcm_status & (1 << 16)) {
-               if (dtcm_pool_start < DTCM_END) {
+       if (tcm_status & (0x03 << 16)) {
+               if (dtcm_pool_start < dtcm_end) {
                        ret = gen_pool_add(tcm_pool, dtcm_pool_start,
-                                          DTCM_END - dtcm_pool_start + 1, -1);
+                                          dtcm_end - dtcm_pool_start, -1);
                        if (ret) {
                                pr_err("CPU DTCM: could not add DTCM " \
                                       "remainder to pool!\n");
@@ -219,16 +247,16 @@ static int __init setup_tcm_pool(void)
                        }
                        pr_debug("CPU DTCM: Added %08x bytes @ %08x to " \
                                 "the TCM memory pool\n",
-                                DTCM_END - dtcm_pool_start + 1,
+                                dtcm_end - dtcm_pool_start,
                                 dtcm_pool_start);
                }
        }
 
        /* Add the rest of ITCM to the TCM pool */
-       if (tcm_status & 1) {
-               if (itcm_pool_start < ITCM_END) {
+       if (tcm_status & 0x03) {
+               if (itcm_pool_start < itcm_end) {
                        ret = gen_pool_add(tcm_pool, itcm_pool_start,
-                                          ITCM_END - itcm_pool_start + 1, -1);
+                                          itcm_end - itcm_pool_start, -1);
                        if (ret) {
                                pr_err("CPU ITCM: could not add ITCM " \
                                       "remainder to pool!\n");
@@ -236,7 +264,7 @@ static int __init setup_tcm_pool(void)
                        }
                        pr_debug("CPU ITCM: Added %08x bytes @ %08x to " \
                                 "the TCM memory pool\n",
-                                ITCM_END - itcm_pool_start + 1,
+                                itcm_end - itcm_pool_start,
                                 itcm_pool_start);
                }
        }
index 1621e53..cda78d5 100644 (file)
@@ -30,6 +30,7 @@
 #include <asm/unistd.h>
 #include <asm/traps.h>
 #include <asm/unwind.h>
+#include <asm/tls.h>
 
 #include "ptrace.h"
 #include "signal.h"
@@ -518,17 +519,20 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 
        case NR(set_tls):
                thread->tp_value = regs->ARM_r0;
-#if defined(CONFIG_HAS_TLS_REG)
-               asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) );
-#elif !defined(CONFIG_TLS_REG_EMUL)
-               /*
-                * User space must never try to access this directly.
-                * Expect your app to break eventually if you do so.
-                * The user helper at 0xffff0fe0 must be used instead.
-                * (see entry-armv.S for details)
-                */
-               *((unsigned int *)0xffff0ff0) = regs->ARM_r0;
-#endif
+               if (tls_emu)
+                       return 0;
+               if (has_tls_reg) {
+                       asm ("mcr p15, 0, %0, c13, c0, 3"
+                               : : "r" (regs->ARM_r0));
+               } else {
+                       /*
+                        * User space must never try to access this directly.
+                        * Expect your app to break eventually if you do so.
+                        * The user helper at 0xffff0fe0 must be used instead.
+                        * (see entry-armv.S for details)
+                        */
+                       *((unsigned int *)0xffff0ff0) = regs->ARM_r0;
+               }
                return 0;
 
 #ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG
@@ -743,6 +747,16 @@ void __init trap_init(void)
        return;
 }
 
+static void __init kuser_get_tls_init(unsigned long vectors)
+{
+       /*
+        * vectors + 0xfe0 = __kuser_get_tls
+        * vectors + 0xfe8 = hardware TLS instruction at 0xffff0fe8
+        */
+       if (tls_emu || has_tls_reg)
+               memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4);
+}
+
 void __init early_trap_init(void)
 {
        unsigned long vectors = CONFIG_VECTORS_BASE;
@@ -761,6 +775,11 @@ void __init early_trap_init(void)
        memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);
 
        /*
+        * Do processor specific fixups for the kuser helpers
+        */
+       kuser_get_tls_init(vectors);
+
+       /*
         * Copy signal return handlers into the vector page, and
         * set sigreturn to be a pointer to these.
         */
index 030ba72..59ff42d 100644 (file)
@@ -41,7 +41,6 @@ else
 endif
 
 lib-$(CONFIG_ARCH_RPC)         += ecard.o io-acorn.o floppydma.o
-lib-$(CONFIG_ARCH_L7200)       += io-acorn.o
 lib-$(CONFIG_ARCH_SHARK)       += io-shark.o
 
 $(obj)/csumpartialcopy.o:      $(obj)/csumpartialcopygeneric.S
index c008225..4f93c56 100644 (file)
 
 #define PHYS_OFFSET    UL(0xf0000000)
 
-/*
- * The nodes are the followings:
- *
- *   node 0: 0xf000.0000 - 0xf3ff.ffff
- *   node 1: 0xf400.0000 - 0xf7ff.ffff
- *   node 2: 0xf800.0000 - 0xfbff.ffff
- *   node 3: 0xfc00.0000 - 0xffff.ffff
- */
-#define NODE_MEM_SIZE_BITS     26
-
 #endif /* __ASM_ARCH_MEMORY_H */
index 841eaf8..939bccd 100644 (file)
@@ -366,6 +366,17 @@ config MACH_STAMP9G20
 
 endif
 
+if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
+comment "AT91SAM9260/AT91SAM9G20 boards"
+
+config MACH_SNAPPER_9260
+        bool "Bluewater Systems Snapper 9260/9G20 module"
+        help
+          Select this if you are using the Bluewater Systems Snapper 9260 or
+          Snapper 9G20 modules.
+          <http://www.bluewatersys.com/>
+endif
+
 # ----------------------------------------------------------
 
 if ARCH_AT91SAM9G45
index c1f821e..ca2ac00 100644 (file)
@@ -66,6 +66,9 @@ obj-$(CONFIG_MACH_CPU9G20)    += board-cpu9krea.o
 obj-$(CONFIG_MACH_STAMP9G20)   += board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)   += board-stamp9g20.o
 
+# AT91SAM9260/AT91SAM9G20 board-specific support
+obj-$(CONFIG_MACH_SNAPPER_9260)        += board-snapper9260.o
+
 # AT91SAM9G45 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
 
index 85166b7..753c0d3 100644 (file)
@@ -20,6 +20,7 @@
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
 #include <mach/at91_shdwc.h>
+#include <mach/cpu.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -176,6 +177,13 @@ static struct clk mmc1_clk = {
        .type           = CLK_TYPE_PERIPHERAL,
 };
 
+/* Video decoder clock - Only for sam9m10/sam9m11 */
+static struct clk vdec_clk = {
+       .name           = "vdec_clk",
+       .pmc_mask       = 1 << AT91SAM9G45_ID_VDEC,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+
 /* One additional fake clock for ohci */
 static struct clk ohci_clk = {
        .name           = "ohci_clk",
@@ -239,6 +247,9 @@ static void __init at91sam9g45_register_clocks(void)
        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
                clk_register(periph_clocks[i]);
 
+       if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
+               clk_register(&vdec_clk);
+
        clk_register(&pck0);
        clk_register(&pck1);
 }
index a4102d7..c49f5c0 100644 (file)
@@ -26,6 +26,9 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/at73c213.h>
 #include <linux/clk.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/consumer.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -235,6 +238,46 @@ static struct gpio_led ek_leds[] = {
        }
 };
 
+#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
+static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
+       REGULATOR_SUPPLY("AVDD", "0-001b"),
+       REGULATOR_SUPPLY("HPVDD", "0-001b"),
+       REGULATOR_SUPPLY("DBVDD", "0-001b"),
+       REGULATOR_SUPPLY("DCVDD", "0-001b"),
+};
+
+static struct regulator_init_data ek_avdd_reg_init_data = {
+       .constraints    = {
+               .name   = "3V3",
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+       },
+       .consumer_supplies = ek_audio_consumer_supplies,
+       .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
+};
+
+static struct fixed_voltage_config ek_vdd_pdata = {
+       .supply_name    = "board-3V3",
+       .microvolts     = 3300000,
+       .gpio           = -EINVAL,
+       .enabled_at_boot = 0,
+       .init_data      = &ek_avdd_reg_init_data,
+};
+static struct platform_device ek_voltage_regulator = {
+       .name           = "reg-fixed-voltage",
+       .id             = -1,
+       .num_resources  = 0,
+       .dev            = {
+               .platform_data  = &ek_vdd_pdata,
+       },
+};
+static void __init ek_add_regulators(void)
+{
+       platform_device_register(&ek_voltage_regulator);
+}
+#else
+static void __init ek_add_regulators(void) {}
+#endif
+
 static struct i2c_board_info __initdata ek_i2c_devices[] = {
        {
                I2C_BOARD_INFO("24c512", 0x50),
@@ -256,6 +299,8 @@ static void __init ek_board_init(void)
        ek_add_device_nand();
        /* Ethernet */
        at91_add_device_eth(&ek_macb_data);
+       /* Regulators */
+       ek_add_regulators();
        /* MMC */
 #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
        at91_add_device_mci(0, &ek_mmc_data);
index c11fd47..6ea9808 100644 (file)
@@ -27,6 +27,9 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/clk.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/consumer.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -269,6 +272,46 @@ static void __init ek_add_device_buttons(void)
 static void __init ek_add_device_buttons(void) {}
 #endif
 
+#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
+static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
+       REGULATOR_SUPPLY("AVDD", "0-001b"),
+       REGULATOR_SUPPLY("HPVDD", "0-001b"),
+       REGULATOR_SUPPLY("DBVDD", "0-001b"),
+       REGULATOR_SUPPLY("DCVDD", "0-001b"),
+};
+
+static struct regulator_init_data ek_avdd_reg_init_data = {
+       .constraints    = {
+               .name   = "3V3",
+               .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+       },
+       .consumer_supplies = ek_audio_consumer_supplies,
+       .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
+};
+
+static struct fixed_voltage_config ek_vdd_pdata = {
+       .supply_name    = "board-3V3",
+       .microvolts     = 3300000,
+       .gpio           = -EINVAL,
+       .enabled_at_boot = 0,
+       .init_data      = &ek_avdd_reg_init_data,
+};
+static struct platform_device ek_voltage_regulator = {
+       .name           = "reg-fixed-voltage",
+       .id             = -1,
+       .num_resources  = 0,
+       .dev            = {
+               .platform_data  = &ek_vdd_pdata,
+       },
+};
+static void __init ek_add_regulators(void)
+{
+       platform_device_register(&ek_voltage_regulator);
+}
+#else
+static void __init ek_add_regulators(void) {}
+#endif
+
 
 static struct i2c_board_info __initdata ek_i2c_devices[] = {
         {
@@ -294,6 +337,8 @@ static void __init ek_board_init(void)
        ek_add_device_nand();
        /* Ethernet */
        at91_add_device_eth(&ek_macb_data);
+       /* Regulators */
+       ek_add_regulators();
        /* MMC */
        at91_add_device_mmc(0, &ek_mmc_data);
        /* I2C */
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
new file mode 100644 (file)
index 0000000..2c08ae4
--- /dev/null
@@ -0,0 +1,189 @@
+/*
+ * linux/arch/arm/mach-at91/board-snapper9260.c
+ *
+ *  Copyright (C) 2010 Bluewater System Ltd
+ *
+ * Author: Andre Renaud <andre@bluewatersys.com>
+ * Author: Ryan Mallon  <ryan@bluewatersys.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/i2c/pca953x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/hardware.h>
+#include <mach/board.h>
+#include <mach/at91sam9_smc.h>
+
+#include "sam9_smc.h"
+#include "generic.h"
+
+#define SNAPPER9260_IO_EXP_GPIO(x)     (NR_BUILTIN_GPIO + (x))
+
+static void __init snapper9260_map_io(void)
+{
+       at91sam9260_initialize(18432000);
+
+       /* Debug on ttyS0 */
+       at91_register_uart(0, 0, 0);
+       at91_set_serial_console(0);
+
+       at91_register_uart(AT91SAM9260_ID_US0, 1,
+                          ATMEL_UART_CTS | ATMEL_UART_RTS);
+       at91_register_uart(AT91SAM9260_ID_US1, 2,
+                          ATMEL_UART_CTS | ATMEL_UART_RTS);
+       at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
+}
+
+static void __init snapper9260_init_irq(void)
+{
+       at91sam9260_init_interrupts(NULL);
+}
+
+static struct at91_usbh_data __initdata snapper9260_usbh_data = {
+       .ports          = 2,
+};
+
+static struct at91_udc_data __initdata snapper9260_udc_data = {
+       .vbus_pin               = SNAPPER9260_IO_EXP_GPIO(5),
+       .vbus_active_low        = 1,
+       .vbus_polled            = 1,
+};
+
+static struct at91_eth_data snapper9260_macb_data = {
+       .is_rmii        = 1,
+};
+
+static struct mtd_partition __initdata snapper9260_nand_partitions[] = {
+       {
+               .name   = "Preboot",
+               .offset = 0,
+               .size   = SZ_128K,
+       },
+       {
+               .name   = "Bootloader",
+               .offset = MTDPART_OFS_APPEND,
+               .size   = SZ_256K,
+       },
+       {
+               .name   = "Environment",
+               .offset = MTDPART_OFS_APPEND,
+               .size   = SZ_128K,
+       },
+       {
+               .name   = "Kernel",
+               .offset = MTDPART_OFS_APPEND,
+               .size   = SZ_4M,
+       },
+       {
+               .name   = "Filesystem",
+               .offset = MTDPART_OFS_APPEND,
+               .size   = MTDPART_SIZ_FULL,
+       },
+};
+
+static struct mtd_partition * __init
+snapper9260_nand_partition_info(int size, int *num_partitions)
+{
+       *num_partitions = ARRAY_SIZE(snapper9260_nand_partitions);
+       return snapper9260_nand_partitions;
+}
+
+static struct atmel_nand_data __initdata snapper9260_nand_data = {
+       .ale            = 21,
+       .cle            = 22,
+       .rdy_pin        = AT91_PIN_PC13,
+       .partition_info = snapper9260_nand_partition_info,
+       .bus_width_16   = 0,
+};
+
+static struct sam9_smc_config __initdata snapper9260_nand_smc_config = {
+       .ncs_read_setup         = 0,
+       .nrd_setup              = 0,
+       .ncs_write_setup        = 0,
+       .nwe_setup              = 0,
+
+       .ncs_read_pulse         = 5,
+       .nrd_pulse              = 2,
+       .ncs_write_pulse        = 5,
+       .nwe_pulse              = 2,
+
+       .read_cycle             = 7,
+       .write_cycle            = 7,
+
+       .mode                   = (AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+                                  AT91_SMC_EXNWMODE_DISABLE),
+       .tdf_cycles             = 1,
+};
+
+static struct pca953x_platform_data snapper9260_io_expander_data = {
+       .gpio_base              = SNAPPER9260_IO_EXP_GPIO(0),
+};
+
+static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
+       {
+               /* IO expander */
+               I2C_BOARD_INFO("max7312", 0x28),
+               .platform_data = &snapper9260_io_expander_data,
+       },
+       {
+               /* Audio codec */
+               I2C_BOARD_INFO("tlv320aic23", 0x1a),
+       },
+       {
+               /* RTC */
+               I2C_BOARD_INFO("isl1208", 0x6f),
+       },
+};
+
+static void __init snapper9260_add_device_nand(void)
+{
+       at91_set_A_periph(AT91_PIN_PC14, 0);
+       sam9_smc_configure(3, &snapper9260_nand_smc_config);
+       at91_add_device_nand(&snapper9260_nand_data);
+}
+
+static void __init snapper9260_board_init(void)
+{
+       at91_add_device_i2c(snapper9260_i2c_devices,
+                           ARRAY_SIZE(snapper9260_i2c_devices));
+       at91_add_device_serial();
+       at91_add_device_usbh(&snapper9260_usbh_data);
+       at91_add_device_udc(&snapper9260_udc_data);
+       at91_add_device_eth(&snapper9260_macb_data);
+       at91_add_device_ssc(AT91SAM9260_ID_SSC, (ATMEL_SSC_TF | ATMEL_SSC_TK |
+                                                ATMEL_SSC_TD | ATMEL_SSC_RD));
+       snapper9260_add_device_nand();
+}
+
+MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
+       .phys_io        = AT91_BASE_SYS,
+       .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+       .boot_params    = AT91_SDRAM_BASE + 0x100,
+       .timer          = &at91sam926x_timer,
+       .map_io         = snapper9260_map_io,
+       .init_irq       = snapper9260_init_irq,
+       .init_machine   = snapper9260_board_init,
+MACHINE_END
+
+
index d8c1ede..9c6af97 100644 (file)
@@ -84,7 +84,7 @@
  */
 #define AT91_ECC       (0xffffe200 - AT91_BASE_SYS)
 #define AT91_BCRAMC    (0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC   (0xffffe600 - AT91_BASE_SYS)
+#define AT91_DDRSDRC0  (0xffffe600 - AT91_BASE_SYS)
 #define AT91_SMC       (0xffffe800 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffea00 - AT91_BASE_SYS)
 #define AT91_CCFG      (0xffffeb10 - AT91_BASE_SYS)
index 1499b1c..976f4a6 100644 (file)
@@ -15,7 +15,7 @@
 #ifndef AT91CAP9_DDRSDR_H
 #define AT91CAP9_DDRSDR_H
 
-#define AT91_DDRSDRC_MR                (AT91_DDRSDRC + 0x00)   /* Mode Register */
+#define AT91_DDRSDRC_MR                0x00    /* Mode Register */
 #define                AT91_DDRSDRC_MODE       (0xf << 0)              /* Command Mode */
 #define                        AT91_DDRSDRC_MODE_NORMAL                0
 #define                        AT91_DDRSDRC_MODE_NOP           1
 #define                        AT91_DDRSDRC_MODE_EXT_LMR       5
 #define                        AT91_DDRSDRC_MODE_DEEP          6
 
-#define AT91_DDRSDRC_RTR       (AT91_DDRSDRC + 0x04)   /* Refresh Timer Register */
+#define AT91_DDRSDRC_RTR       0x04    /* Refresh Timer Register */
 #define                AT91_DDRSDRC_COUNT      (0xfff << 0)            /* Refresh Timer Counter */
 
-#define AT91_DDRSDRC_CR                (AT91_DDRSDRC + 0x08)   /* Configuration Register */
+#define AT91_DDRSDRC_CR                0x08    /* Configuration Register */
 #define                AT91_DDRSDRC_NC         (3 << 0)                /* Number of Column Bits */
 #define                        AT91_DDRSDRC_NC_SDR8    (0 << 0)
 #define                        AT91_DDRSDRC_NC_SDR9    (1 << 0)
@@ -49,7 +49,7 @@
 #define                AT91_DDRSDRC_DLL        (1 << 7)                /* Reset DLL */
 #define                AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
 
-#define AT91_DDRSDRC_T0PR      (AT91_DDRSDRC + 0x0C)   /* Timing 0 Register */
+#define AT91_DDRSDRC_T0PR      0x0C    /* Timing 0 Register */
 #define                AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
 #define                AT91_DDRSDRC_TRCD       (0xf <<  4)             /* Row to Column delay */
 #define                AT91_DDRSDRC_TWR        (0xf <<  8)             /* Write recovery delay */
 #define                AT91_DDRSDRC_TWTR       (1   << 24)             /* Internal Write to Read delay */
 #define                AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
 
-#define AT91_DDRSDRC_T1PR      (AT91_DDRSDRC + 0x10)   /* Timing 1 Register */
+#define AT91_DDRSDRC_T1PR      0x10    /* Timing 1 Register */
 #define                AT91_DDRSDRC_TRFC       (0x1f << 0)             /* Row Cycle Delay */
 #define                AT91_DDRSDRC_TXSNR      (0xff << 8)             /* Exit self-refresh to non-read */
 #define                AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
 #define                AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
 
-#define AT91_DDRSDRC_LPR       (AT91_DDRSDRC + 0x18)   /* Low Power Register */
+#define AT91_DDRSDRC_LPR       0x18    /* Low Power Register */
 #define                AT91_DDRSDRC_LPCB               (3 << 0)        /* Low-power Configurations */
 #define                        AT91_DDRSDRC_LPCB_DISABLE               0
 #define                        AT91_DDRSDRC_LPCB_SELF_REFRESH          1
 #define                        AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES      (1 << 12)
 #define                        AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES     (2 << 12)
 
-#define AT91_DDRSDRC_MDR       (AT91_DDRSDRC + 0x1C)   /* Memory Device Register */
+#define AT91_DDRSDRC_MDR       0x1C    /* Memory Device Register */
 #define                AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
 #define                        AT91_DDRSDRC_MD_SDR             0
 #define                        AT91_DDRSDRC_MD_LOW_POWER_SDR   1
 #define                        AT91_DDRSDRC_MD_DDR             2
 #define                        AT91_DDRSDRC_MD_LOW_POWER_DDR   3
 
-#define AT91_DDRSDRC_DLLR      (AT91_DDRSDRC + 0x20)   /* DLL Information Register */
+#define AT91_DDRSDRC_DLLR      0x20    /* DLL Information Register */
 #define                AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
 #define                AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
 #define                AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
 #define                AT91_DDRSDRC_SDVAL      (0xff << 16)            /* Slave Delay value */
 #define                AT91_DDRSDRC_SDCVAL     (0xff << 24)            /* Slave Delay Correction value */
 
+/* Register access macros */
+#define at91_ramc_read(num, reg) \
+       at91_sys_read(AT91_DDRSDRC##num + reg)
+#define at91_ramc_write(num, reg, value) \
+       at91_sys_write(AT91_DDRSDRC##num + reg, value)
+
 
 #endif
index 43c396b..4e79036 100644 (file)
@@ -84,7 +84,7 @@
  * System Peripherals (offset from AT91_BASE_SYS)
  */
 #define AT91_ECC       (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC    (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SDRAMC0   (0xffffea00 - AT91_BASE_SYS)
 #define AT91_SMC       (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
 #define AT91_CCFG      (0xffffef10 - AT91_BASE_SYS)
index 87de8be..2b56185 100644 (file)
@@ -68,7 +68,7 @@
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
-#define AT91_SDRAMC    (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SDRAMC0   (0xffffea00 - AT91_BASE_SYS)
 #define AT91_SMC       (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
 #define AT91_AIC       (0xfffff000 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
new file mode 100644 (file)
index 0000000..d27b15b
--- /dev/null
@@ -0,0 +1,130 @@
+/*
+ * Header file for the Atmel DDR/SDR SDRAM Controller
+ *
+ * Copyright (C) 2010 Atmel Corporation
+ *     Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91SAM9_DDRSDR_H
+#define AT91SAM9_DDRSDR_H
+
+#define AT91_DDRSDRC_MR                0x00    /* Mode Register */
+#define                AT91_DDRSDRC_MODE       (0x7 << 0)              /* Command Mode */
+#define                        AT91_DDRSDRC_MODE_NORMAL        0
+#define                        AT91_DDRSDRC_MODE_NOP           1
+#define                        AT91_DDRSDRC_MODE_PRECHARGE     2
+#define                        AT91_DDRSDRC_MODE_LMR           3
+#define                        AT91_DDRSDRC_MODE_REFRESH       4
+#define                        AT91_DDRSDRC_MODE_EXT_LMR       5
+#define                        AT91_DDRSDRC_MODE_DEEP          6
+
+#define AT91_DDRSDRC_RTR       0x04    /* Refresh Timer Register */
+#define                AT91_DDRSDRC_COUNT      (0xfff << 0)            /* Refresh Timer Counter */
+
+#define AT91_DDRSDRC_CR                0x08    /* Configuration Register */
+#define                AT91_DDRSDRC_NC         (3 << 0)                /* Number of Column Bits */
+#define                        AT91_DDRSDRC_NC_SDR8    (0 << 0)
+#define                        AT91_DDRSDRC_NC_SDR9    (1 << 0)
+#define                        AT91_DDRSDRC_NC_SDR10   (2 << 0)
+#define                        AT91_DDRSDRC_NC_SDR11   (3 << 0)
+#define                        AT91_DDRSDRC_NC_DDR9    (0 << 0)
+#define                        AT91_DDRSDRC_NC_DDR10   (1 << 0)
+#define                        AT91_DDRSDRC_NC_DDR11   (2 << 0)
+#define                        AT91_DDRSDRC_NC_DDR12   (3 << 0)
+#define                AT91_DDRSDRC_NR         (3 << 2)                /* Number of Row Bits */
+#define                        AT91_DDRSDRC_NR_11      (0 << 2)
+#define                        AT91_DDRSDRC_NR_12      (1 << 2)
+#define                        AT91_DDRSDRC_NR_13      (2 << 2)
+#define                        AT91_DDRSDRC_NR_14      (3 << 2)
+#define                AT91_DDRSDRC_CAS        (7 << 4)                /* CAS Latency */
+#define                        AT91_DDRSDRC_CAS_2      (2 << 4)
+#define                        AT91_DDRSDRC_CAS_3      (3 << 4)
+#define                        AT91_DDRSDRC_CAS_25     (6 << 4)
+#define                AT91_DDRSDRC_RST_DLL    (1 << 7)                /* Reset DLL */
+#define                AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
+#define                AT91_DDRSDRC_DIS_DLL    (1 << 9)                /* Disable DLL */
+#define                AT91_DDRSDRC_OCD        (1 << 12)               /* Off-Chip Driver */
+#define                AT91_DDRSDRC_DQMS       (1 << 16)               /* Mask Data is Shared */
+#define                AT91_DDRSDRC_ACTBST     (1 << 18)               /* Active Bank X to Burst Stop Read Access Bank Y */
+
+#define AT91_DDRSDRC_T0PR      0x0C    /* Timing 0 Register */
+#define                AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
+#define                AT91_DDRSDRC_TRCD       (0xf <<  4)             /* Row to Column delay */
+#define                AT91_DDRSDRC_TWR        (0xf <<  8)             /* Write recovery delay */
+#define                AT91_DDRSDRC_TRC        (0xf << 12)             /* Row cycle delay */
+#define                AT91_DDRSDRC_TRP        (0xf << 16)             /* Row precharge delay */
+#define                AT91_DDRSDRC_TRRD       (0xf << 20)             /* Active BankA to BankB */
+#define                AT91_DDRSDRC_TWTR       (0x7 << 24)             /* Internal Write to Read delay */
+#define                AT91_DDRSDRC_RED_WRRD   (0x1 << 27)             /* Reduce Write to Read Delay */
+#define                AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
+
+#define AT91_DDRSDRC_T1PR      0x10    /* Timing 1 Register */
+#define                AT91_DDRSDRC_TRFC       (0x1f << 0)             /* Row Cycle Delay */
+#define                AT91_DDRSDRC_TXSNR      (0xff << 8)             /* Exit self-refresh to non-read */
+#define                AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
+#define                AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
+
+#define AT91_DDRSDRC_T2PR      0x14    /* Timing 2 Register */
+#define                AT91_DDRSDRC_TXARD      (0xf  << 0)             /* Exit active power down delay to read command in mode "Fast Exit" */
+#define                AT91_DDRSDRC_TXARDS     (0xf  << 4)             /* Exit active power down delay to read command in mode "Slow Exit" */
+#define                AT91_DDRSDRC_TRPA       (0xf  << 8)             /* Row Precharge All delay */
+#define                AT91_DDRSDRC_TRTP       (0x7  << 12)            /* Read to Precharge delay */
+
+#define AT91_DDRSDRC_LPR       0x1C    /* Low Power Register */
+#define                AT91_DDRSDRC_LPCB       (3 << 0)                /* Low-power Configurations */
+#define                        AT91_DDRSDRC_LPCB_DISABLE               0
+#define                        AT91_DDRSDRC_LPCB_SELF_REFRESH          1
+#define                        AT91_DDRSDRC_LPCB_POWER_DOWN            2
+#define                        AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN       3
+#define                AT91_DDRSDRC_CLKFR      (1 << 2)        /* Clock Frozen */
+#define                AT91_DDRSDRC_PASR       (7 << 4)        /* Partial Array Self Refresh */
+#define                AT91_DDRSDRC_TCSR       (3 << 8)        /* Temperature Compensated Self Refresh */
+#define                AT91_DDRSDRC_DS         (3 << 10)       /* Drive Strength */
+#define                AT91_DDRSDRC_TIMEOUT    (3 << 12)       /* Time to define when Low Power Mode is enabled */
+#define                        AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES       (0 << 12)
+#define                        AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES      (1 << 12)
+#define                        AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES     (2 << 12)
+#define                AT91_DDRSDRC_APDE       (1 << 16)        /* Active power down exit time */
+#define                AT91_DDRSDRC_UPD_MR     (3 << 20)        /* Update load mode register and extended mode register */
+
+#define AT91_DDRSDRC_MDR       0x20    /* Memory Device Register */
+#define                AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
+#define                        AT91_DDRSDRC_MD_SDR             0
+#define                        AT91_DDRSDRC_MD_LOW_POWER_SDR   1
+#define                        AT91_DDRSDRC_MD_LOW_POWER_DDR   3
+#define                        AT91_DDRSDRC_MD_DDR2            6
+#define                AT91_DDRSDRC_DBW        (1 << 4)                /* Data Bus Width */
+#define                        AT91_DDRSDRC_DBW_32BITS         (0 <<  4)
+#define                        AT91_DDRSDRC_DBW_16BITS         (1 <<  4)
+
+#define AT91_DDRSDRC_DLL       0x24    /* DLL Information Register */
+#define                AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
+#define                AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
+#define                AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
+#define                AT91_DDRSDRC_MDVAL      (0xff <<  8)            /* Master Delay value */
+
+#define AT91_DDRSDRC_HS                0x2C    /* High Speed Register */
+#define                AT91_DDRSDRC_DIS_ATCP_RD        (1 << 2)        /* Anticip read access is disabled */
+
+#define AT91_DDRSDRC_DELAY(n)  (0x30 + (0x4 * (n)))    /* Delay I/O Register n */
+
+#define AT91_DDRSDRC_WPMR      0xE4    /* Write Protect Mode Register */
+#define                AT91_DDRSDRC_WP         (1 << 0)                /* Write protect enable */
+#define                AT91_DDRSDRC_WPKEY      (0xffffff << 8)         /* Write protect key */
+#define                AT91_DDRSDRC_KEY        (0x444452 << 8)         /* Write protect key = "DDR" */
+
+#define AT91_DDRSDRC_WPSR      0xE8    /* Write Protect Status Register */
+#define                AT91_DDRSDRC_WPVS       (1 << 0)                /* Write protect violation status */
+#define                AT91_DDRSDRC_WPVSRC     (0xffff << 8)           /* Write protect violation source */
+
+/* Register access macros */
+#define at91_ramc_read(num, reg) \
+       at91_sys_read(AT91_DDRSDRC##num + reg)
+#define at91_ramc_write(num, reg, value) \
+       at91_sys_write(AT91_DDRSDRC##num + reg, value)
+
+#endif
index b726038..100f5a5 100644 (file)
@@ -17,7 +17,7 @@
 #define AT91SAM9_SDRAMC_H
 
 /* SDRAM Controller (SDRAMC) registers */
-#define AT91_SDRAMC_MR         (AT91_SDRAMC + 0x00)    /* SDRAM Controller Mode Register */
+#define AT91_SDRAMC_MR         0x00    /* SDRAM Controller Mode Register */
 #define                AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
 #define                        AT91_SDRAMC_MODE_NORMAL         0
 #define                        AT91_SDRAMC_MODE_NOP            1
 #define                        AT91_SDRAMC_MODE_EXT_LMR        5
 #define                        AT91_SDRAMC_MODE_DEEP           6
 
-#define AT91_SDRAMC_TR         (AT91_SDRAMC + 0x04)    /* SDRAM Controller Refresh Timer Register */
+#define AT91_SDRAMC_TR         0x04    /* SDRAM Controller Refresh Timer Register */
 #define                AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Counter */
 
-#define AT91_SDRAMC_CR         (AT91_SDRAMC + 0x08)    /* SDRAM Controller Configuration Register */
+#define AT91_SDRAMC_CR         0x08    /* SDRAM Controller Configuration Register */
 #define                AT91_SDRAMC_NC          (3 << 0)                /* Number of Column Bits */
 #define                        AT91_SDRAMC_NC_8        (0 << 0)
 #define                        AT91_SDRAMC_NC_9        (1 << 0)
@@ -57,7 +57,7 @@
 #define                AT91_SDRAMC_TRAS        (0xf << 24)             /* Active to Precharge Delay */
 #define                AT91_SDRAMC_TXSR        (0xf << 28)             /* Exit Self Refresh to Active Delay */
 
-#define AT91_SDRAMC_LPR                (AT91_SDRAMC + 0x10)    /* SDRAM Controller Low Power Register */
+#define AT91_SDRAMC_LPR                0x10    /* SDRAM Controller Low Power Register */
 #define                AT91_SDRAMC_LPCB                (3 << 0)        /* Low-power Configurations */
 #define                        AT91_SDRAMC_LPCB_DISABLE                0
 #define                        AT91_SDRAMC_LPCB_SELF_REFRESH           1
 #define                        AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
 #define                        AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES      (2 << 12)
 
-#define AT91_SDRAMC_IER                (AT91_SDRAMC + 0x14)    /* SDRAM Controller Interrupt Enable Register */
-#define AT91_SDRAMC_IDR                (AT91_SDRAMC + 0x18)    /* SDRAM Controller Interrupt Disable Register */
-#define AT91_SDRAMC_IMR                (AT91_SDRAMC + 0x1C)    /* SDRAM Controller Interrupt Mask Register */
-#define AT91_SDRAMC_ISR                (AT91_SDRAMC + 0x20)    /* SDRAM Controller Interrupt Status Register */
+#define AT91_SDRAMC_IER                0x14    /* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR                0x18    /* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR                0x1C    /* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR                0x20    /* SDRAM Controller Interrupt Status Register */
 #define                AT91_SDRAMC_RES         (1 << 0)                /* Refresh Error Status */
 
-#define AT91_SDRAMC_MDR                (AT91_SDRAMC + 0x24)    /* SDRAM Memory Device Register */
+#define AT91_SDRAMC_MDR                0x24    /* SDRAM Memory Device Register */
 #define                AT91_SDRAMC_MD          (3 << 0)                /* Memory Device Type */
 #define                        AT91_SDRAMC_MD_SDRAM            0
 #define                        AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
 
+/* Register access macros */
+#define at91_ramc_read(num, reg) \
+       at91_sys_read(AT91_SDRAMC##num + reg)
+#define at91_ramc_write(num, reg, value) \
+       at91_sys_write(AT91_SDRAMC##num + reg, value)
 
 #endif
index fc2de6c..87ba851 100644 (file)
@@ -74,7 +74,7 @@
  */
 #define AT91_DMA       (0xffffe600 - AT91_BASE_SYS)
 #define AT91_ECC       (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC    (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SDRAMC0   (0xffffea00 - AT91_BASE_SYS)
 #define AT91_SMC       (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
 #define AT91_CCFG      (0xffffef10 - AT91_BASE_SYS)
index df2ed84..58528aa 100644 (file)
@@ -44,6 +44,8 @@
  /* USB Device */
 struct at91_udc_data {
        u8      vbus_pin;               /* high == host powering us */
+       u8      vbus_active_low;        /* vbus polarity */
+       u8      vbus_polled;            /* Use polling, not interrupt */
        u8      pullup_pin;             /* active == D+ pulled up */
        u8      pullup_active_low;      /* true == pullup_pin is active low */
 };
index 833659d..3bef931 100644 (file)
@@ -52,6 +52,7 @@ static inline unsigned long at91_cpu_fully_identify(void)
 
 #define ARCH_EXID_AT91SAM9M11  0x00000001
 #define ARCH_EXID_AT91SAM9M10  0x00000002
+#define ARCH_EXID_AT91SAM9G46  0x00000003
 #define ARCH_EXID_AT91SAM9G45  0x00000004
 
 static inline unsigned long at91_exid_identify(void)
@@ -128,9 +129,18 @@ static inline unsigned long at91cap9_rev_identify(void)
 #ifdef CONFIG_ARCH_AT91SAM9G45
 #define cpu_is_at91sam9g45()   (at91_cpu_identify() == ARCH_ID_AT91SAM9G45)
 #define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES)
+#define cpu_is_at91sam9m10()    (cpu_is_at91sam9g45() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9M10))
+#define cpu_is_at91sam9m46()    (cpu_is_at91sam9g45() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9G46))
+#define cpu_is_at91sam9m11()    (cpu_is_at91sam9g45() && \
+                                (at91_exid_identify() == ARCH_EXID_AT91SAM9M11))
 #else
 #define cpu_is_at91sam9g45()   (0)
 #define cpu_is_at91sam9g45es() (0)
+#define cpu_is_at91sam9m10()   (0)
+#define cpu_is_at91sam9g46()   (0)
+#define cpu_is_at91sam9m11()   (0)
 #endif
 
 #ifdef CONFIG_ARCH_AT91CAP9
index 04c91e3..bfdd8ab 100644 (file)
@@ -19,6 +19,7 @@
 #define PIN_BASE               NR_AIC_IRQS
 
 #define MAX_GPIO_BANKS         5
+#define NR_BUILTIN_GPIO                (PIN_BASE + (MAX_GPIO_BANKS * 32))
 
 /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
 
index 08322c4..8c87d0c 100644 (file)
@@ -30,14 +30,50 @@ static inline u32 sdram_selfrefresh_enable(void)
 {
        u32 saved_lpr, lpr;
 
-       saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
+       saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
 
        lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
-       at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
+       at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
        return saved_lpr;
 }
 
-#define sdram_selfrefresh_disable(saved_lpr)   at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
+#define sdram_selfrefresh_disable(saved_lpr)   at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
+
+#elif defined(CONFIG_ARCH_AT91SAM9G45)
+#include <mach/at91sam9_ddrsdr.h>
+
+/* We manage both DDRAM/SDRAM controllers, we need more than one value to
+ * remember.
+ */
+static u32 saved_lpr1;
+
+static inline u32 sdram_selfrefresh_enable(void)
+{
+       /* Those tow values allow us to delay self-refresh activation
+        * to the maximum. */
+       u32 lpr0, lpr1;
+       u32 saved_lpr0;
+
+       saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
+       lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
+       lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
+
+       saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
+       lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
+       lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
+
+       /* self-refresh mode now */
+       at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
+       at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
+
+       return saved_lpr0;
+}
+
+#define sdram_selfrefresh_disable(saved_lpr0)  \
+       do { \
+               at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
+               at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
+       } while (0)
 
 #else
 #include <mach/at91sam9_sdramc.h>
@@ -47,7 +83,6 @@ static inline u32 sdram_selfrefresh_enable(void)
  * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
  * handle those cases both here and in the Suspend-To-RAM support.
  */
-#define        AT91_SDRAMC     AT91_SDRAMC0
 #warning Assuming EB1 SDRAM controller is *NOT* used
 #endif
 
@@ -55,13 +90,13 @@ static inline u32 sdram_selfrefresh_enable(void)
 {
        u32 saved_lpr, lpr;
 
-       saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
+       saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
 
        lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
-       at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
+       at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
        return saved_lpr;
 }
 
-#define sdram_selfrefresh_disable(saved_lpr)   at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
+#define sdram_selfrefresh_disable(saved_lpr)   at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
 
 #endif
index 9c5b48e..b6b00a1 100644 (file)
 #include <mach/hardware.h>
 #include <mach/at91_pmc.h>
 
-#ifdef CONFIG_ARCH_AT91RM9200
+#if defined(CONFIG_ARCH_AT91RM9200)
 #include <mach/at91rm9200_mc.h>
 #elif defined(CONFIG_ARCH_AT91CAP9)
 #include <mach/at91cap9_ddrsdr.h>
+#elif defined(CONFIG_ARCH_AT91SAM9G45)
+#include <mach/at91sam9_ddrsdr.h>
 #else
 #include <mach/at91sam9_sdramc.h>
 #endif
@@ -30,7 +32,6 @@
  * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
  * handle those cases both here and in the Suspend-To-RAM support.
  */
-#define AT91_SDRAMC    AT91_SDRAMC0
 #warning Assuming EB1 SDRAM controller is *NOT* used
 #endif
 
@@ -113,12 +114,14 @@ ENTRY(at91_slow_clock)
        /*
         * Register usage:
         *  R1 = Base address of AT91_PMC
-        *  R2 = Base address of AT91_SDRAMC (or AT91_SYS on AT91RM9200)
+        *  R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
         *  R3 = temporary register
         *  R4 = temporary register
+        *  R5 = Base address of second RAM Controller or 0 if not present
         */
        ldr     r1, .at91_va_base_pmc
        ldr     r2, .at91_va_base_sdramc
+       ldr     r5, .at91_va_base_ramc1
 
        /* Drain write buffer */
        mcr     p15, 0, r0, c7, c10, 4
@@ -127,20 +130,33 @@ ENTRY(at91_slow_clock)
        /* Put SDRAM in self-refresh mode */
        mov     r3, #1
        str     r3, [r2, #AT91_SDRAMC_SRR]
-#elif defined(CONFIG_ARCH_AT91CAP9)
-       /* Enable SDRAM self-refresh mode */
-       ldr     r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
-       str     r3, .saved_sam9_lpr
+#elif defined(CONFIG_ARCH_AT91CAP9) \
+       || defined(CONFIG_ARCH_AT91SAM9G45)
 
-       mov     r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
-       str     r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
+       /* prepare for DDRAM self-refresh mode */
+       ldr     r3, [r2, #AT91_DDRSDRC_LPR]
+       str     r3, .saved_sam9_lpr
+       bic     r3, #AT91_DDRSDRC_LPCB
+       orr     r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+
+       /* figure out if we use the second ram controller */
+       cmp     r5, #0
+       ldrne   r4, [r5, #AT91_DDRSDRC_LPR]
+       strne   r4, .saved_sam9_lpr1
+       bicne   r4, #AT91_DDRSDRC_LPCB
+       orrne   r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+
+       /* Enable DDRAM self-refresh mode */
+       str     r3, [r2, #AT91_DDRSDRC_LPR]
+       strne   r4, [r5, #AT91_DDRSDRC_LPR]
 #else
        /* Enable SDRAM self-refresh mode */
-       ldr     r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
+       ldr     r3, [r2, #AT91_SDRAMC_LPR]
        str     r3, .saved_sam9_lpr
 
-       mov     r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
-       str     r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
+       bic     r3, #AT91_SDRAMC_LPCB
+       orr     r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
+       str     r3, [r2, #AT91_SDRAMC_LPR]
 #endif
 
        /* Save Master clock setting */
@@ -247,14 +263,21 @@ ENTRY(at91_slow_clock)
 
 #ifdef CONFIG_ARCH_AT91RM9200
        /* Do nothing - self-refresh is automatically disabled. */
-#elif defined(CONFIG_ARCH_AT91CAP9)
-       /* Restore LPR on AT91CAP9 */
+#elif defined(CONFIG_ARCH_AT91CAP9) \
+       || defined(CONFIG_ARCH_AT91SAM9G45)
+       /* Restore LPR on AT91 with DDRAM */
        ldr     r3, .saved_sam9_lpr
-       str     r3, [r2, #AT91_DDRSDRC_LPR - AT91_DDRSDRC]
+       str     r3, [r2, #AT91_DDRSDRC_LPR]
+
+       /* if we use the second ram controller */
+       cmp     r5, #0
+       ldrne   r4, .saved_sam9_lpr1
+       strne   r4, [r5, #AT91_DDRSDRC_LPR]
+
 #else
-       /* Restore LPR on AT91SAM9 */
+       /* Restore LPR on AT91 with SDRAM */
        ldr     r3, .saved_sam9_lpr
-       str     r3, [r2, #AT91_SDRAMC_LPR - AT91_SDRAMC]
+       str     r3, [r2, #AT91_SDRAMC_LPR]
 #endif
 
        /* Restore registers, and return */
@@ -273,18 +296,29 @@ ENTRY(at91_slow_clock)
 .saved_sam9_lpr:
        .word 0
 
+.saved_sam9_lpr1:
+       .word 0
+
 .at91_va_base_pmc:
        .word AT91_VA_BASE_SYS + AT91_PMC
 
 #ifdef CONFIG_ARCH_AT91RM9200
 .at91_va_base_sdramc:
        .word AT91_VA_BASE_SYS
-#elif defined(CONFIG_ARCH_AT91CAP9)
+#elif defined(CONFIG_ARCH_AT91CAP9) \
+       || defined(CONFIG_ARCH_AT91SAM9G45)
 .at91_va_base_sdramc:
-       .word AT91_VA_BASE_SYS + AT91_DDRSDRC
+       .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
 #else
 .at91_va_base_sdramc:
-       .word AT91_VA_BASE_SYS + AT91_SDRAMC
+       .word AT91_VA_BASE_SYS + AT91_SDRAMC0
+#endif
+
+.at91_va_base_ramc1:
+#if defined(CONFIG_ARCH_AT91SAM9G45)
+       .word AT91_VA_BASE_SYS + AT91_DDRSDRC1
+#else
+       .word 0
 #endif
 
 ENTRY(at91_slow_clock_sz)
index 72e405d..d3f959e 100644 (file)
@@ -91,14 +91,23 @@ static struct clk uart_clk = {
        .parent = &pll1_clk,
 };
 
+static struct clk dummy_apb_pclk = {
+       .name = "BUSCLK",
+       .type = CLK_TYPE_PRIMARY,
+       .mode = CLK_MODE_XTAL,
+};
+
 static struct clk_lookup lookups[] = {
-       {                       /* UART0 */
-        .dev_id = "uarta",
-        .clk = &uart_clk,
-        }, {                   /* UART1 */
-            .dev_id = "uartb",
-            .clk = &uart_clk,
-            }
+       {                       /* Bus clock */
+               .con_id = "apb_pclk",
+               .clk = &dummy_apb_pclk,
+       }, {                    /* UART0 */
+               .dev_id = "uarta",
+               .clk = &uart_clk,
+       }, {                    /* UART1 */
+               .dev_id = "uartb",
+               .clk = &uart_clk,
+       }
 };
 
 static struct amba_device *amba_devs[] __initdata = {
index dbaae5f..eb34bd1 100644 (file)
@@ -30,7 +30,6 @@ config ARCH_CLEP7312
 config ARCH_EDB7211
        bool "EDB7211"
        select ISA
-       select ARCH_DISCONTIGMEM_ENABLE
        select ARCH_SPARSEMEM_ENABLE
        select ARCH_SELECT_MEMORY_MODEL
        help
index 09fb57e..3c3bf45 100644 (file)
@@ -32,7 +32,6 @@ fixup_clep7312(struct machine_desc *desc, struct tag *tags,
        mi->nr_banks=1;
        mi->bank[0].start = 0xc0000000;
        mi->bank[0].size = 0x01000000;
-       mi->bank[0].node = 0;
 }
 
 
index dc81cc6..4a7a232 100644 (file)
@@ -18,6 +18,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #include <linux/init.h>
+#include <linux/memblock.h>
 #include <linux/types.h>
 #include <linux/string.h>
 
 
 extern void edb7211_map_io(void);
 
+/* Reserve screen memory region at the start of main system memory. */
+static void __init edb7211_reserve(void)
+{
+       memblock_reserve(PHYS_OFFSET, 0x00020000);
+}
+
 static void __init
 fixup_edb7211(struct machine_desc *desc, struct tag *tags,
              char **cmdline, struct meminfo *mi)
@@ -43,10 +50,8 @@ fixup_edb7211(struct machine_desc *desc, struct tag *tags,
         */
        mi->bank[0].start = 0xc0000000;
        mi->bank[0].size = 8*1024*1024;
-       mi->bank[0].node = 0;
        mi->bank[1].start = 0xc1000000;
        mi->bank[1].size = 8*1024*1024;
-       mi->bank[1].node = 1;
        mi->nr_banks = 2;
 }
 
@@ -57,6 +62,7 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
        .boot_params    = 0xc0020100,   /* 0xc0000000 - 0xc001ffff can be video RAM */
        .fixup          = fixup_edb7211,
        .map_io         = edb7211_map_io,
+       .reserve        = edb7211_reserve,
        .init_irq       = clps711x_init_irq,
        .timer          = &clps711x_timer,
 MACHINE_END
index 7430e40..a696099 100644 (file)
@@ -39,7 +39,6 @@ struct meminfo memmap = {
                {
                        .start  = 0xC0000000,
                        .size   = 0x01000000,
-                       .node   = 0
                },
        },
 };
index f70d52b..f45c8e8 100644 (file)
@@ -20,7 +20,6 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
 
-
 /*
  * Physical DRAM offset.
  */
@@ -72,7 +71,6 @@
  *     node 2:  0xd0000000 - 0xd7ffffff
  *     node 3:  0xd8000000 - 0xdfffffff
  */
-#define NODE_MEM_SIZE_BITS     24
 #define SECTION_SIZE_BITS      24
 #define MAX_PHYSMEM_BITS       32
 
index 427507a..11033f1 100644 (file)
@@ -1,2 +1,3 @@
-obj-$(CONFIG_ARCH_CNS3XXX)             += core.o pm.o
+obj-$(CONFIG_ARCH_CNS3XXX)             += core.o pm.o devices.o
+obj-$(CONFIG_PCI)                      += pcie.o
 obj-$(CONFIG_MACH_CNS3420VB)           += cns3420vb.o
index 2e30c82..9df8391 100644 (file)
@@ -32,6 +32,7 @@
 #include <mach/cns3xxx.h>
 #include <mach/irqs.h>
 #include "core.h"
+#include "devices.h"
 
 /*
  * NOR Flash
@@ -117,6 +118,9 @@ static void __init cns3420_init(void)
 {
        platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
 
+       cns3xxx_ahci_init();
+       cns3xxx_sdhci_init();
+
        pm_power_off = cns3xxx_power_off;
 }
 
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
new file mode 100644 (file)
index 0000000..50b4d31
--- /dev/null
@@ -0,0 +1,111 @@
+/*
+ * CNS3xxx common devices
+ *
+ * Copyright 2008 Cavium Networks
+ *               Scott Shu
+ * Copyright 2010 MontaVista Software, LLC.
+ *               Anton Vorontsov <avorontsov@mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/compiler.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <mach/cns3xxx.h>
+#include <mach/irqs.h>
+#include "core.h"
+#include "devices.h"
+
+/*
+ * AHCI
+ */
+static struct resource cns3xxx_ahci_resource[] = {
+       [0] = {
+               .start  = CNS3XXX_SATA2_BASE,
+               .end    = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = IRQ_CNS3XXX_SATA,
+               .end    = IRQ_CNS3XXX_SATA,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device cns3xxx_ahci_pdev = {
+       .name           = "ahci",
+       .id             = 0,
+       .resource       = cns3xxx_ahci_resource,
+       .num_resources  = ARRAY_SIZE(cns3xxx_ahci_resource),
+       .dev            = {
+               .dma_mask               = &cns3xxx_ahci_dmamask,
+               .coherent_dma_mask      = DMA_BIT_MASK(32),
+       },
+};
+
+void __init cns3xxx_ahci_init(void)
+{
+       u32 tmp;
+
+       tmp = __raw_readl(MISC_SATA_POWER_MODE);
+       tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
+       tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
+       __raw_writel(tmp, MISC_SATA_POWER_MODE);
+
+       /* Enable SATA PHY */
+       cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
+       cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
+
+       /* Enable SATA Clock */
+       cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
+
+       /* De-Asscer SATA Reset */
+       cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
+
+       platform_device_register(&cns3xxx_ahci_pdev);
+}
+
+/*
+ * SDHCI
+ */
+static struct resource cns3xxx_sdhci_resources[] = {
+       [0] = {
+               .start = CNS3XXX_SDIO_BASE,
+               .end   = CNS3XXX_SDIO_BASE + SZ_4K - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start = IRQ_CNS3XXX_SDIO,
+               .end   = IRQ_CNS3XXX_SDIO,
+               .flags = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device cns3xxx_sdhci_pdev = {
+       .name           = "sdhci-cns3xxx",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(cns3xxx_sdhci_resources),
+       .resource       = cns3xxx_sdhci_resources,
+};
+
+void __init cns3xxx_sdhci_init(void)
+{
+       u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014);
+       u32 gpioa_pins = __raw_readl(gpioa);
+
+       /* MMC/SD pins share with GPIOA */
+       gpioa_pins |= 0x1fff0004;
+       __raw_writel(gpioa_pins, gpioa);
+
+       cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
+       cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
+
+       platform_device_register(&cns3xxx_sdhci_pdev);
+}
diff --git a/arch/arm/mach-cns3xxx/devices.h b/arch/arm/mach-cns3xxx/devices.h
new file mode 100644 (file)
index 0000000..27e15a1
--- /dev/null
@@ -0,0 +1,20 @@
+/*
+ * CNS3xxx common devices
+ *
+ * Copyright 2008 Cavium Networks
+ *               Scott Shu
+ * Copyright 2010 MontaVista Software, LLC.
+ *               Anton Vorontsov <avorontsov@mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __CNS3XXX_DEVICES_H_
+#define __CNS3XXX_DEVICES_H_
+
+void __init cns3xxx_ahci_init(void);
+void __init cns3xxx_sdhci_init(void);
+
+#endif /* __CNS3XXX_DEVICES_H_ */
index 8a2f5a2..6dbce13 100644 (file)
  * Misc block
  */
 #define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
-#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset))))
-
-#define MISC_MEMORY_REMAP_REG                  MISC_MEM_MAP_VALUE(0x00)
-#define MISC_CHIP_CONFIG_REG                   MISC_MEM_MAP_VALUE(0x04)
-#define MISC_DEBUG_PROBE_DATA_REG              MISC_MEM_MAP_VALUE(0x08)
-#define MISC_DEBUG_PROBE_SELECTION_REG         MISC_MEM_MAP_VALUE(0x0C)
-#define MISC_IO_PIN_FUNC_SELECTION_REG         MISC_MEM_MAP_VALUE(0x10)
-#define MISC_GPIOA_PIN_ENABLE_REG              MISC_MEM_MAP_VALUE(0x14)
-#define MISC_GPIOB_PIN_ENABLE_REG              MISC_MEM_MAP_VALUE(0x18)
-#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A      MISC_MEM_MAP_VALUE(0x1C)
-#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B      MISC_MEM_MAP_VALUE(0x20)
-#define MISC_GPIOA_15_0_PULL_CTRL_REG          MISC_MEM_MAP_VALUE(0x24)
-#define MISC_GPIOA_16_31_PULL_CTRL_REG         MISC_MEM_MAP_VALUE(0x28)
-#define MISC_GPIOB_15_0_PULL_CTRL_REG          MISC_MEM_MAP_VALUE(0x2C)
-#define MISC_GPIOB_16_31_PULL_CTRL_REG         MISC_MEM_MAP_VALUE(0x30)
-#define MISC_IO_PULL_CTRL_REG                  MISC_MEM_MAP_VALUE(0x34)
-#define MISC_E_FUSE_31_0_REG                   MISC_MEM_MAP_VALUE(0x40)
-#define MISC_E_FUSE_63_32_REG                  MISC_MEM_MAP_VALUE(0x44)
-#define MISC_E_FUSE_95_64_REG                  MISC_MEM_MAP_VALUE(0x48)
-#define MISC_E_FUSE_127_96_REG                 MISC_MEM_MAP_VALUE(0x4C)
-#define MISC_SOFTWARE_TEST_1_REG               MISC_MEM_MAP_VALUE(0x50)
-#define MISC_SOFTWARE_TEST_2_REG               MISC_MEM_MAP_VALUE(0x54)
-
-#define MISC_SATA_POWER_MODE                   MISC_MEM_MAP_VALUE(0x310)
-
-#define MISC_USB_CFG_REG                       MISC_MEM_MAP_VALUE(0x800)
-#define MISC_USB_STS_REG                       MISC_MEM_MAP_VALUE(0x804)
-#define MISC_USBPHY00_CFG_REG                  MISC_MEM_MAP_VALUE(0x808)
-#define MISC_USBPHY01_CFG_REG                  MISC_MEM_MAP_VALUE(0x80c)
-#define MISC_USBPHY10_CFG_REG                  MISC_MEM_MAP_VALUE(0x810)
-#define MISC_USBPHY11_CFG_REG                  MISC_MEM_MAP_VALUE(0x814)
+
+#define MISC_MEMORY_REMAP_REG                  MISC_MEM_MAP(0x00)
+#define MISC_CHIP_CONFIG_REG                   MISC_MEM_MAP(0x04)
+#define MISC_DEBUG_PROBE_DATA_REG              MISC_MEM_MAP(0x08)
+#define MISC_DEBUG_PROBE_SELECTION_REG         MISC_MEM_MAP(0x0C)
+#define MISC_IO_PIN_FUNC_SELECTION_REG         MISC_MEM_MAP(0x10)
+#define MISC_GPIOA_PIN_ENABLE_REG              MISC_MEM_MAP(0x14)
+#define MISC_GPIOB_PIN_ENABLE_REG              MISC_MEM_MAP(0x18)
+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A      MISC_MEM_MAP(0x1C)
+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B      MISC_MEM_MAP(0x20)
+#define MISC_GPIOA_15_0_PULL_CTRL_REG          MISC_MEM_MAP(0x24)
+#define MISC_GPIOA_16_31_PULL_CTRL_REG         MISC_MEM_MAP(0x28)
+#define MISC_GPIOB_15_0_PULL_CTRL_REG          MISC_MEM_MAP(0x2C)
+#define MISC_GPIOB_16_31_PULL_CTRL_REG         MISC_MEM_MAP(0x30)
+#define MISC_IO_PULL_CTRL_REG                  MISC_MEM_MAP(0x34)
+#define MISC_E_FUSE_31_0_REG                   MISC_MEM_MAP(0x40)
+#define MISC_E_FUSE_63_32_REG                  MISC_MEM_MAP(0x44)
+#define MISC_E_FUSE_95_64_REG                  MISC_MEM_MAP(0x48)
+#define MISC_E_FUSE_127_96_REG                 MISC_MEM_MAP(0x4C)
+#define MISC_SOFTWARE_TEST_1_REG               MISC_MEM_MAP(0x50)
+#define MISC_SOFTWARE_TEST_2_REG               MISC_MEM_MAP(0x54)
+
+#define MISC_SATA_POWER_MODE                   MISC_MEM_MAP(0x310)
+
+#define MISC_USB_CFG_REG                       MISC_MEM_MAP(0x800)
+#define MISC_USB_STS_REG                       MISC_MEM_MAP(0x804)
+#define MISC_USBPHY00_CFG_REG                  MISC_MEM_MAP(0x808)
+#define MISC_USBPHY01_CFG_REG                  MISC_MEM_MAP(0x80c)
+#define MISC_USBPHY10_CFG_REG                  MISC_MEM_MAP(0x810)
+#define MISC_USBPHY11_CFG_REG                  MISC_MEM_MAP(0x814)
 
 #define MISC_PCIEPHY_CMCTL(x)                  MISC_MEM_MAP(0x900 + (x) * 0x004)
 #define MISC_PCIEPHY_CTL(x)                    MISC_MEM_MAP(0x940 + (x) * 0x100)
 /*
  * Power management and clock control
  */
-#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset))))
-
-#define PM_CLK_GATE_REG                                        PMU_REG_VALUE(0x000)
-#define PM_SOFT_RST_REG                                        PMU_REG_VALUE(0x004)
-#define PM_HS_CFG_REG                                  PMU_REG_VALUE(0x008)
-#define PM_CACTIVE_STA_REG                             PMU_REG_VALUE(0x00C)
-#define PM_PWR_STA_REG                                 PMU_REG_VALUE(0x010)
-#define PM_CLK_CTRL_REG                                        PMU_REG_VALUE(0x014)
-#define PM_PLL_LCD_I2S_CTRL_REG                                PMU_REG_VALUE(0x018)
-#define PM_PLL_HM_PD_CTRL_REG                          PMU_REG_VALUE(0x01C)
-#define PM_REGULAT_CTRL_REG                            PMU_REG_VALUE(0x020)
-#define PM_WDT_CTRL_REG                                        PMU_REG_VALUE(0x024)
-#define PM_WU_CTRL0_REG                                        PMU_REG_VALUE(0x028)
-#define PM_WU_CTRL1_REG                                        PMU_REG_VALUE(0x02C)
-#define PM_CSR_REG                                     PMU_REG_VALUE(0x030)
+#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))
+
+#define PM_CLK_GATE_REG                                        PMU_MEM_MAP(0x000)
+#define PM_SOFT_RST_REG                                        PMU_MEM_MAP(0x004)
+#define PM_HS_CFG_REG                                  PMU_MEM_MAP(0x008)
+#define PM_CACTIVE_STA_REG                             PMU_MEM_MAP(0x00C)
+#define PM_PWR_STA_REG                                 PMU_MEM_MAP(0x010)
+#define PM_CLK_CTRL_REG                                        PMU_MEM_MAP(0x014)
+#define PM_PLL_LCD_I2S_CTRL_REG                                PMU_MEM_MAP(0x018)
+#define PM_PLL_HM_PD_CTRL_REG                          PMU_MEM_MAP(0x01C)
+#define PM_REGULAT_CTRL_REG                            PMU_MEM_MAP(0x020)
+#define PM_WDT_CTRL_REG                                        PMU_MEM_MAP(0x024)
+#define PM_WU_CTRL0_REG                                        PMU_MEM_MAP(0x028)
+#define PM_WU_CTRL1_REG                                        PMU_MEM_MAP(0x02C)
+#define PM_CSR_REG                                     PMU_MEM_MAP(0x030)
 
 /* PM_CLK_GATE_REG */
 #define PM_CLK_GATE_REG_OFFSET_SDIO                    (25)
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
new file mode 100644 (file)
index 0000000..38088c3
--- /dev/null
@@ -0,0 +1,389 @@
+/*
+ * PCI-E support for CNS3xxx
+ *
+ * Copyright 2008 Cavium Networks
+ *               Richard Liu <richard.liu@caviumnetworks.com>
+ * Copyright 2010 MontaVista Software, LLC.
+ *               Anton Vorontsov <avorontsov@mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/bug.h>
+#include <linux/pci.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+#include <asm/mach/map.h>
+#include <mach/cns3xxx.h>
+#include "core.h"
+
+enum cns3xxx_access_type {
+       CNS3XXX_HOST_TYPE = 0,
+       CNS3XXX_CFG0_TYPE,
+       CNS3XXX_CFG1_TYPE,
+       CNS3XXX_NUM_ACCESS_TYPES,
+};
+
+struct cns3xxx_pcie {
+       struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES];
+       unsigned int irqs[2];
+       struct resource res_io;
+       struct resource res_mem;
+       struct hw_pci hw_pci;
+
+       bool linked;
+};
+
+static struct cns3xxx_pcie cns3xxx_pcie[]; /* forward decl. */
+
+static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
+{
+       struct pci_sys_data *root = sysdata;
+
+       return &cns3xxx_pcie[root->domain];
+}
+
+static struct cns3xxx_pcie *pdev_to_cnspci(struct pci_dev *dev)
+{
+       return sysdata_to_cnspci(dev->sysdata);
+}
+
+static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
+{
+       return sysdata_to_cnspci(bus->sysdata);
+}
+
+static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
+                                 unsigned int devfn, int where)
+{
+       struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
+       int busno = bus->number;
+       int slot = PCI_SLOT(devfn);
+       int offset;
+       enum cns3xxx_access_type type;
+       void __iomem *base;
+
+       /* If there is no link, just show the CNS PCI bridge. */
+       if (!cnspci->linked && (busno > 0 || slot > 0))
+               return NULL;
+
+       /*
+        * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
+        * we still want to access it. For this to work, we must place
+        * the first device on the same bus as the CNS PCI bridge.
+        */
+       if (busno == 0) {
+               if (slot > 1)
+                       return NULL;
+               type = slot;
+       } else {
+               type = CNS3XXX_CFG1_TYPE;
+       }
+
+       base = (void __iomem *)cnspci->cfg_bases[type].virtual;
+       offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc);
+
+       return base + offset;
+}
+
+static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+                                  int where, int size, u32 *val)
+{
+       u32 v;
+       void __iomem *base;
+       u32 mask = (0x1ull << (size * 8)) - 1;
+       int shift = (where % 4) * 8;
+
+       base = cns3xxx_pci_cfg_base(bus, devfn, where);
+       if (!base) {
+               *val = 0xffffffff;
+               return PCIBIOS_SUCCESSFUL;
+       }
+
+       v = __raw_readl(base);
+
+       if (bus->number == 0 && devfn == 0 &&
+                       (where & 0xffc) == PCI_CLASS_REVISION) {
+               /*
+                * RC's class is 0xb, but Linux PCI driver needs 0x604
+                * for a PCIe bridge. So we must fixup the class code
+                * to 0x604 here.
+                */
+               v &= 0xff;
+               v |= 0x604 << 16;
+       }
+
+       *val = (v >> shift) & mask;
+
+       return PCIBIOS_SUCCESSFUL;
+}
+
+static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+                                   int where, int size, u32 val)
+{
+       u32 v;
+       void __iomem *base;
+       u32 mask = (0x1ull << (size * 8)) - 1;
+       int shift = (where % 4) * 8;
+
+       base = cns3xxx_pci_cfg_base(bus, devfn, where);
+       if (!base)
+               return PCIBIOS_SUCCESSFUL;
+
+       v = __raw_readl(base);
+
+       v &= ~(mask << shift);
+       v |= (val & mask) << shift;
+
+       __raw_writel(v, base);
+
+       return PCIBIOS_SUCCESSFUL;
+}
+
+static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
+{
+       struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
+       struct resource *res_io = &cnspci->res_io;
+       struct resource *res_mem = &cnspci->res_mem;
+       struct resource **sysres = sys->resource;
+
+       BUG_ON(request_resource(&iomem_resource, res_io) ||
+              request_resource(&iomem_resource, res_mem));
+
+       sysres[0] = res_io;
+       sysres[1] = res_mem;
+
+       return 1;
+}
+
+static struct pci_ops cns3xxx_pcie_ops = {
+       .read = cns3xxx_pci_read_config,
+       .write = cns3xxx_pci_write_config,
+};
+
+static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
+{
+       return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys);
+}
+
+static int cns3xxx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+       struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
+       int irq = cnspci->irqs[slot];
+
+       pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
+               pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
+               PCI_FUNC(dev->devfn), slot, pin, irq);
+
+       return irq;
+}
+
+static struct cns3xxx_pcie cns3xxx_pcie[] = {
+       [0] = {
+               .cfg_bases = {
+                       [CNS3XXX_HOST_TYPE] = {
+                               .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,
+                               .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
+                               .length = SZ_16M,
+                               .type = MT_DEVICE,
+                       },
+                       [CNS3XXX_CFG0_TYPE] = {
+                               .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT,
+                               .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE),
+                               .length = SZ_16M,
+                               .type = MT_DEVICE,
+                       },
+                       [CNS3XXX_CFG1_TYPE] = {
+                               .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT,
+                               .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE),
+                               .length = SZ_16M,
+                               .type = MT_DEVICE,
+                       },
+               },
+               .res_io = {
+                       .name = "PCIe0 I/O space",
+                       .start = CNS3XXX_PCIE0_IO_BASE,
+                       .end = CNS3XXX_PCIE0_IO_BASE + SZ_16M - 1,
+                       .flags = IORESOURCE_IO,
+               },
+               .res_mem = {
+                       .name = "PCIe0 non-prefetchable",
+                       .start = CNS3XXX_PCIE0_MEM_BASE,
+                       .end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1,
+                       .flags = IORESOURCE_MEM,
+               },
+               .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
+               .hw_pci = {
+                       .domain = 0,
+                       .swizzle = pci_std_swizzle,
+                       .nr_controllers = 1,
+                       .setup = cns3xxx_pci_setup,
+                       .scan = cns3xxx_pci_scan_bus,
+                       .map_irq = cns3xxx_pcie_map_irq,
+               },
+       },
+       [1] = {
+               .cfg_bases = {
+                       [CNS3XXX_HOST_TYPE] = {
+                               .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT,
+                               .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE),
+                               .length = SZ_16M,
+                               .type = MT_DEVICE,
+                       },
+                       [CNS3XXX_CFG0_TYPE] = {
+                               .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT,
+                               .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE),
+                               .length = SZ_16M,
+                               .type = MT_DEVICE,
+                       },
+                       [CNS3XXX_CFG1_TYPE] = {
+                               .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT,
+                               .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
+                               .length = SZ_16M,
+                               .type = MT_DEVICE,
+                       },
+               },
+               .res_io = {
+                       .name = "PCIe1 I/O space",
+                       .start = CNS3XXX_PCIE1_IO_BASE,
+                       .end = CNS3XXX_PCIE1_IO_BASE + SZ_16M - 1,
+                       .flags = IORESOURCE_IO,
+               },
+               .res_mem = {
+                       .name = "PCIe1 non-prefetchable",
+                       .start = CNS3XXX_PCIE1_MEM_BASE,
+                       .end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1,
+                       .flags = IORESOURCE_MEM,
+               },
+               .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
+               .hw_pci = {
+                       .domain = 1,
+                       .swizzle = pci_std_swizzle,
+                       .nr_controllers = 1,
+                       .setup = cns3xxx_pci_setup,
+                       .scan = cns3xxx_pci_scan_bus,
+                       .map_irq = cns3xxx_pcie_map_irq,
+               },
+       },
+};
+
+static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
+{
+       int port = cnspci->hw_pci.domain;
+       u32 reg;
+       unsigned long time;
+
+       reg = __raw_readl(MISC_PCIE_CTRL(port));
+       /*
+        * Enable Application Request to 1, it will exit L1 automatically,
+        * but when chip back, it will use another clock, still can use 0x1.
+        */
+       reg |= 0x3;
+       __raw_writel(reg, MISC_PCIE_CTRL(port));
+
+       pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
+       pr_info("PCIe: Port[%d] Check data link layer...", port);
+
+       time = jiffies;
+       while (1) {
+               reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
+               if (reg & 0x1) {
+                       pr_info("Link up.\n");
+                       cnspci->linked = 1;
+                       break;
+               } else if (time_after(jiffies, time + 50)) {
+                       pr_info("Device not found.\n");
+                       break;
+               }
+       }
+}
+
+static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
+{
+       int port = cnspci->hw_pci.domain;
+       struct pci_sys_data sd = {
+               .domain = port,
+       };
+       struct pci_bus bus = {
+               .number = 0,
+               .ops = &cns3xxx_pcie_ops,
+               .sysdata = &sd,
+       };
+       u32 io_base = cnspci->res_io.start >> 16;
+       u32 mem_base = cnspci->res_mem.start >> 16;
+       u32 host_base = cnspci->cfg_bases[CNS3XXX_HOST_TYPE].pfn;
+       u32 cfg0_base = cnspci->cfg_bases[CNS3XXX_CFG0_TYPE].pfn;
+       u32 devfn = 0;
+       u8 tmp8;
+       u16 pos;
+       u16 dc;
+
+       host_base = (__pfn_to_phys(host_base) - 1) >> 16;
+       cfg0_base = (__pfn_to_phys(cfg0_base) - 1) >> 16;
+
+       pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
+       pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
+       pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
+
+       pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8);
+       pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8);
+       pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
+
+       pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
+       pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, host_base);
+       pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
+       pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, cfg0_base);
+
+       if (!cnspci->linked)
+               return;
+
+       /* Set Device Max_Read_Request_Size to 128 byte */
+       devfn = PCI_DEVFN(1, 0);
+       pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
+       pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
+       dc &= ~(0x3 << 12);     /* Clear Device Control Register [14:12] */
+       pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
+       pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
+       if (!(dc & (0x3 << 12)))
+               pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n");
+
+       /* Disable PCIe0 Interrupt Mask INTA to INTD */
+       __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
+}
+
+static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
+                                     struct pt_regs *regs)
+{
+       if (fsr & (1 << 10))
+               regs->ARM_pc += 4;
+       return 0;
+}
+
+static int __init cns3xxx_pcie_init(void)
+{
+       int i;
+
+       hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS,
+                       "imprecise external abort");
+
+       for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
+               iotable_init(cns3xxx_pcie[i].cfg_bases,
+                            ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
+               cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
+               cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
+               cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
+               cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
+               pci_common_init(&cns3xxx_pcie[i].hw_pci);
+       }
+
+       pci_assign_unassigned_resources();
+
+       return 0;
+}
+device_initcall(cns3xxx_pcie_init);
index 725e1a4..38e4470 100644 (file)
@@ -6,18 +6,25 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/io.h>
 #include <linux/delay.h>
 #include <mach/system.h>
 #include <mach/cns3xxx.h>
 
 void cns3xxx_pwr_clk_en(unsigned int block)
 {
-       PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK);
+       u32 reg = __raw_readl(PM_CLK_GATE_REG);
+
+       reg |= (block & PM_CLK_GATE_REG_MASK);
+       __raw_writel(reg, PM_CLK_GATE_REG);
 }
 
 void cns3xxx_pwr_power_up(unsigned int block)
 {
-       PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL);
+       u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
+
+       reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
+       __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
 
        /* Wait for 300us for the PLL output clock locked. */
        udelay(300);
@@ -25,22 +32,29 @@ void cns3xxx_pwr_power_up(unsigned int block)
 
 void cns3xxx_pwr_power_down(unsigned int block)
 {
+       u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
+
        /* write '1' to power down */
-       PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL);
+       reg |= (block & CNS3XXX_PWR_PLL_ALL);
+       __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
 };
 
 static void cns3xxx_pwr_soft_rst_force(unsigned int block)
 {
+       u32 reg = __raw_readl(PM_SOFT_RST_REG);
+
        /*
         * bit 0, 28, 29 => program low to reset,
         * the other else program low and then high
         */
        if (block & 0x30000001) {
-               PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
+               reg &= ~(block & PM_SOFT_RST_REG_MASK);
        } else {
-               PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
-               PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK);
+               reg &= ~(block & PM_SOFT_RST_REG_MASK);
+               reg |= (block & PM_SOFT_RST_REG_MASK);
        }
+
+       __raw_writel(reg, PM_SOFT_RST_REG);
 }
 
 void cns3xxx_pwr_soft_rst(unsigned int block)
@@ -73,12 +87,13 @@ void arch_reset(char mode, const char *cmd)
  */
 int cns3xxx_cpu_clock(void)
 {
+       u32 reg = __raw_readl(PM_CLK_CTRL_REG);
        int cpu;
        int cpu_sel;
        int div_sel;
 
-       cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
-       div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
+       cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
+       div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
 
        cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
 
index a91edfb..22eb97c 100644 (file)
  * below 128M
  */
 static inline void
-__arch_adjust_zones(int node, unsigned long *size, unsigned long *holes)
+__arch_adjust_zones(unsigned long *size, unsigned long *holes)
 {
        unsigned int sz = (128<<20) >> PAGE_SHIFT;
 
-       if (node != 0)
-               sz = 0;
-
        size[1] = size[0] - sz;
        size[0] = sz;
 }
 
-#define arch_adjust_zones(node, zone_size, holes) \
-        if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes)
+#define arch_adjust_zones(zone_size, holes) \
+        if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(zone_size, holes)
 
 #define ISA_DMA_THRESHOLD      (PHYS_OFFSET + (128<<20) - 1)
 #define MAX_DMA_ADDRESS                (PAGE_OFFSET + (128<<20))
index 5da2cf4..f7a1258 100644 (file)
@@ -752,6 +752,67 @@ void __init dove_xor1_init(void)
        platform_device_register(&dove_xor11_channel);
 }
 
+/*****************************************************************************
+ * SDIO
+ ****************************************************************************/
+static u64 sdio_dmamask = DMA_BIT_MASK(32);
+
+static struct resource dove_sdio0_resources[] = {
+       {
+               .start  = DOVE_SDIO0_PHYS_BASE,
+               .end    = DOVE_SDIO0_PHYS_BASE + 0xff,
+               .flags  = IORESOURCE_MEM,
+       }, {
+               .start  = IRQ_DOVE_SDIO0,
+               .end    = IRQ_DOVE_SDIO0,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device dove_sdio0 = {
+       .name           = "sdhci-mv",
+       .id             = 0,
+       .dev            = {
+               .dma_mask               = &sdio_dmamask,
+               .coherent_dma_mask      = DMA_BIT_MASK(32),
+       },
+       .resource       = dove_sdio0_resources,
+       .num_resources  = ARRAY_SIZE(dove_sdio0_resources),
+};
+
+void __init dove_sdio0_init(void)
+{
+       platform_device_register(&dove_sdio0);
+}
+
+static struct resource dove_sdio1_resources[] = {
+       {
+               .start  = DOVE_SDIO1_PHYS_BASE,
+               .end    = DOVE_SDIO1_PHYS_BASE + 0xff,
+               .flags  = IORESOURCE_MEM,
+       }, {
+               .start  = IRQ_DOVE_SDIO1,
+               .end    = IRQ_DOVE_SDIO1,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device dove_sdio1 = {
+       .name           = "sdhci-mv",
+       .id             = 1,
+       .dev            = {
+               .dma_mask               = &sdio_dmamask,
+               .coherent_dma_mask      = DMA_BIT_MASK(32),
+       },
+       .resource       = dove_sdio1_resources,
+       .num_resources  = ARRAY_SIZE(dove_sdio1_resources),
+};
+
+void __init dove_sdio1_init(void)
+{
+       platform_device_register(&dove_sdio1);
+}
+
 void __init dove_init(void)
 {
        int tclk;
index b29e893..a51517c 100644 (file)
@@ -36,5 +36,7 @@ void dove_uart3_init(void);
 void dove_spi0_init(void);
 void dove_spi1_init(void);
 void dove_i2c_init(void);
+void dove_sdio0_init(void);
+void dove_sdio1_init(void);
 
 #endif
index f2971b7..bef7046 100644 (file)
@@ -82,6 +82,8 @@ static void __init dove_db_init(void)
        dove_ehci0_init();
        dove_ehci1_init();
        dove_sata_init(&dove_db_sata_data);
+       dove_sdio0_init();
+       dove_sdio1_init();
        dove_spi0_init();
        dove_spi1_init();
        dove_uart0_init();
index 3a1a855..f744f67 100644 (file)
@@ -13,7 +13,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 
 #include <mach/hardware.h>
 
 #include <asm/mach/arch.h>
 
 
-static struct physmap_flash_data adssphere_flash_data = {
-       .width          = 4,
-};
-
-static struct resource adssphere_flash_resource = {
-       .start          = EP93XX_CS6_PHYS_BASE,
-       .end            = EP93XX_CS6_PHYS_BASE + SZ_32M - 1,
-       .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device adssphere_flash = {
-       .name           = "physmap-flash",
-       .id             = 0,
-       .dev            = {
-               .platform_data  = &adssphere_flash_data,
-       },
-       .num_resources  = 1,
-       .resource       = &adssphere_flash_resource,
-};
-
 static struct ep93xx_eth_data __initdata adssphere_eth_data = {
        .phy_id         = 1,
 };
@@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata adssphere_eth_data = {
 static void __init adssphere_init_machine(void)
 {
        ep93xx_init_devices();
-       platform_device_register(&adssphere_flash);
-
+       ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
        ep93xx_register_eth(&adssphere_eth_data, 1);
 }
 
index e29bdef..7f30397 100644 (file)
@@ -185,7 +185,7 @@ static struct clk_lookup clocks[] = {
        INIT_CK(NULL,                   "pll1",         &clk_pll1),
        INIT_CK(NULL,                   "fclk",         &clk_f),
        INIT_CK(NULL,                   "hclk",         &clk_h),
-       INIT_CK(NULL,                   "pclk",         &clk_p),
+       INIT_CK(NULL,                   "apb_pclk",     &clk_p),
        INIT_CK(NULL,                   "pll2",         &clk_pll2),
        INIT_CK("ep93xx-ohci",          NULL,           &clk_usb_host),
        INIT_CK("ep93xx-keypad",        NULL,           &clk_keypad),
index 9092677..8e37a04 100644 (file)
@@ -29,6 +29,7 @@
 #include <linux/termios.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
+#include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 #include <linux/spi/spi.h>
@@ -215,8 +216,8 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
        spin_lock_irqsave(&syscon_swlock, flags);
 
        val = __raw_readl(EP93XX_SYSCON_DEVCFG);
-       val |= set_bits;
        val &= ~clear_bits;
+       val |= set_bits;
        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
        __raw_writel(val, EP93XX_SYSCON_DEVCFG);
 
@@ -348,6 +349,43 @@ static struct platform_device ep93xx_ohci_device = {
 
 
 /*************************************************************************
+ * EP93xx physmap'ed flash
+ *************************************************************************/
+static struct physmap_flash_data ep93xx_flash_data;
+
+static struct resource ep93xx_flash_resource = {
+       .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device ep93xx_flash = {
+       .name           = "physmap-flash",