ARM: tegra: usb_phy: Fix for glitch on STROBE line
Vinod Atyam [Wed, 20 Jun 2012 17:36:37 +0000 (22:36 +0530)]
Observed glitch on STROBE line during HSIC resume.
This is because after removing the TX circuit power down,
HSIC controller is keeping in reset to program
phy parameters. TX circuit is driving low on STROBE line until
controller removed out of reset.
Now corrected the code to remove power down after setting phy
parameters and removed the reset on HSIC controller.

Bug 991709

Change-Id: I4966ea92752d2e5c6ea7042a6c5fb8707cf6bb35
Signed-off-by: Vinod Atyam <vatyam@nvidia.com>
Reviewed-on: http://git-master/r/110112
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/tegra3_usb_phy.c

index 85fb3db..1922c0b 100644 (file)
@@ -2106,16 +2106,15 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
        }
 
        val = readl(base + UHSIC_PADS_CFG1);
-       val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
+       val &= ~(UHSIC_PD_BG | UHSIC_PD_TRK | UHSIC_PD_RX |
                        UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
-       val |= UHSIC_RX_SEL;
+       val |= (UHSIC_RX_SEL | UHSIC_PD_TX);
        writel(val, base + UHSIC_PADS_CFG1);
-       udelay(2);
 
        val = readl(base + USB_SUSP_CTRL);
        val |= UHSIC_RESET;
        writel(val, base + USB_SUSP_CTRL);
-       udelay(30);
+       udelay(1);
 
        val = readl(base + USB_SUSP_CTRL);
        val |= UHSIC_PHY_ENABLE;
@@ -2154,7 +2153,11 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
        val = readl(base + USB_SUSP_CTRL);
        val &= ~(UHSIC_RESET);
        writel(val, base + USB_SUSP_CTRL);
-       udelay(2);
+       udelay(1);
+
+       val = readl(base + UHSIC_PADS_CFG1);
+       val &= ~(UHSIC_PD_TX);
+       writel(val, base + UHSIC_PADS_CFG1);
 
        val = readl(base + USB_USBMODE);
        val |= USB_USBMODE_HOST;