perf, x86: rename macro in ARCH_PERFMON_EVENTSEL_ENABLE
Robert Richter [Mon, 1 Mar 2010 13:21:23 +0000 (14:21 +0100)]
For consistency reasons this patch renames
ARCH_PERFMON_EVENTSEL0_ENABLE to ARCH_PERFMON_EVENTSEL_ENABLE.

The following is performed:

 $ sed -i -e s/ARCH_PERFMON_EVENTSEL0_ENABLE/ARCH_PERFMON_EVENTSEL_ENABLE/g \
   arch/x86/include/asm/perf_event.h arch/x86/kernel/cpu/perf_event.c \
   arch/x86/kernel/cpu/perf_event_p6.c \
   arch/x86/kernel/cpu/perfctr-watchdog.c \
   arch/x86/oprofile/op_model_amd.c arch/x86/oprofile/op_model_ppro.c

Signed-off-by: Robert Richter <robert.richter@amd.com>

arch/x86/include/asm/perf_event.h
arch/x86/kernel/cpu/perf_event.c
arch/x86/kernel/cpu/perf_event_p6.c
arch/x86/kernel/cpu/perfctr-watchdog.c
arch/x86/oprofile/op_model_amd.c
arch/x86/oprofile/op_model_ppro.c

index c7f60e1..80e6936 100644 (file)
@@ -18,7 +18,7 @@
 #define MSR_ARCH_PERFMON_EVENTSEL0                          0x186
 #define MSR_ARCH_PERFMON_EVENTSEL1                          0x187
 
-#define ARCH_PERFMON_EVENTSEL0_ENABLE                    (1 << 22)
+#define ARCH_PERFMON_EVENTSEL_ENABLE                     (1 << 22)
 #define ARCH_PERFMON_EVENTSEL_ANY                        (1 << 21)
 #define ARCH_PERFMON_EVENTSEL_INT                        (1 << 20)
 #define ARCH_PERFMON_EVENTSEL_OS                         (1 << 17)
index 641ccb9..6531b4b 100644 (file)
@@ -553,9 +553,9 @@ static void x86_pmu_disable_all(void)
                if (!test_bit(idx, cpuc->active_mask))
                        continue;
                rdmsrl(x86_pmu.eventsel + idx, val);
-               if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
+               if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
                        continue;
-               val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
+               val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
                wrmsrl(x86_pmu.eventsel + idx, val);
        }
 }
@@ -590,7 +590,7 @@ static void x86_pmu_enable_all(void)
                        continue;
 
                val = event->hw.config;
-               val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
+               val |= ARCH_PERFMON_EVENTSEL_ENABLE;
                wrmsrl(x86_pmu.eventsel + idx, val);
        }
 }
@@ -853,7 +853,7 @@ void hw_perf_enable(void)
 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
 {
        (void)checking_wrmsrl(hwc->config_base + idx,
-                             hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
+                             hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);
 }
 
 static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx)
index 1ca5ba0..a4e67b9 100644 (file)
@@ -62,7 +62,7 @@ static void p6_pmu_disable_all(void)
 
        /* p6 only has one enable register */
        rdmsrl(MSR_P6_EVNTSEL0, val);
-       val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
+       val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
        wrmsrl(MSR_P6_EVNTSEL0, val);
 }
 
@@ -72,7 +72,7 @@ static void p6_pmu_enable_all(void)
 
        /* p6 only has one enable register */
        rdmsrl(MSR_P6_EVNTSEL0, val);
-       val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
+       val |= ARCH_PERFMON_EVENTSEL_ENABLE;
        wrmsrl(MSR_P6_EVNTSEL0, val);
 }
 
@@ -83,7 +83,7 @@ p6_pmu_disable_event(struct hw_perf_event *hwc, int idx)
        u64 val = P6_NOP_EVENT;
 
        if (cpuc->enabled)
-               val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
+               val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 
        (void)checking_wrmsrl(hwc->config_base + idx, val);
 }
@@ -95,7 +95,7 @@ static void p6_pmu_enable_event(struct hw_perf_event *hwc, int idx)
 
        val = hwc->config;
        if (cpuc->enabled)
-               val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
+               val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 
        (void)checking_wrmsrl(hwc->config_base + idx, val);
 }
index 74f4e85..fb329e9 100644 (file)
@@ -680,7 +680,7 @@ static int setup_intel_arch_watchdog(unsigned nmi_hz)
        cpu_nmi_set_wd_enabled();
 
        apic_write(APIC_LVTPC, APIC_DM_NMI);
-       evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
+       evntsel |= ARCH_PERFMON_EVENTSEL_ENABLE;
        wrmsr(evntsel_msr, evntsel, 0);
        intel_arch_wd_ops.checkbit = 1ULL << (eax.split.bit_width - 1);
        return 1;
index 8ddb9fa..090cbbe 100644 (file)
@@ -171,7 +171,7 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
                        continue;
                }
                rdmsrl(msrs->controls[i].addr, val);
-               if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
+               if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
                        op_x86_warn_in_use(i);
                val &= model->reserved;
                wrmsrl(msrs->controls[i].addr, val);
@@ -398,7 +398,7 @@ static void op_amd_start(struct op_msrs const * const msrs)
                if (!reset_value[op_x86_phys_to_virt(i)])
                        continue;
                rdmsrl(msrs->controls[i].addr, val);
-               val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
+               val |= ARCH_PERFMON_EVENTSEL_ENABLE;
                wrmsrl(msrs->controls[i].addr, val);
        }
 
@@ -418,7 +418,7 @@ static void op_amd_stop(struct op_msrs const * const msrs)
                if (!reset_value[op_x86_phys_to_virt(i)])
                        continue;
                rdmsrl(msrs->controls[i].addr, val);
-               val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
+               val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
                wrmsrl(msrs->controls[i].addr, val);
        }
 
index 5d1727b..2bf90fa 100644 (file)
@@ -88,7 +88,7 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
                        continue;
                }
                rdmsrl(msrs->controls[i].addr, val);
-               if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
+               if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
                        op_x86_warn_in_use(i);
                val &= model->reserved;
                wrmsrl(msrs->controls[i].addr, val);
@@ -166,7 +166,7 @@ static void ppro_start(struct op_msrs const * const msrs)
        for (i = 0; i < num_counters; ++i) {
                if (reset_value[i]) {
                        rdmsrl(msrs->controls[i].addr, val);
-                       val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
+                       val |= ARCH_PERFMON_EVENTSEL_ENABLE;
                        wrmsrl(msrs->controls[i].addr, val);
                }
        }
@@ -184,7 +184,7 @@ static void ppro_stop(struct op_msrs const * const msrs)
                if (!reset_value[i])
                        continue;
                rdmsrl(msrs->controls[i].addr, val);
-               val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
+               val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
                wrmsrl(msrs->controls[i].addr, val);
        }
 }