Allow the L2X0 outer cache support to be configurable
Catalin Marinas [Fri, 18 Apr 2008 21:43:17 +0000 (22:43 +0100)]
By default, this option was selected by the platform Kconfig. This
patch adds "depends on" to L2X0 so that it can be enabled/disabled
manually.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

arch/arm/mach-realview/Kconfig
arch/arm/mach-realview/realview_eb.c
arch/arm/mach-realview/realview_pb1176.c
arch/arm/mach-realview/realview_pb11mp.c
arch/arm/mm/Kconfig

index eba1a8c..5ccde7c 100644 (file)
@@ -10,7 +10,6 @@ config MACH_REALVIEW_EB
 config REALVIEW_EB_ARM11MP
        bool "Support ARM11MPCore tile"
        depends on MACH_REALVIEW_EB
-       select CACHE_L2X0
        help
          Enable support for the ARM11MPCore tile on the Realview platform.
 
@@ -27,7 +26,6 @@ config REALVIEW_EB_ARM11MP_REVB
 config MACH_REALVIEW_PB11MP
        bool "Support RealView/PB11MPCore platform"
        select ARM_GIC
-       select CACHE_L2X0
        help
          Include support for the ARM(R) RealView MPCore Platform Baseboard.
          PB11MPCore is a platform with an on-board ARM11MPCore and has
@@ -36,7 +34,6 @@ config MACH_REALVIEW_PB11MP
 config MACH_REALVIEW_PB1176
        bool "Support RealView/PB1176 platform"
        select ARM_GIC
-       select CACHE_L2X0
        help
          Include support for the ARM(R) RealView ARM1176 Platform Baseboard.
 
index 247b556..5782d83 100644 (file)
@@ -365,9 +365,11 @@ static void __init realview_eb_init(void)
        if (core_tile_eb11mp()) {
                realview_eb11mp_fixup();
 
+#ifdef CONFIG_CACHE_L2X0
                /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
                 * Bits:  .... ...0 0111 1001 0000 .... .... .... */
                l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
+#endif
        }
 
        clk_register(&realview_clcd_clk);
index 4e67310..cf7f576 100644 (file)
@@ -260,8 +260,10 @@ static void __init realview_pb1176_init(void)
 {
        int i;
 
+#ifdef CONFIG_CACHE_L2X0
        /* 128Kb (16Kb/way) 8-way associativity. evmon/parity/share enabled. */
        l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff);
+#endif
 
        clk_register(&realview_clcd_clk);
 
index 7d1fa1f..f7ce1c5 100644 (file)
@@ -306,9 +306,11 @@ static void __init realview_pb11mp_init(void)
 {
        int i;
 
+#ifdef CONFIG_CACHE_L2X0
        /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
         * Bits:  .... ...0 0111 1001 0000 .... .... .... */
        l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
+#endif
 
        clk_register(&realview_clcd_clk);
 
index f405435..3696f4f 100644 (file)
@@ -701,5 +701,9 @@ config OUTER_CACHE
        default n
 
 config CACHE_L2X0
-       bool
+       bool "Enable the L2x0 outer cache controller"
+       depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
+       default y
        select OUTER_CACHE
+       help
+         This option enables the L2x0 PrimeCell.