bnx2: Fix register printouts during NETEV_WATCHDOG.
Eddie Wai [Tue, 18 May 2010 00:32:56 +0000 (17:32 -0700)]
Dump the correct MCP registers and add EMAC_RX_STATUS register during
NETDEV_WATCHDOG for debugging.

Signed-off-by: Eddie Wai <waie@broadcom.com>
Signed-off-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

drivers/net/bnx2.c
drivers/net/bnx2.h

index 667f419..c281218 100644 (file)
@@ -6301,14 +6301,23 @@ static void
 bnx2_dump_state(struct bnx2 *bp)
 {
        struct net_device *dev = bp->dev;
+       u32 mcp_p0, mcp_p1;
 
        netdev_err(dev, "DEBUG: intr_sem[%x]\n", atomic_read(&bp->intr_sem));
-       netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] RPM_MGMT_PKT_CTRL[%08x]\n",
+       netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
                   REG_RD(bp, BNX2_EMAC_TX_STATUS),
+                  REG_RD(bp, BNX2_EMAC_RX_STATUS));
+       netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
                   REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
+       if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+               mcp_p0 = BNX2_MCP_STATE_P0;
+               mcp_p1 = BNX2_MCP_STATE_P1;
+       } else {
+               mcp_p0 = BNX2_MCP_STATE_P0_5708;
+               mcp_p1 = BNX2_MCP_STATE_P1_5708;
+       }
        netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
-                  bnx2_reg_rd_ind(bp, BNX2_MCP_STATE_P0),
-                  bnx2_reg_rd_ind(bp, BNX2_MCP_STATE_P1));
+                  bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
        netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
                   REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
        if (bp->flags & BNX2_FLAG_USING_MSIX)
index dd35bd0..ddaa3fc 100644 (file)
@@ -6347,6 +6347,8 @@ struct l2_fhdr {
 #define BNX2_MCP_SCRATCH                               0x00160000
 #define BNX2_MCP_STATE_P1                               0x0016f9c8
 #define BNX2_MCP_STATE_P0                               0x0016fdc8
+#define BNX2_MCP_STATE_P1_5708                          0x001699c8
+#define BNX2_MCP_STATE_P0_5708                          0x00169dc8
 
 #define BNX2_SHM_HDR_SIGNATURE                         BNX2_MCP_SCRATCH
 #define BNX2_SHM_HDR_SIGNATURE_SIG_MASK                         0xffff0000