ARM: tegra: pluto: Change clock source pll_m to pll_p
Vijay Mali [Tue, 2 Oct 2012 21:09:10 +0000 (14:09 -0700)]
Change clock source from pll_m to pll_p for lower emc frequencies

Signed-off-by: Vijay Mali <vmali@nvidia.com>
Reviewed-on: http://git-master/r/143406
(cherry picked from commit bdd5886c50ba44a3092b2dc39d5c341dedab3d76)

Change-Id: I869a274d0f895bdc3609f81304d3ea1a5e8f9dd6

Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Change-Id: I4d9fb86966fbef670506f30153524724fe75d2b0
Reviewed-on: http://git-master/r/146338
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Tested-by: Vijay Mali <vmali@nvidia.com>

arch/arm/mach-tegra/board-pluto-memory.c

index c4fb06e..8273976 100644 (file)
@@ -33,7 +33,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8jtmlar_ntm_table[] = {
                0x40,       /* Rev 4.0 */
                12750,      /* SDRAM frequency */
                1100,       /* min voltage */
-               "pll_m",    /* clock source id */
+               "pll_p",    /* clock source id */
                0x0000001e, /* CLK_SOURCE_EMC */
                99,         /* number of burst_regs */
                30,         /* number of trim_regs (each channel) */
@@ -228,7 +228,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8jtmlar_ntm_table[] = {
                0x40,       /* Rev 4.0 */
                25500,      /* SDRAM frequency */
                1100,       /* min voltage */
-               "pll_m",    /* clock source id */
+               "pll_p",    /* clock source id */
                0x0000000e, /* CLK_SOURCE_EMC */
                99,         /* number of burst_regs */
                30,         /* number of trim_regs (each channel) */
@@ -423,7 +423,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8jtmlar_ntm_table[] = {
                0x40,       /* Rev 4.0 */
                51000,      /* SDRAM frequency */
                1100,       /* min voltage */
-               "pll_m",    /* clock source id */
+               "pll_p",    /* clock source id */
                0x00000006, /* CLK_SOURCE_EMC */
                99,         /* number of burst_regs */
                30,         /* number of trim_regs (each channel) */
@@ -618,7 +618,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8jtmlar_ntm_table[] = {
                0x40,       /* Rev 4.0 */
                102000,     /* SDRAM frequency */
                1100,       /* min voltage */
-               "pll_m",    /* clock source id */
+               "pll_p",    /* clock source id */
                0x00000002, /* CLK_SOURCE_EMC */
                99,         /* number of burst_regs */
                30,         /* number of trim_regs (each channel) */
@@ -813,7 +813,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8jtmlar_ntm_table[] = {
                0x40,       /* Rev 4.0 */
                204000,     /* SDRAM frequency */
                1100,       /* min voltage */
-               "pll_m",    /* clock source id */
+               "pll_p",    /* clock source id */
                0x80000000, /* CLK_SOURCE_EMC */
                99,         /* number of burst_regs */
                30,         /* number of trim_regs (each channel) */