ARM: tegra: clock: Support restricted PLLM usage
Alex Frid [Sat, 12 Nov 2011 02:19:16 +0000 (18:19 -0800)]
Added configuration option TEGRA_PLLM_RESTRICTED - when enabled,
PLLM - memory PLL - usage may be restricted to modules with dividers
capable of dividing maximum PLLM frequency at minimum voltage. When
disabled, PLLM is available as a clock source with no restrictions
(current configuration), which may effectively increase lower limit
for core voltage if high grade SDRAM is used.

Implemented PLLM restrictions in Tegra3 clock framework and DVFS, but
keep them disabled by default.

Bug 884419

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 5313ebcae92839146870d5865bc0f4cd08b35c61)
(cherry picked from commit 634647a9d2a8c1e03c8d98d0b2199950c947acc3)

Change-Id: I012452d92830ad6b63ec407350568b8c316b3caa
Reviewed-on: http://git-master/r/66512
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: Rded91b0aab5167ab2c6aa4ff3a7b7c7829cb221c

arch/arm/mach-tegra/board-cardhu.c

index 1365e04..da4b14c 100644 (file)
@@ -324,7 +324,9 @@ static struct platform_device *cardhu_uart_devices[] __initdata = {
 static struct uart_clk_parent uart_parent_clk[] = {
        [0] = {.name = "clk_m"},
        [1] = {.name = "pll_p"},
+#ifndef CONFIG_TEGRA_PLLM_RESTRICTED
        [2] = {.name = "pll_m"},
+#endif
 };
 
 static struct tegra_uart_platform_data cardhu_uart_pdata;
@@ -467,8 +469,12 @@ static struct platform_device *cardhu_spi_devices[] __initdata = {
 
 struct spi_clk_parent spi_parent_clk[] = {
        [0] = {.name = "pll_p"},
+#ifndef CONFIG_TEGRA_PLLM_RESTRICTED
        [1] = {.name = "pll_m"},
        [2] = {.name = "clk_m"},
+#else
+       [1] = {.name = "clk_m"},
+#endif
 };
 
 static struct tegra_spi_platform_data cardhu_spi_pdata = {