mlx4_core: Get ethernet MTU and default address from firmware
Yevgeny Petrilin [Wed, 22 Oct 2008 17:56:48 +0000 (10:56 -0700)]
Get maximum ethernet MTU and default MAC address from the firmware
QUERY_DEV_CAP command.

Signed-off-by: Yevgeny Petrilin <yevgenyp@mellanox.co.il>
Signed-off-by: Roland Dreier <rolandd@cisco.com>

drivers/net/mlx4/fw.c
drivers/net/mlx4/fw.h
drivers/net/mlx4/main.c
include/linux/mlx4/device.h

index 40d8142..8d402db 100644 (file)
@@ -346,7 +346,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
                        MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
                        dev_cap->max_vl[i]         = field >> 4;
                        MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
-                       dev_cap->max_mtu[i]        = field >> 4;
+                       dev_cap->ib_mtu[i]         = field >> 4;
                        dev_cap->max_port_width[i] = field & 0xf;
                        MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
                        dev_cap->max_gids[i]       = 1 << (field & 0xf);
@@ -355,8 +355,10 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
                }
        } else {
 #define QUERY_PORT_MTU_OFFSET                  0x01
+#define QUERY_PORT_ETH_MTU_OFFSET              0x02
 #define QUERY_PORT_WIDTH_OFFSET                        0x06
 #define QUERY_PORT_MAX_GID_PKEY_OFFSET         0x07
+#define QUERY_PORT_MAC_OFFSET                  0x08
 #define QUERY_PORT_MAX_MACVLAN_OFFSET          0x0a
 #define QUERY_PORT_MAX_VL_OFFSET               0x0b
 
@@ -367,7 +369,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
                                goto out;
 
                        MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
-                       dev_cap->max_mtu[i]        = field & 0xf;
+                       dev_cap->ib_mtu[i]         = field & 0xf;
                        MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
                        dev_cap->max_port_width[i] = field & 0xf;
                        MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
@@ -378,7 +380,8 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
                        MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
                        dev_cap->log_max_macs[i]  = field & 0xf;
                        dev_cap->log_max_vlans[i] = field >> 4;
-
+                       MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
+                       MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
                }
        }
 
@@ -412,7 +415,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
        mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
                 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
        mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
-                dev_cap->local_ca_ack_delay, 128 << dev_cap->max_mtu[1],
+                dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
                 dev_cap->max_port_width[1]);
        mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
                 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
@@ -824,7 +827,7 @@ int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
                flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
                MLX4_PUT(inbox, flags,            INIT_PORT_FLAGS_OFFSET);
 
-               field = 128 << dev->caps.mtu_cap[port];
+               field = 128 << dev->caps.ib_mtu_cap[port];
                MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
                field = dev->caps.gid_table_len[port];
                MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
index c34e726..d0913d4 100644 (file)
@@ -66,11 +66,13 @@ struct mlx4_dev_cap {
        int local_ca_ack_delay;
        int num_ports;
        u32 max_msg_sz;
-       int max_mtu[MLX4_MAX_PORTS + 1];
+       int ib_mtu[MLX4_MAX_PORTS + 1];
        int max_port_width[MLX4_MAX_PORTS + 1];
        int max_vl[MLX4_MAX_PORTS + 1];
        int max_gids[MLX4_MAX_PORTS + 1];
        int max_pkeys[MLX4_MAX_PORTS + 1];
+       u64 def_mac[MLX4_MAX_PORTS + 1];
+       u16 eth_mtu[MLX4_MAX_PORTS + 1];
        u16 stat_rate_support;
        u32 flags;
        int reserved_uars;
index 560e196..28f36b8 100644 (file)
@@ -133,10 +133,12 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
        dev->caps.num_ports          = dev_cap->num_ports;
        for (i = 1; i <= dev->caps.num_ports; ++i) {
                dev->caps.vl_cap[i]         = dev_cap->max_vl[i];
-               dev->caps.mtu_cap[i]        = dev_cap->max_mtu[i];
+               dev->caps.ib_mtu_cap[i]     = dev_cap->ib_mtu[i];
                dev->caps.gid_table_len[i]  = dev_cap->max_gids[i];
                dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
                dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
+               dev->caps.eth_mtu_cap[i]    = dev_cap->eth_mtu[i];
+               dev->caps.def_mac[i]        = dev_cap->def_mac[i];
        }
 
        dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
index 693f93c..f9e73cf 100644 (file)
@@ -166,7 +166,9 @@ struct mlx4_caps {
        u64                     fw_ver;
        int                     num_ports;
        int                     vl_cap[MLX4_MAX_PORTS + 1];
-       int                     mtu_cap[MLX4_MAX_PORTS + 1];
+       int                     ib_mtu_cap[MLX4_MAX_PORTS + 1];
+       u64                     def_mac[MLX4_MAX_PORTS + 1];
+       int                     eth_mtu_cap[MLX4_MAX_PORTS + 1];
        int                     gid_table_len[MLX4_MAX_PORTS + 1];
        int                     pkey_table_len[MLX4_MAX_PORTS + 1];
        int                     local_ca_ack_delay;