video: tegra: host: retune 3dfs algorithm for 114
Samuel Russell [Wed, 13 Feb 2013 23:43:59 +0000 (15:43 -0800)]
Adjust the tuning of 3dfs for 114 chips to perform better for
increased POR clocks.

Bug 1220024
Bug 1232650
Bug 1231533

Change-Id: I2e5ff3e86c84fc2180c8500e6d109fe85410d833
Signed-off-by: Samuel Russell <samuelr@nvidia.com>
Reviewed-on: http://git-master/r/200582
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijay Gupta <vijayg@nvidia.com>
Tested-by: Vijay Gupta <vijayg@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/video/tegra/host/gr3d/pod_scaling.c

index 55e3c0b..ddde17d 100644 (file)
@@ -884,8 +884,8 @@ static int nvhost_pod_init(struct devfreq *df)
                podgov->idle_max = podgov->p_idle_max = 500;
                podgov->p_hint_lo_limit = 500;
                podgov->p_hint_hi_limit = 997;
-               podgov->p_scaleup_limit = 1400;
-               podgov->p_scaledown_limit = 1600;
+               podgov->p_scaleup_limit = 1100;
+               podgov->p_scaledown_limit = 1300;
                podgov->p_smooth = 3;
        } else {
                podgov->idle_min = podgov->p_idle_min = 100;