Merge branch 'master' of ssh://infradead/~/public_git/wireless-next into for-davem
John W. Linville [Mon, 19 Sep 2011 19:00:16 +0000 (15:00 -0400)]
1  2 
MAINTAINERS
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
drivers/net/wireless/ath/ath9k/ar9003_phy.h
drivers/net/wireless/rt2x00/rt2800usb.c
net/mac80211/agg-rx.c
net/mac80211/cfg.c
net/mac80211/iface.c
net/mac80211/mesh_pathtbl.c
net/mac80211/sta_info.c

diff --cc MAINTAINERS
Simple merge
   */
  #define AR_SM1_BASE   0xb200
  
- #define AR_PHY_SWITCH_CHAIN_1    (AR_SM1_BASE + 0x84)
- #define AR_PHY_FCAL_2_1          (AR_SM1_BASE + 0xd0)
- #define AR_PHY_DFT_TONE_CTL_1    (AR_SM1_BASE + 0xd4)
- #define AR_PHY_CL_TAB_1          (AR_SM1_BASE + 0x100)
- #define AR_PHY_CHAN_INFO_GAIN_1  (AR_SM1_BASE + 0x180)
- #define AR_PHY_TPC_4_B1          (AR_SM1_BASE + 0x204)
- #define AR_PHY_TPC_5_B1          (AR_SM1_BASE + 0x208)
- #define AR_PHY_TPC_6_B1          (AR_SM1_BASE + 0x20c)
- #define AR_PHY_TPC_11_B1         (AR_SM1_BASE + 0x220)
- #define AR_PHY_PDADC_TAB_1       (AR_SM1_BASE + 0x240)
+ #define AR_PHY_SWITCH_CHAIN_1   (AR_SM1_BASE + 0x84)
+ #define AR_PHY_FCAL_2_1         (AR_SM1_BASE + 0xd0)
+ #define AR_PHY_DFT_TONE_CTL_1   (AR_SM1_BASE + 0xd4)
+ #define AR_PHY_CL_TAB_1         (AR_SM1_BASE + 0x100)
+ #define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180)
+ #define AR_PHY_TPC_4_B1         (AR_SM1_BASE + 0x204)
+ #define AR_PHY_TPC_5_B1         (AR_SM1_BASE + 0x208)
+ #define AR_PHY_TPC_6_B1         (AR_SM1_BASE + 0x20c)
+ #define AR_PHY_TPC_11_B1        (AR_SM1_BASE + 0x220)
+ #define AR_PHY_PDADC_TAB_1    (AR_SM1_BASE + (AR_SREV_AR9300(ah) ? \
+                                       0x240 : 0x280))
+ #define AR_PHY_TPC_19_B1      (AR_SM1_BASE + 0x240)
+ #define AR_PHY_TPC_19_B1_ALPHA_THERM          0xff
+ #define AR_PHY_TPC_19_B1_ALPHA_THERM_S                0
  #define AR_PHY_TX_IQCAL_STATUS_B1   (AR_SM1_BASE + 0x48c)
 -#define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i)    (AR_SM_BASE + 0x450 + ((_i) << 2))
 +#define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i)    (AR_SM1_BASE + 0x450 + ((_i) << 2))
  
+ /* SM 1 AIC Registers */
+ #define AR_PHY_AIC_CTRL_0_B1  (AR_SM1_BASE + 0x4b0)
+ #define AR_PHY_AIC_CTRL_1_B1  (AR_SM1_BASE + 0x4b4)
+ #define AR_PHY_AIC_CTRL_2_B1  (AR_SM1_BASE + 0x4b8)
+ #define AR_PHY_AIC_STAT_0_B1  (AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \
+                                       0x4c0 : 0x4c4))
+ #define AR_PHY_AIC_STAT_1_B1  (AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \
+                                       0x4c4 : 0x4c8))
+ #define AR_PHY_AIC_CTRL_4_B1  (AR_SM1_BASE + 0x4c0)
+ #define AR_PHY_AIC_STAT_2_B1  (AR_SM1_BASE + 0x4cc)
+ #define AR_PHY_AIC_SRAM_ADDR_B1       (AR_SM1_BASE + 0x5f0)
+ #define AR_PHY_AIC_SRAM_DATA_B1       (AR_SM1_BASE + 0x5f4)
  /*
   * Channel 2 Register Map
   */
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge