drivers: video: tegra: dc: Expose HBR capability
Rahul Mittal [Mon, 29 Oct 2012 12:50:47 +0000 (17:50 +0530)]
Enable HBR bit in HDMI_NV_PDISP_SOR_AUDIO_SPARE0_0 register
This exposes HBR pin capability in HD-Audio codec

Bug 966764

Change-Id: I5253daf9e2864b728bf8aab1a71a2f0e4230debd
Signed-off-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-on: http://git-master/r/159550
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

drivers/video/tegra/dc/hdmi.c
drivers/video/tegra/dc/hdmi_reg.h

index 74fc3d6..09f1f38 100644 (file)
@@ -1910,6 +1910,11 @@ static int tegra_dc_hdmi_setup_audio(struct tegra_dc *dc, unsigned audio_freq,
                          AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
                          AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0),
                          HDMI_NV_PDISP_AUDIO_CNTRL0);
+#if !defined(CONFIG_ARCH_TEGRA_3x_SOC)
+       tegra_hdmi_writel(hdmi, (1 << HDMI_AUDIO_HBR_ENABLE_SHIFT) |
+          tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0_0),
+          HDMI_NV_PDISP_SOR_AUDIO_SPARE0_0);
+#endif
 #else
        tegra_hdmi_writel(hdmi,
                          AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
index 2d127c4..124ebc7 100644 (file)
 #define HDMI_NV_PDISP_AUDIO_CNTRL0                             0x8b
 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_0               0xac
+#if !defined(CONFIG_ARCH_TEGRA_3x_SOC)
+#define HDMI_NV_PDISP_SOR_AUDIO_SPARE0_0               0xae
+#define HDMI_AUDIO_HBR_ENABLE_SHIFT            27
+#endif
 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0                0xbc
 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0         0xbd
 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320_0                    0xbf