ARM: tegra11x: Simplify cpu hotplug sequence
Bo Yan [Tue, 20 Nov 2012 04:58:52 +0000 (20:58 -0800)]
There is no need to clear CPU CSR register. The "ENABLE" bit (bit 0)
is set by software, but cleared by hardware once the sequence is
completed. In case of failure, it's desirable not to change it for
debug purpose.

After CPU_CSR clear is removed, the power mask is set by the CPU
that's booting up.

Change-Id: I4879c64ec5858ed85008fbeeedb8232e35643a8c
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/164891
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

arch/arm/mach-tegra/headsmp.S
arch/arm/mach-tegra/platsmp.c

index fb7c3f6..048d1db 100644 (file)
@@ -62,14 +62,6 @@ ENTRY(tegra_secondary_startup)
        mov     r0, #1
        mcr     p15, 0, r0, c9, c14, 0
 
-#ifdef CONFIG_ARCH_TEGRA_11x_SOC
-       cpu_id  r0
-       cpu_to_csr_reg  r1, r0
-       mov32   r2, TEGRA_FLOW_CTRL_BASE
-       mov     r0, #0
-       str     r0, [r2, r1]
-#endif
-
        b       secondary_startup
 ENDPROC(tegra_secondary_startup)
 #endif
index c931803..4c79e9f 100644 (file)
@@ -163,20 +163,12 @@ static bool is_cpu_powered(unsigned int cpu)
                return tegra_powergate_is_powered(TEGRA_CPU_POWERGATE_ID(cpu));
 }
 
-static bool is_clamp_removed(unsigned int cpu)
-{
-       u32 reg;
-
-       reg = pmc_readl(CLAMP_STATUS);
-
-       return !((reg >> TEGRA_CPU_POWERGATE_ID(cpu)) & 1);
-}
-
 static void __cpuinit tegra_secondary_init(unsigned int cpu)
 {
        gic_secondary_init(0);
 
        cpumask_set_cpu(cpu, to_cpumask(tegra_cpu_init_bits));
+       cpumask_set_cpu(cpu, tegra_cpu_power_mask);
        if (!tegra_all_cpus_booted)
                if (cpumask_equal(tegra_cpu_init_mask, cpu_present_mask))
                        tegra_all_cpus_booted = true;
@@ -265,20 +257,15 @@ fail:
 
 static int tegra11x_power_up_cpu(unsigned int cpu)
 {
-       unsigned long timeout;
-
        BUG_ON(cpu == smp_processor_id());
        BUG_ON(is_lp_cluster());
 
        cpu = cpu_logical_map(cpu);
 
        if (cpu_isset(cpu, tegra_cpu_power_map)) {
-
                /* set SCLK as event trigger for flow conroller */
                flowctrl_write_cpu_csr(cpu, 0x1);
                flowctrl_write_cpu_halt(cpu, 0x48000000);
-               return 0;
-
        } else {
                u32 reg;
 
@@ -286,22 +273,7 @@ static int tegra11x_power_up_cpu(unsigned int cpu)
                pmc_writel(reg, PWRGATE_TOGGLE);
        }
 
-       /* Wait for the power to come up. */
-       timeout = jiffies + msecs_to_jiffies(100);
-       do {
-               if ((is_cpu_powered(cpu) && is_clamp_removed(cpu)) ||
-                       cpu_online(cpu)) {
-                       cpumask_set_cpu(cpu, tegra_cpu_power_mask);
-                       wmb();
-                       return 0;
-               }
-               udelay(10);
-       } while (time_before(jiffies, timeout));
-
-       /* Clear flow controller CSR. */
-       flowctrl_write_cpu_csr(cpu, 0);
-
-       return -ETIMEDOUT;
+       return 0;
 }
 
 int tegra_boot_secondary(unsigned int cpu, struct task_struct *idle)