media: video: fix clock settings for Tegra VI driver
Bryan Wu [Wed, 4 Jun 2014 18:16:32 +0000 (11:16 -0700)]
 - remove reduntant emc clock rate set which is controlled by DVFS
 - VI's maxim working clock freq is 300MHz
 - Change VI clock divider from an integer to a decimal, so the
   maxim VI clock on Cardhu should be 272MHz (PLL_P is 408MHz and
   divider is 1.5)

Bug 1478352

Change-Id: I4028ed8531d92300d131befb53a4c9dc9f90930d
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/419071
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Tested-by: Winnie Hsu <whsu@nvidia.com>

arch/arm/mach-tegra/tegra3_clocks.c
drivers/media/video/tegra_v4l2_camera.c

index 0bc6086..e9d29d4 100644 (file)
@@ -4369,7 +4369,7 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("uartc_dbg", "serial8250.0",         "uartc", 55,    0x1a0,  900000000, mux_pllp_clkm,               MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
        PERIPH_CLK("uartd_dbg", "serial8250.0",         "uartd", 65,    0x1c0,  900000000, mux_pllp_clkm,               MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
        PERIPH_CLK("uarte_dbg", "serial8250.0",         "uarte", 66,    0x1c4,  900000000, mux_pllp_clkm,               MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
-       PERIPH_CLK_EX("vi",     "tegra_camera",         "vi",   20,     0x148,  470000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT,    &tegra_vi_clk_ops),
+       PERIPH_CLK_EX("vi",     "tegra_camera",         "vi",   20,     0x148,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71, &tegra_vi_clk_ops),
        PERIPH_CLK("vi_sensor", "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  600000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
        PERIPH_CLK("3d2",       "3d2",                  NULL,   98,     0x3b0,  600000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
index 237441f..8834e27 100644 (file)
@@ -1000,7 +1000,7 @@ static void tegra_camera_activate(struct tegra_camera_dev *pcdev)
        tegra_unpowergate_partition(TEGRA_POWERGATE_VENC);
 
        /* Turn on relevant clocks. */
-       clk_set_rate(pcdev->clk_vi, 150000000);
+       clk_set_rate(pcdev->clk_vi, 300000000);
        clk_enable(pcdev->clk_vi);
        clk_set_rate(pcdev->clk_vi_sensor, 24000000);
        clk_enable(pcdev->clk_vi_sensor);
@@ -1009,7 +1009,6 @@ static void tegra_camera_activate(struct tegra_camera_dev *pcdev)
        clk_enable(pcdev->clk_csus);
        clk_set_rate(pcdev->clk_sclk, 80000000);
        clk_enable(pcdev->clk_sclk);
-       clk_set_rate(pcdev->clk_sclk, 375000000);
        clk_enable(pcdev->clk_emc);
 
        /* Save current syncpt values. */
@@ -1887,7 +1886,7 @@ static int __devinit tegra_camera_probe(struct nvhost_device *ndev,
                goto exit_put_clk_sclk;
        }
 
-       clk_set_rate(pcdev->clk_vi, 150000000);
+       clk_set_rate(pcdev->clk_vi, 300000000);
        clk_set_rate(pcdev->clk_vi_sensor, 24000000);
 
        /* Get regulator pointer */