arm: tegra: Board files settings for LP1 0.95V CoreV
Karthik Ramakrishnan [Sat, 11 Aug 2012 00:24:20 +0000 (17:24 -0700)]
Set the register values for each of the board files to
keep the Core voltage to 0.95V in LP1.

This change is only for those platforms where LP1 is supported.
Enterprise and Kai are the main platforms for this change. There
is no support for Cardhu for LP1 and so is left blank and the
feature will be skipped for Cardhu platforms, except for AP37.
AP37 with a PM269 board needs this change and so Cardhu board
file is updated with the values specific to AP37.

This change is part of the feature to set VCore to 0.95V
Refer to http://git-master/r/124135 for more details
Bug 1035684

Change-Id: I6d1d984b0e7968b441cebbc37705c25647a4a85a
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
(cherry picked from commit b46921e475bd95e729896a6763bc94df1e03ee4a)
Reviewed-on: http://git-master/r/124780
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

arch/arm/mach-tegra/board-cardhu-power.c
arch/arm/mach-tegra/board-enterprise-power.c
arch/arm/mach-tegra/board-kai-power.c

index 4f96c5c..e76cbc4 100644 (file)
@@ -1134,15 +1134,25 @@ static struct tegra_suspend_platform_data cardhu_suspend_data = {
        .cpu_lp2_min_residency = 2000,
        .board_suspend = cardhu_board_suspend,
        .board_resume = cardhu_board_resume,
+#ifdef CONFIG_TEGRA_LP1_950
+       .lp1_lowvolt_support = false,
+       .i2c_base_addr = 0,
+       .pmuslave_addr = 0,
+       .core_reg_addr = 0,
+       .lp1_core_volt_low = 0,
+       .lp1_core_volt_high = 0,
+#endif
 };
 
 int __init cardhu_suspend_init(void)
 {
        struct board_info board_info;
        struct board_info pmu_board_info;
+       struct board_info display_board_info;
 
        tegra_get_board_info(&board_info);
        tegra_get_pmu_board_info(&pmu_board_info);
+       tegra_get_display_board_info(&display_board_info);
 
        /* For PMU Fab A03, A04 and A05 make core_pwr_req to high */
        if ((pmu_board_info.fab == BOARD_FAB_A03) ||
@@ -1170,6 +1180,17 @@ int __init cardhu_suspend_init(void)
                        tegra_disable_wake_source(TEGRA_WAKE_USB1_VBUS);
                break;
        case BOARD_PM269:
+#ifdef CONFIG_TEGRA_LP1_950
+               /* AP37 board supports the LP1_950mV feature */
+               if (is_display_board_dsi(display_board_info.board_id)) {
+                       cardhu_suspend_data.lp1_lowvolt_support = true;
+                       cardhu_suspend_data.i2c_base_addr = TEGRA_I2C5_BASE;
+                       cardhu_suspend_data.pmuslave_addr = 0xC0;
+                       cardhu_suspend_data.core_reg_addr = 0x03;
+                       cardhu_suspend_data.lp1_core_volt_low = 0x2D;
+                       cardhu_suspend_data.lp1_core_volt_high = 0x50;
+               }
+#endif
        case BOARD_PM305:
        case BOARD_PM311:
                break;
index 7ea2095..b7fd365 100644 (file)
@@ -779,6 +779,14 @@ static struct tegra_suspend_platform_data enterprise_suspend_data = {
        .sysclkreq_high = true,
        .board_suspend = enterprise_board_suspend,
        .board_resume = enterprise_board_resume,
+#ifdef CONFIG_TEGRA_LP1_950
+       .lp1_lowvolt_support = true,
+       .i2c_base_addr = TEGRA_I2C5_BASE,
+       .pmuslave_addr = 0x24,
+       .core_reg_addr = 0x5B,
+       .lp1_core_volt_low = 0x1D,
+       .lp1_core_volt_high = 0x33,
+#endif
 };
 
 static void enterprise_init_deep_sleep_mode(void)
index 6c66f1d..027d974 100644 (file)
@@ -614,6 +614,14 @@ static struct tegra_suspend_platform_data kai_suspend_data = {
        .cpu_lp2_min_residency = 2000,
        .board_suspend = kai_board_suspend,
        .board_resume = kai_board_resume,
+#ifdef CONFIG_TEGRA_LP1_950
+       .lp1_lowvolt_support = true,
+       .i2c_base_addr = TEGRA_I2C5_BASE,
+       .pmuslave_addr = 0x78,
+       .core_reg_addr = 0x17,
+       .lp1_core_volt_low = 0x0C,
+       .lp1_core_volt_high = 0x20,
+#endif
 };
 
 int __init kai_suspend_init(void)