asoc: codecs: Add ALC5640 audio codec.
Manoj Gangwal [Tue, 20 Dec 2011 14:58:46 +0000 (19:58 +0530)]
Changes made to add support of ALC5640 codec
for cardhu and support wm8903 codec also without
need for code recompilation.

Bug 910788

Change-Id: Iace74293a44c38eaae516552f03d8bfa6bfe936f
Signed-off-by: Manoj Gangwal <mgangwal@nvidia.com>
Reviewed-on: http://git-master/r/71455
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Re6463a1f9f9eb686049e830efd5ff2a75298bf2c

sound/soc/codecs/Kconfig
sound/soc/codecs/Makefile
sound/soc/codecs/rt5640.c [new file with mode: 0644]
sound/soc/codecs/rt5640.h [new file with mode: 0644]

index 7a8e6fc..145c289 100644 (file)
@@ -43,6 +43,7 @@ config SND_SOC_ALL_CODECS
        select SND_SOC_MAX9877 if I2C
        select SND_SOC_PCM3008
        select SND_SOC_RT5631 if I2C
+       select SND_SOC_RT5640 if I2C
        select SND_SOC_SGTL5000 if I2C
        select SND_SOC_SN95031 if INTEL_SCU_IPC
        select SND_SOC_SPDIF
@@ -231,6 +232,9 @@ config SND_SOC_PCM3008
 config SND_SOC_RT5631
        tristate
 
+config SND_SOC_RT5640
+       tristate
+
 #Freescale sgtl5000 codec
 config SND_SOC_SGTL5000
        tristate
index 6744a30..96db708 100644 (file)
@@ -97,6 +97,7 @@ snd-soc-wm9705-objs := wm9705.o
 snd-soc-wm9712-objs := wm9712.o
 snd-soc-wm9713-objs := wm9713.o
 snd-soc-wm-hubs-objs := wm_hubs.o
+snd-soc-rt5640-objs := rt5640.o
 
 # Amp
 snd-soc-max9877-objs := max9877.o
@@ -200,6 +201,7 @@ obj-$(CONFIG_SND_SOC_WM9705)        += snd-soc-wm9705.o
 obj-$(CONFIG_SND_SOC_WM9712)   += snd-soc-wm9712.o
 obj-$(CONFIG_SND_SOC_WM9713)   += snd-soc-wm9713.o
 obj-$(CONFIG_SND_SOC_WM_HUBS)  += snd-soc-wm-hubs.o
+obj-$(CONFIG_SND_SOC_RT5640)   += snd-soc-rt5640.o
 
 # Amp
 obj-$(CONFIG_SND_SOC_MAX9877)  += snd-soc-max9877.o
diff --git a/sound/soc/codecs/rt5640.c b/sound/soc/codecs/rt5640.c
new file mode 100644 (file)
index 0000000..c6f0ad0
--- /dev/null
@@ -0,0 +1,2509 @@
+/*
+ * rt5640.c  --  RT5640 ALSA SoC audio codec driver
+ *
+ * Copyright 2011 Realtek Semiconductor Corp.
+ * Author: Johnny Hsu <johnnyhsu@realtek.com>
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+
+#include "rt5640.h"
+#if (CONFIG_SND_SOC_RT5642_MODULE | CONFIG_SND_SOC_RT5642)
+#include "rt5640-dsp.h"
+#endif
+
+#define RT5640_DEMO 1
+#define RT5640_REG_RW 1
+#define RT5640_DET_EXT_MIC 0
+
+#ifdef RT5640_DEMO
+struct rt5640_init_reg {
+       u8 reg;
+       u16 val;
+};
+
+static struct rt5640_init_reg init_list[] = {
+       {RT5640_DUMMY1          , 0x3701},/*fa[12:13] = 1'b;fa[8~10]=1;fa[0]=1*/
+       {RT5640_DEPOP_M1        , 0x0019},/* 8e[4:3] = 11'b; 8e[0] = 1'b */
+       {RT5640_DEPOP_M2        , 0x3100},/* 8f[13] = 1'b */
+       {RT5640_ADDA_CLK1       , 0x1114},/* 73[2] = 1'b  */
+       {RT5640_MICBIAS         , 0x3030},/* 93[5:4] = 11'b */
+       {RT5640_PRIV_INDEX      , 0x003d},/* PR3d[12] = 1'b */
+       {RT5640_PRIV_DATA       , 0x3600},
+       {RT5640_CLS_D_OUT       , 0xa000},/* 8d[11] = 0'b */
+       {RT5640_PRIV_INDEX      , 0x001c},/* PR1c = 0D21'h */
+       {RT5640_PRIV_DATA       , 0x0D21},
+       {RT5640_PRIV_INDEX      , 0x001b},/* PR1B = 0D21'h */
+       {RT5640_PRIV_DATA       , 0x0000},
+       {RT5640_PRIV_INDEX      , 0x0012},/* PR12 = 0aa8'h */
+       {RT5640_PRIV_DATA       , 0x0aa8},
+       {RT5640_PRIV_INDEX      , 0x0014},/* PR14 = 0aaa'h */
+       {RT5640_PRIV_DATA       , 0x0aaa},
+       {RT5640_PRIV_INDEX      , 0x0020},/* PR20 = 6110'h */
+       {RT5640_PRIV_DATA       , 0x6110},
+       {RT5640_PRIV_INDEX      , 0x0021},/* PR21 = e0e0'h */
+       {RT5640_PRIV_DATA       , 0xe0e0},
+       {RT5640_PRIV_INDEX      , 0x0023},/* PR23 = 1804'h */
+       {RT5640_PRIV_DATA       , 0x1804},
+       /*playback*/
+       {RT5640_STO_DAC_MIXER   , 0x1414},/*Dig inf 1 -> Sto DAC mixer -> DACL*/
+       {RT5640_OUT_L3_MIXER    , 0x01fe},/*DACL1 -> OUTMIXL*/
+       {RT5640_OUT_R3_MIXER    , 0x01fe},/*DACR1 -> OUTMIXR */
+       {RT5640_HP_VOL          , 0x8888},/* OUTMIX -> HPVOL */
+       {RT5640_HPO_MIXER       , 0xc000},/* HPVOL -> HPOLMIX */
+/*     {RT5640_HPO_MIXER       , 0xa000},// DAC1 -> HPOLMIX   */
+       {RT5640_SPK_L_MIXER     , 0x0036},/* DACL1 -> SPKMIXL */
+       {RT5640_SPK_R_MIXER     , 0x0036},/* DACR1 -> SPKMIXR */
+       {RT5640_SPK_VOL         , 0x8888},/* SPKMIX -> SPKVOL */
+       {RT5640_SPO_L_MIXER     , 0xe800},/* SPKVOLL -> SPOLMIX */
+       {RT5640_SPO_R_MIXER     , 0x2800},/* SPKVOLR -> SPORMIX */
+/*     {RT5640_SPO_L_MIXER     , 0xb800},//DAC -> SPOLMIX */
+/*     {RT5640_SPO_R_MIXER     , 0x1800},//DAC -> SPORMIX */
+       {RT5640_I2S1_SDP        , 0xD000},/*change IIS1 and IIS2 */
+       /*record*/
+       {RT5640_IN1_IN2         , 0x5080},/*IN1 boost 40db & differential mode*/
+       {RT5640_IN3_IN4         , 0x0500},/*IN2 boost 40db & signal ended mode*/
+       {RT5640_REC_L2_MIXER    , 0x005f},/* enable Mic1 -> RECMIXL */
+       {RT5640_REC_R2_MIXER    , 0x005f},/* enable Mic1 -> RECMIXR */
+/*     {RT5640_REC_L2_MIXER    , 0x006f},//Mic2 -> RECMIXL */
+/*     {RT5640_REC_R2_MIXER    , 0x006f},//Mic2 -> RECMIXR */
+       {RT5640_STO_ADC_MIXER   , 0x3020},/* ADC -> Sto ADC mixer */
+
+#if RT5640_DET_EXT_MIC
+       {RT5640_MICBIAS , 0x3800},/* enable MICBIAS short current */
+       {RT5640_GPIO_CTRL1      , 0x8400},/* set GPIO1 to IRQ */
+       {RT5640_GPIO_CTRL3      , 0x0004},/* set GPIO1 output */
+       {RT5640_IRQ_CTRL2       , 0x8000},/*set MICBIAS short current to IRQ */
+                                       /*( if sticky set regBE : 8800 ) */
+#endif
+
+};
+#define RT5640_INIT_REG_LEN ARRAY_SIZE(init_list)
+
+static int rt5640_reg_init(struct snd_soc_codec *codec)
+{
+       int i;
+       for (i = 0; i < RT5640_INIT_REG_LEN; i++)
+               snd_soc_write(codec, init_list[i].reg, init_list[i].val);
+       return 0;
+}
+#endif
+
+static const u16 rt5640_reg[RT5640_VENDOR_ID2 + 1] = {
+       [RT5640_RESET] = 0x000c,
+       [RT5640_SPK_VOL] = 0xc8c8,
+       [RT5640_HP_VOL] = 0xc8c8,
+       [RT5640_OUTPUT] = 0xc8c8,
+       [RT5640_MONO_OUT] = 0x8000,
+       [RT5640_INL_INR_VOL] = 0x0808,
+       [RT5640_DAC1_DIG_VOL] = 0xafaf,
+       [RT5640_DAC2_DIG_VOL] = 0xafaf,
+       [RT5640_ADC_DIG_VOL] = 0x2f2f,
+       [RT5640_ADC_DATA] = 0x2f2f,
+       [RT5640_STO_ADC_MIXER] = 0x7060,
+       [RT5640_MONO_ADC_MIXER] = 0x7070,
+       [RT5640_AD_DA_MIXER] = 0x8080,
+       [RT5640_STO_DAC_MIXER] = 0x5454,
+       [RT5640_MONO_DAC_MIXER] = 0x5454,
+       [RT5640_DIG_MIXER] = 0xaa00,
+       [RT5640_DSP_PATH2] = 0xa000,
+       [RT5640_REC_L2_MIXER] = 0x007f,
+       [RT5640_REC_R2_MIXER] = 0x007f,
+       [RT5640_HPO_MIXER] = 0xe000,
+       [RT5640_SPK_L_MIXER] = 0x003e,
+       [RT5640_SPK_R_MIXER] = 0x003e,
+       [RT5640_SPO_L_MIXER] = 0xf800,
+       [RT5640_SPO_R_MIXER] = 0x3800,
+       [RT5640_SPO_CLSD_RATIO] = 0x0004,
+       [RT5640_MONO_MIXER] = 0xfc00,
+       [RT5640_OUT_L3_MIXER] = 0x01ff,
+       [RT5640_OUT_R3_MIXER] = 0x01ff,
+       [RT5640_LOUT_MIXER] = 0xf000,
+       [RT5640_PWR_ANLG1] = 0x00c0,
+       [RT5640_I2S1_SDP] = 0x8000,
+       [RT5640_I2S2_SDP] = 0x8000,
+       [RT5640_I2S3_SDP] = 0x8000,
+       [RT5640_ADDA_CLK1] = 0x1110,
+       [RT5640_ADDA_CLK2] = 0x0c00,
+       [RT5640_DMIC] = 0x1d00,
+       [RT5640_ASRC_3] = 0x0008,
+       [RT5640_HP_OVCD] = 0x0600,
+       [RT5640_CLS_D_OVCD] = 0x0228,
+       [RT5640_CLS_D_OUT] = 0xa800,
+       [RT5640_DEPOP_M1] = 0x0004,
+       [RT5640_DEPOP_M2] = 0x1100,
+       [RT5640_DEPOP_M3] = 0x0646,
+       [RT5640_CHARGE_PUMP] = 0x0c00,
+       [RT5640_MICBIAS] = 0x3000,
+       [RT5640_EQ_CTRL1] = 0x2080,
+       [RT5640_DRC_AGC_1] = 0x2206,
+       [RT5640_DRC_AGC_2] = 0x1f00,
+       [RT5640_ANC_CTRL1] = 0x034b,
+       [RT5640_ANC_CTRL2] = 0x0066,
+       [RT5640_ANC_CTRL3] = 0x000b,
+       [RT5640_GPIO_CTRL1] = 0x0400,
+       [RT5640_DSP_CTRL3] = 0x2000,
+       [RT5640_BASE_BACK] = 0x0013,
+       [RT5640_MP3_PLUS1] = 0x0680,
+       [RT5640_MP3_PLUS2] = 0x1c17,
+       [RT5640_3D_HP] = 0x8c00,
+       [RT5640_ADJ_HPF] = 0x2a20,
+       [RT5640_HP_CALIB_AMP_DET] = 0x0400,
+       [RT5640_SV_ZCD1] = 0x0809,
+       [RT5640_VENDOR_ID1] = 0x10ec,
+       [RT5640_VENDOR_ID2] = 0x6231,
+};
+
+static int rt5640_reset(struct snd_soc_codec *codec)
+{
+       return snd_soc_write(codec, RT5640_RESET, 0);
+}
+
+/**
+ * rt5640_index_write - Write private register.
+ * @codec: SoC audio codec device.
+ * @reg: Private register index.
+ * @value: Private register Data.
+ *
+ * Modify private register for advanced setting. It can be written through
+ * private index (0x6a) and data (0x6c) register.
+ *
+ * Returns 0 for success or negative error code.
+ */
+static int rt5640_index_write(struct snd_soc_codec *codec,
+               unsigned int reg, unsigned int value)
+{
+       int ret;
+
+       ret = snd_soc_write(codec, RT5640_PRIV_INDEX, reg);
+       if (ret < 0) {
+               dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
+               goto err;
+       }
+       ret = snd_soc_write(codec, RT5640_PRIV_DATA, value);
+       if (ret < 0) {
+               dev_err(codec->dev, "Failed to set private value: %d\n", ret);
+               goto err;
+       }
+       return 0;
+
+err:
+       return ret;
+}
+
+/**
+ * rt5640_index_read - Read private register.
+ * @codec: SoC audio codec device.
+ * @reg: Private register index.
+ *
+ * Read advanced setting from private register. It can be read through
+ * private index (0x6a) and data (0x6c) register.
+ *
+ * Returns private register value or negative error code.
+ */
+static unsigned int rt5640_index_read(
+       struct snd_soc_codec *codec, unsigned int reg)
+{
+       int ret;
+
+       ret = snd_soc_write(codec, RT5640_PRIV_INDEX, reg);
+       if (ret < 0) {
+               dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
+               return ret;
+       }
+       return snd_soc_read(codec, RT5640_PRIV_DATA);
+}
+
+/**
+ * rt5640_index_update_bits - update private register bits
+ * @codec: audio codec
+ * @reg: Private register index.
+ * @mask: register mask
+ * @value: new value
+ *
+ * Writes new register value.
+ *
+ * Returns 1 for change, 0 for no change, or negative error code.
+ */
+static int rt5640_index_update_bits(struct snd_soc_codec *codec,
+       unsigned int reg, unsigned int mask, unsigned int value)
+{
+       unsigned int old, new;
+       int change, ret;
+
+       ret = rt5640_index_read(codec, reg);
+       if (ret < 0) {
+               dev_err(codec->dev, "Failed to read private reg: %d\n", ret);
+               goto err;
+       }
+
+       old = ret;
+       new = (old & ~mask) | (value & mask);
+       change = old != new;
+       if (change) {
+               ret = rt5640_index_write(codec, reg, new);
+               if (ret < 0) {
+                       dev_err(codec->dev,
+                               "Failed to write private reg: %d\n", ret);
+                       goto err;
+               }
+       }
+       return change;
+
+err:
+       return ret;
+}
+
+static int rt5640_volatile_register(
+       struct snd_soc_codec *codec, unsigned int reg)
+{
+       switch (reg) {
+       case RT5640_RESET:
+       case RT5640_PRIV_DATA:
+       case RT5640_ASRC_5:
+       case RT5640_EQ_CTRL1:
+       case RT5640_DRC_AGC_1:
+       case RT5640_ANC_CTRL1:
+       case RT5640_IRQ_CTRL2:
+       case RT5640_INT_IRQ_ST:
+       case RT5640_DSP_CTRL2:
+       case RT5640_DSP_CTRL3:
+       case RT5640_PGM_REG_ARR1:
+       case RT5640_PGM_REG_ARR3:
+               return 1;
+       default:
+               return 0;
+       }
+}
+
+static int rt5640_readable_register(
+       struct snd_soc_codec *codec, unsigned int reg)
+{
+       switch (reg) {
+       case RT5640_RESET:
+       case RT5640_SPK_VOL:
+       case RT5640_HP_VOL:
+       case RT5640_OUTPUT:
+       case RT5640_MONO_OUT:
+       case RT5640_IN1_IN2:
+       case RT5640_IN3_IN4:
+       case RT5640_INL_INR_VOL:
+       case RT5640_DAC1_DIG_VOL:
+       case RT5640_DAC2_DIG_VOL:
+       case RT5640_DAC2_CTRL:
+       case RT5640_ADC_DIG_VOL:
+       case RT5640_ADC_DATA:
+       case RT5640_ADC_BST_VOL:
+       case RT5640_STO_ADC_MIXER:
+       case RT5640_MONO_ADC_MIXER:
+       case RT5640_AD_DA_MIXER:
+       case RT5640_STO_DAC_MIXER:
+       case RT5640_MONO_DAC_MIXER:
+       case RT5640_DIG_MIXER:
+       case RT5640_DSP_PATH1:
+       case RT5640_DSP_PATH2:
+       case RT5640_DIG_INF_DATA:
+       case RT5640_REC_L1_MIXER:
+       case RT5640_REC_L2_MIXER:
+       case RT5640_REC_R1_MIXER:
+       case RT5640_REC_R2_MIXER:
+       case RT5640_HPO_MIXER:
+       case RT5640_SPK_L_MIXER:
+       case RT5640_SPK_R_MIXER:
+       case RT5640_SPO_L_MIXER:
+       case RT5640_SPO_R_MIXER:
+       case RT5640_SPO_CLSD_RATIO:
+       case RT5640_MONO_MIXER:
+       case RT5640_OUT_L1_MIXER:
+       case RT5640_OUT_L2_MIXER:
+       case RT5640_OUT_L3_MIXER:
+       case RT5640_OUT_R1_MIXER:
+       case RT5640_OUT_R2_MIXER:
+       case RT5640_OUT_R3_MIXER:
+       case RT5640_LOUT_MIXER:
+       case RT5640_PWR_DIG1:
+       case RT5640_PWR_DIG2:
+       case RT5640_PWR_ANLG1:
+       case RT5640_PWR_ANLG2:
+       case RT5640_PWR_MIXER:
+       case RT5640_PWR_VOL:
+       case RT5640_PRIV_INDEX:
+       case RT5640_PRIV_DATA:
+       case RT5640_I2S1_SDP:
+       case RT5640_I2S2_SDP:
+       case RT5640_I2S3_SDP:
+       case RT5640_ADDA_CLK1:
+       case RT5640_ADDA_CLK2:
+       case RT5640_DMIC:
+       case RT5640_GLB_CLK:
+       case RT5640_PLL_CTRL1:
+       case RT5640_PLL_CTRL2:
+       case RT5640_ASRC_1:
+       case RT5640_ASRC_2:
+       case RT5640_ASRC_3:
+       case RT5640_ASRC_4:
+       case RT5640_ASRC_5:
+       case RT5640_HP_OVCD:
+       case RT5640_CLS_D_OVCD:
+       case RT5640_CLS_D_OUT:
+       case RT5640_DEPOP_M1:
+       case RT5640_DEPOP_M2:
+       case RT5640_DEPOP_M3:
+       case RT5640_CHARGE_PUMP:
+       case RT5640_PV_DET_SPK_G:
+       case RT5640_MICBIAS:
+       case RT5640_EQ_CTRL1:
+       case RT5640_EQ_CTRL2:
+       case RT5640_WIND_FILTER:
+       case RT5640_DRC_AGC_1:
+       case RT5640_DRC_AGC_2:
+       case RT5640_DRC_AGC_3:
+       case RT5640_SVOL_ZC:
+       case RT5640_ANC_CTRL1:
+       case RT5640_ANC_CTRL2:
+       case RT5640_ANC_CTRL3:
+       case RT5640_JD_CTRL:
+       case RT5640_ANC_JD:
+       case RT5640_IRQ_CTRL1:
+       case RT5640_IRQ_CTRL2:
+       case RT5640_INT_IRQ_ST:
+       case RT5640_GPIO_CTRL1:
+       case RT5640_GPIO_CTRL2:
+       case RT5640_GPIO_CTRL3:
+       case RT5640_DSP_CTRL1:
+       case RT5640_DSP_CTRL2:
+       case RT5640_DSP_CTRL3:
+       case RT5640_DSP_CTRL4:
+       case RT5640_PGM_REG_ARR1:
+       case RT5640_PGM_REG_ARR2:
+       case RT5640_PGM_REG_ARR3:
+       case RT5640_PGM_REG_ARR4:
+       case RT5640_PGM_REG_ARR5:
+       case RT5640_SCB_FUNC:
+       case RT5640_SCB_CTRL:
+       case RT5640_BASE_BACK:
+       case RT5640_MP3_PLUS1:
+       case RT5640_MP3_PLUS2:
+       case RT5640_3D_HP:
+       case RT5640_ADJ_HPF:
+       case RT5640_HP_CALIB_AMP_DET:
+       case RT5640_HP_CALIB2:
+       case RT5640_SV_ZCD1:
+       case RT5640_SV_ZCD2:
+       case RT5640_DUMMY1:
+       case RT5640_DUMMY2:
+       case RT5640_DUMMY3:
+       case RT5640_VENDOR_ID:
+       case RT5640_VENDOR_ID1:
+       case RT5640_VENDOR_ID2:
+               return 1;
+       default:
+               return 0;
+       }
+}
+
+static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
+static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
+static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
+static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
+static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
+
+/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
+static unsigned int bst_tlv[] = {
+       TLV_DB_RANGE_HEAD(7),
+       0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
+       1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
+       2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
+       3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
+       6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
+       7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
+       8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
+};
+
+static int rt5640_dmic_get(struct snd_kcontrol *kcontrol,
+               struct snd_ctl_elem_value *ucontrol)
+{
+       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+       struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+
+       ucontrol->value.integer.value[0] = rt5640->dmic_en;
+
+       return 0;
+}
+
+static int rt5640_dmic_put(struct snd_kcontrol *kcontrol,
+               struct snd_ctl_elem_value *ucontrol)
+{
+       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+       struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+
+       if (rt5640->dmic_en == ucontrol->value.integer.value[0])
+               return 0;
+
+       rt5640->dmic_en = ucontrol->value.integer.value[0];
+       switch (rt5640->dmic_en) {
+       case RT5640_DMIC_DIS:
+               snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
+                       RT5640_GP2_PIN_MASK | RT5640_GP3_PIN_MASK |
+                       RT5640_GP4_PIN_MASK,
+                       RT5640_GP2_PIN_GPIO2 | RT5640_GP3_PIN_GPIO3 |
+                       RT5640_GP4_PIN_GPIO4);
+               snd_soc_update_bits(codec, RT5640_DMIC,
+                       RT5640_DMIC_1_DP_MASK | RT5640_DMIC_2_DP_MASK,
+                       RT5640_DMIC_1_DP_GPIO3 | RT5640_DMIC_2_DP_GPIO4);
+               snd_soc_update_bits(codec, RT5640_DMIC,
+                       RT5640_DMIC_1_EN_MASK | RT5640_DMIC_2_EN_MASK,
+                       RT5640_DMIC_1_DIS | RT5640_DMIC_2_DIS);
+               break;
+
+       case RT5640_DMIC1:
+               snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
+                       RT5640_GP2_PIN_MASK | RT5640_GP3_PIN_MASK,
+                       RT5640_GP2_PIN_DMIC1_SCL | RT5640_GP3_PIN_DMIC1_SDA);
+               snd_soc_update_bits(codec, RT5640_DMIC,
+                       RT5640_DMIC_1L_LH_MASK | RT5640_DMIC_1R_LH_MASK |
+                       RT5640_DMIC_1_DP_MASK,
+                       RT5640_DMIC_1L_LH_FALLING | RT5640_DMIC_1R_LH_RISING |
+                       RT5640_DMIC_1_DP_IN1P);
+               snd_soc_update_bits(codec, RT5640_DMIC,
+                       RT5640_DMIC_1_EN_MASK, RT5640_DMIC_1_EN);
+               break;
+
+       case RT5640_DMIC2:
+               snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
+                       RT5640_GP2_PIN_MASK | RT5640_GP4_PIN_MASK,
+                       RT5640_GP2_PIN_DMIC1_SCL | RT5640_GP4_PIN_DMIC2_SDA);
+               snd_soc_update_bits(codec, RT5640_DMIC,
+                       RT5640_DMIC_2L_LH_MASK | RT5640_DMIC_2R_LH_MASK |
+                       RT5640_DMIC_2_DP_MASK,
+                       RT5640_DMIC_2L_LH_FALLING | RT5640_DMIC_2R_LH_RISING |
+                       RT5640_DMIC_2_DP_IN1N);
+               snd_soc_update_bits(codec, RT5640_DMIC,
+                       RT5640_DMIC_2_EN_MASK, RT5640_DMIC_2_EN);
+               break;
+
+       default:
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+
+/* IN1/IN2 Input Type */
+static const char *rt5640_input_mode[] = {
+       "Single ended", "Differential"};
+
+static const SOC_ENUM_SINGLE_DECL(
+       rt5640_in1_mode_enum, RT5640_IN1_IN2,
+       RT5640_IN_SFT1, rt5640_input_mode);
+
+static const SOC_ENUM_SINGLE_DECL(
+       rt5640_in2_mode_enum, RT5640_IN3_IN4,
+       RT5640_IN_SFT2, rt5640_input_mode);
+
+/* Interface data select */
+static const char *rt5640_data_select[] = {
+       "Normal", "left copy to right", "right copy to left", "Swap"};
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_if1_dac_enum, RT5640_DIG_INF_DATA,
+                               RT5640_IF1_DAC_SEL_SFT, rt5640_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_if1_adc_enum, RT5640_DIG_INF_DATA,
+                               RT5640_IF1_ADC_SEL_SFT, rt5640_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_if2_dac_enum, RT5640_DIG_INF_DATA,
+                               RT5640_IF2_DAC_SEL_SFT, rt5640_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_if2_adc_enum, RT5640_DIG_INF_DATA,
+                               RT5640_IF2_ADC_SEL_SFT, rt5640_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_if3_dac_enum, RT5640_DIG_INF_DATA,
+                               RT5640_IF3_DAC_SEL_SFT, rt5640_data_select);
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_if3_adc_enum, RT5640_DIG_INF_DATA,
+                               RT5640_IF3_ADC_SEL_SFT, rt5640_data_select);
+
+/* Class D speaker gain ratio */
+static const char *rt5640_clsd_spk_ratio[] = {"1.66x", "1.83x", "1.94x", "2x",
+       "2.11x", "2.22x", "2.33x", "2.44x", "2.55x", "2.66x", "2.77x"};
+
+static const SOC_ENUM_SINGLE_DECL(
+       rt5640_clsd_spk_ratio_enum, RT5640_CLS_D_OUT,
+       RT5640_CLSD_RATIO_SFT, rt5640_clsd_spk_ratio);
+
+/* DMIC */
+static const char *rt5640_dmic_mode[] = {"Disable", "DMIC1", "DMIC2"};
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_dmic_enum, 0, 0, rt5640_dmic_mode);
+
+
+
+#ifdef RT5640_REG_RW
+#define REGVAL_MAX 0xffff
+static unsigned int regctl_addr;
+static int rt5640_regctl_info(struct snd_kcontrol *kcontrol,
+                       struct snd_ctl_elem_info *uinfo) {
+       uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+       uinfo->count = 2;
+       uinfo->value.integer.min = 0;
+       uinfo->value.integer.max = REGVAL_MAX;
+       return 0;
+}
+
+static int rt5640_regctl_get(struct snd_kcontrol *kcontrol,
+                       struct snd_ctl_elem_value *ucontrol)
+{
+       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+       ucontrol->value.integer.value[0] = regctl_addr;
+       ucontrol->value.integer.value[1] = snd_soc_read(codec, regctl_addr);
+       return 0;
+}
+
+static int rt5640_regctl_put(struct snd_kcontrol *kcontrol,
+                       struct snd_ctl_elem_value *ucontrol)
+{
+       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+       regctl_addr = ucontrol->value.integer.value[0];
+       if (ucontrol->value.integer.value[1] <= REGVAL_MAX)
+               snd_soc_write(codec, regctl_addr,
+               ucontrol->value.integer.value[1]);
+       return 0;
+}
+#endif
+
+
+#define VOL_RESCALE_MAX_VOL 0x27 /* 39 */
+#define VOL_RESCALE_MIX_RANGE 0x1F /* 31 */
+
+static int rt5640_vol_rescale_get(struct snd_kcontrol *kcontrol,
+               struct snd_ctl_elem_value *ucontrol)
+{
+       struct soc_mixer_control *mc =
+               (struct soc_mixer_control *)kcontrol->private_value;
+       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+       unsigned int val = snd_soc_read(codec, mc->reg);
+
+       ucontrol->value.integer.value[0] = VOL_RESCALE_MAX_VOL -
+               ((val & RT5640_L_VOL_MASK) >> mc->shift);
+       ucontrol->value.integer.value[1] = VOL_RESCALE_MAX_VOL -
+               (val & RT5640_R_VOL_MASK);
+
+       return 0;
+}
+
+static int rt5640_vol_rescale_put(struct snd_kcontrol *kcontrol,
+               struct snd_ctl_elem_value *ucontrol)
+{
+       struct soc_mixer_control *mc =
+               (struct soc_mixer_control *)kcontrol->private_value;
+       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+       unsigned int val, val2;
+
+       val = VOL_RESCALE_MAX_VOL - ucontrol->value.integer.value[0];
+       val2 = VOL_RESCALE_MAX_VOL - ucontrol->value.integer.value[1];
+       return snd_soc_update_bits_locked(codec, mc->reg, RT5640_L_VOL_MASK |
+                       RT5640_R_VOL_MASK, val << mc->shift | val2);
+}
+
+
+static const struct snd_kcontrol_new rt5640_snd_controls[] = {
+       /* Speaker Output Volume */
+       SOC_DOUBLE("Speaker Playback Switch", RT5640_SPK_VOL,
+               RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
+
+       SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5640_SPK_VOL,
+               RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, VOL_RESCALE_MIX_RANGE, 0,
+               rt5640_vol_rescale_get, rt5640_vol_rescale_put, out_vol_tlv),
+
+       /* Headphone Output Volume */
+       SOC_DOUBLE("HP Playback Switch", RT5640_HP_VOL,
+               RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
+
+       SOC_DOUBLE_EXT_TLV("HP Playback Volume", RT5640_HP_VOL,
+               RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, VOL_RESCALE_MIX_RANGE, 0,
+               rt5640_vol_rescale_get, rt5640_vol_rescale_put, out_vol_tlv),
+
+       /* OUTPUT Control */
+       SOC_DOUBLE("OUT Playback Switch", RT5640_OUTPUT,
+               RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
+       SOC_DOUBLE("OUT Channel Switch", RT5640_OUTPUT,
+               RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1),
+       SOC_DOUBLE_TLV("OUT Playback Volume", RT5640_OUTPUT,
+               RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv),
+       /* MONO Output Control */
+       SOC_SINGLE("Mono Playback Switch", RT5640_MONO_OUT,
+                               RT5640_L_MUTE_SFT, 1, 1),
+       /* DAC Digital Volume */
+       SOC_DOUBLE("DAC2 Playback Switch", RT5640_DAC2_CTRL,
+               RT5640_M_DAC_L2_VOL_SFT, RT5640_M_DAC_R2_VOL_SFT, 1, 1),
+       SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5640_DAC1_DIG_VOL,
+                       RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
+                       175, 0, dac_vol_tlv),
+       SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5640_DAC2_DIG_VOL,
+                       RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
+                       175, 0, dac_vol_tlv),
+       /* IN1/IN2 Control */
+       SOC_ENUM("IN1 Mode Control",  rt5640_in1_mode_enum),
+       SOC_SINGLE_TLV("IN1 Boost", RT5640_IN1_IN2,
+               RT5640_BST_SFT1, 8, 0, bst_tlv),
+       SOC_ENUM("IN2 Mode Control", rt5640_in2_mode_enum),
+       SOC_SINGLE_TLV("IN2 Boost", RT5640_IN3_IN4,
+               RT5640_BST_SFT2, 8, 0, bst_tlv),
+       /* INL/INR Volume Control */
+       SOC_DOUBLE_TLV("IN Capture Volume", RT5640_INL_INR_VOL,
+                       RT5640_INL_VOL_SFT, RT5640_INR_VOL_SFT,
+                       31, 1, in_vol_tlv),
+       /* ADC Digital Volume Control */
+       SOC_DOUBLE("ADC Capture Switch", RT5640_ADC_DIG_VOL,
+               RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
+       SOC_DOUBLE_TLV("ADC Capture Volume", RT5640_ADC_DIG_VOL,
+                       RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
+                       127, 0, adc_vol_tlv),
+       SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5640_ADC_DATA,
+                       RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
+                       127, 0, adc_vol_tlv),
+       /* ADC Boost Volume Control */
+       SOC_DOUBLE_TLV("ADC Boost Gain", RT5640_ADC_BST_VOL,
+                       RT5640_ADC_L_BST_SFT, RT5640_ADC_R_BST_SFT,
+                       3, 0, adc_bst_tlv),
+       /* Class D speaker gain ratio */
+       SOC_ENUM("Class D SPK Ratio Control", rt5640_clsd_spk_ratio_enum),
+       /* DMIC */
+       SOC_ENUM_EXT("DMIC Switch", rt5640_dmic_enum,
+               rt5640_dmic_get, rt5640_dmic_put),
+
+#ifdef RT5640_REG_RW
+       {
+               .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+               .name = "Register Control",
+               .info = rt5640_regctl_info,
+               .get = rt5640_regctl_get,
+               .put = rt5640_regctl_put,
+       },
+#endif
+};
+
+/**
+ * set_dmic_clk - Set parameter of dmic.
+ *
+ * @w: DAPM widget.
+ * @kcontrol: The kcontrol of this widget.
+ * @event: Event id.
+ *
+ * Choose dmic clock between 1MHz and 3MHz.
+ * It is better for clock to approximate 3MHz.
+ */
+static int set_dmic_clk(struct snd_soc_dapm_widget *w,
+       struct snd_kcontrol *kcontrol, int event)
+{
+       struct snd_soc_codec *codec = w->codec;
+       struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+       int div[] = {2, 3, 4, 6, 12}, idx = -EINVAL, i, rate, red, bound, temp;
+
+       rate = rt5640->lrck[rt5640->aif_pu] << 8;
+       red = 3000000 * 12;
+       for (i = 0; i < ARRAY_SIZE(div); i++) {
+               bound = div[i] * 3000000;
+               if (rate > bound)
+                       continue;
+               temp = bound - rate;
+               if (temp < red) {
+                       red = temp;
+                       idx = i;
+               }
+       }
+       if (idx < 0)
+               dev_err(codec->dev, "Failed to set DMIC clock\n");
+       else
+               snd_soc_update_bits(codec, RT5640_DMIC, RT5640_DMIC_CLK_MASK,
+                                       idx << RT5640_DMIC_CLK_SFT);
+       return idx;
+}
+
+static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
+                        struct snd_soc_dapm_widget *sink)
+{
+       unsigned int val;
+
+       val = snd_soc_read(source->codec, RT5640_GLB_CLK);
+       val &= RT5640_SCLK_SRC_MASK;
+       if (val == RT5640_SCLK_SRC_PLL1 || val == RT5640_SCLK_SRC_PLL1T)
+               return 1;
+       else
+               return 0;
+}
+
+/* Digital Mixer */
+static const struct snd_kcontrol_new rt5640_sto_adc_l_mix[] = {
+       SOC_DAPM_SINGLE("ADC1 Switch", RT5640_STO_ADC_MIXER,
+                       RT5640_M_ADC_L1_SFT, 1, 1),
+       SOC_DAPM_SINGLE("ADC2 Switch", RT5640_STO_ADC_MIXER,
+                       RT5640_M_ADC_L2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_sto_adc_r_mix[] = {
+       SOC_DAPM_SINGLE("ADC1 Switch", RT5640_STO_ADC_MIXER,
+                       RT5640_M_ADC_R1_SFT, 1, 1),
+       SOC_DAPM_SINGLE("ADC2 Switch", RT5640_STO_ADC_MIXER,
+                       RT5640_M_ADC_R2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_mono_adc_l_mix[] = {
+       SOC_DAPM_SINGLE("ADC1 Switch", RT5640_MONO_ADC_MIXER,
+                       RT5640_M_MONO_ADC_L1_SFT, 1, 1),
+       SOC_DAPM_SINGLE("ADC2 Switch", RT5640_MONO_ADC_MIXER,
+                       RT5640_M_MONO_ADC_L2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_mono_adc_r_mix[] = {
+       SOC_DAPM_SINGLE("ADC1 Switch", RT5640_MONO_ADC_MIXER,
+                       RT5640_M_MONO_ADC_R1_SFT, 1, 1),
+       SOC_DAPM_SINGLE("ADC2 Switch", RT5640_MONO_ADC_MIXER,
+                       RT5640_M_MONO_ADC_R2_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_dac_l_mix[] = {
+       SOC_DAPM_SINGLE("Stereo ADC Switch", RT5640_AD_DA_MIXER,
+                       RT5640_M_ADCMIX_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("INF1 Switch", RT5640_AD_DA_MIXER,
+                       RT5640_M_IF1_DAC_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_dac_r_mix[] = {
+       SOC_DAPM_SINGLE("Stereo ADC Switch", RT5640_AD_DA_MIXER,
+                       RT5640_M_ADCMIX_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("INF1 Switch", RT5640_AD_DA_MIXER,
+                       RT5640_M_IF1_DAC_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_sto_dac_l_mix[] = {
+       SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_STO_DAC_MIXER,
+                       RT5640_M_DAC_L1_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_STO_DAC_MIXER,
+                       RT5640_M_DAC_L2_SFT, 1, 1),
+       SOC_DAPM_SINGLE("ANC Switch", RT5640_STO_DAC_MIXER,
+                       RT5640_M_ANC_DAC_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_sto_dac_r_mix[] = {
+       SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_STO_DAC_MIXER,
+                       RT5640_M_DAC_R1_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_STO_DAC_MIXER,
+                       RT5640_M_DAC_R2_SFT, 1, 1),
+       SOC_DAPM_SINGLE("ANC Switch", RT5640_STO_DAC_MIXER,
+                       RT5640_M_ANC_DAC_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_mono_dac_l_mix[] = {
+       SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_MONO_DAC_MIXER,
+                       RT5640_M_DAC_L1_MONO_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_DAC_MIXER,
+                       RT5640_M_DAC_L2_MONO_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_DAC_MIXER,
+                       RT5640_M_DAC_R2_MONO_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_mono_dac_r_mix[] = {
+       SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_MONO_DAC_MIXER,
+                       RT5640_M_DAC_R1_MONO_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_DAC_MIXER,
+                       RT5640_M_DAC_R2_MONO_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_DAC_MIXER,
+                       RT5640_M_DAC_L2_MONO_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_dig_l_mix[] = {
+       SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_DIG_MIXER,
+                       RT5640_M_STO_L_DAC_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_DIG_MIXER,
+                       RT5640_M_DAC_L2_DAC_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_dig_r_mix[] = {
+       SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_DIG_MIXER,
+                       RT5640_M_STO_R_DAC_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_DIG_MIXER,
+                       RT5640_M_DAC_R2_DAC_R_SFT, 1, 1),
+};
+
+/* Analog Input Mixer */
+static const struct snd_kcontrol_new rt5640_rec_l_mix[] = {
+       SOC_DAPM_SINGLE("HPOL Switch", RT5640_REC_L2_MIXER,
+                       RT5640_M_HP_L_RM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("INL Switch", RT5640_REC_L2_MIXER,
+                       RT5640_M_IN_L_RM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("BST2 Switch", RT5640_REC_L2_MIXER,
+                       RT5640_M_BST4_RM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("BST1 Switch", RT5640_REC_L2_MIXER,
+                       RT5640_M_BST1_RM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("OUT MIXL Switch", RT5640_REC_L2_MIXER,
+                       RT5640_M_OM_L_RM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_rec_r_mix[] = {
+       SOC_DAPM_SINGLE("HPOR Switch", RT5640_REC_R2_MIXER,
+                       RT5640_M_HP_R_RM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("INR Switch", RT5640_REC_R2_MIXER,
+                       RT5640_M_IN_R_RM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("BST2 Switch", RT5640_REC_R2_MIXER,
+                       RT5640_M_BST4_RM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("BST1 Switch", RT5640_REC_R2_MIXER,
+                       RT5640_M_BST1_RM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("OUT MIXR Switch", RT5640_REC_R2_MIXER,
+                       RT5640_M_OM_R_RM_R_SFT, 1, 1),
+};
+
+/* Analog Output Mixer */
+static const struct snd_kcontrol_new rt5640_spk_l_mix[] = {
+       SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_SPK_L_MIXER,
+                       RT5640_M_RM_L_SM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("INL Switch", RT5640_SPK_L_MIXER,
+                       RT5640_M_IN_L_SM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_SPK_L_MIXER,
+                       RT5640_M_DAC_L1_SM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_SPK_L_MIXER,
+                       RT5640_M_DAC_L2_SM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("OUT MIXL Switch", RT5640_SPK_L_MIXER,
+                       RT5640_M_OM_L_SM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_spk_r_mix[] = {
+       SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_SPK_R_MIXER,
+                       RT5640_M_RM_R_SM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("INR Switch", RT5640_SPK_R_MIXER,
+                       RT5640_M_IN_R_SM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPK_R_MIXER,
+                       RT5640_M_DAC_R1_SM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_SPK_R_MIXER,
+                       RT5640_M_DAC_R2_SM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("OUT MIXR Switch", RT5640_SPK_R_MIXER,
+                       RT5640_M_OM_R_SM_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_out_l_mix[] = {
+       SOC_DAPM_SINGLE("SPK MIXL Switch", RT5640_OUT_L3_MIXER,
+                       RT5640_M_SM_L_OM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_L3_MIXER,
+                       RT5640_M_BST1_OM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("INL Switch", RT5640_OUT_L3_MIXER,
+                       RT5640_M_IN_L_OM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_OUT_L3_MIXER,
+                       RT5640_M_RM_L_OM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_OUT_L3_MIXER,
+                       RT5640_M_DAC_R2_OM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_OUT_L3_MIXER,
+                       RT5640_M_DAC_L2_OM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_OUT_L3_MIXER,
+                       RT5640_M_DAC_L1_OM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_out_r_mix[] = {
+       SOC_DAPM_SINGLE("SPK MIXR Switch", RT5640_OUT_R3_MIXER,
+                       RT5640_M_SM_L_OM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("BST2 Switch", RT5640_OUT_R3_MIXER,
+                       RT5640_M_BST4_OM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_R3_MIXER,
+                       RT5640_M_BST1_OM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("INR Switch", RT5640_OUT_R3_MIXER,
+                       RT5640_M_IN_R_OM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_OUT_R3_MIXER,
+                       RT5640_M_RM_R_OM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_OUT_R3_MIXER,
+                       RT5640_M_DAC_L2_OM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_OUT_R3_MIXER,
+                       RT5640_M_DAC_R2_OM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_OUT_R3_MIXER,
+                       RT5640_M_DAC_R1_OM_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_spo_l_mix[] = {
+       SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_L_MIXER,
+                       RT5640_M_DAC_R1_SPM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_SPO_L_MIXER,
+                       RT5640_M_DAC_L1_SPM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("SPKVOL R Switch", RT5640_SPO_L_MIXER,
+                       RT5640_M_SV_R_SPM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("SPKVOL L Switch", RT5640_SPO_L_MIXER,
+                       RT5640_M_SV_L_SPM_L_SFT, 1, 1),
+       SOC_DAPM_SINGLE("BST1 Switch", RT5640_SPO_L_MIXER,
+                       RT5640_M_BST1_SPM_L_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_spo_r_mix[] = {
+       SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_R_MIXER,
+                       RT5640_M_DAC_R1_SPM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("SPKVOL R Switch", RT5640_SPO_R_MIXER,
+                       RT5640_M_SV_R_SPM_R_SFT, 1, 1),
+       SOC_DAPM_SINGLE("BST1 Switch", RT5640_SPO_R_MIXER,
+                       RT5640_M_BST1_SPM_R_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_hpo_mix[] = {
+       SOC_DAPM_SINGLE("DAC2 Switch", RT5640_HPO_MIXER,
+                       RT5640_M_DAC2_HM_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC1 Switch", RT5640_HPO_MIXER,
+                       RT5640_M_DAC1_HM_SFT, 1, 1),
+       SOC_DAPM_SINGLE("HPVOL Switch", RT5640_HPO_MIXER,
+                       RT5640_M_HPVOL_HM_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_lout_mix[] = {
+       SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_LOUT_MIXER,
+                       RT5640_M_DAC_L1_LM_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_LOUT_MIXER,
+                       RT5640_M_DAC_R1_LM_SFT, 1, 1),
+       SOC_DAPM_SINGLE("OUTVOL L Switch", RT5640_LOUT_MIXER,
+                       RT5640_M_OV_L_LM_SFT, 1, 1),
+       SOC_DAPM_SINGLE("OUTVOL R Switch", RT5640_LOUT_MIXER,
+                       RT5640_M_OV_R_LM_SFT, 1, 1),
+};
+
+static const struct snd_kcontrol_new rt5640_mono_mix[] = {
+       SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_MIXER,
+                       RT5640_M_DAC_R2_MM_SFT, 1, 1),
+       SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_MIXER,
+                       RT5640_M_DAC_L2_MM_SFT, 1, 1),
+       SOC_DAPM_SINGLE("OUTVOL R Switch", RT5640_MONO_MIXER,
+                       RT5640_M_OV_R_MM_SFT, 1, 1),
+       SOC_DAPM_SINGLE("OUTVOL L Switch", RT5640_MONO_MIXER,
+                       RT5640_M_OV_L_MM_SFT, 1, 1),
+       SOC_DAPM_SINGLE("BST1 Switch", RT5640_MONO_MIXER,
+                       RT5640_M_BST1_MM_SFT, 1, 1),
+};
+
+/* INL/R source */
+static const char *rt5640_inl_src[] = {"IN2P", "MonoP"};
+
+static const SOC_ENUM_SINGLE_DECL(
+       rt5640_inl_enum, RT5640_INL_INR_VOL,
+       RT5640_INL_SEL_SFT, rt5640_inl_src);
+
+static const struct snd_kcontrol_new rt5640_inl_mux =
+       SOC_DAPM_ENUM("INL source", rt5640_inl_enum);
+
+static const char *rt5640_inr_src[] = {"IN2N", "MonoN"};
+
+static const SOC_ENUM_SINGLE_DECL(
+       rt5640_inr_enum, RT5640_INL_INR_VOL,
+       RT5640_INR_SEL_SFT, rt5640_inr_src);
+
+static const struct snd_kcontrol_new rt5640_inr_mux =
+       SOC_DAPM_ENUM("INR source", rt5640_inr_enum);
+
+/* Stereo ADC source */
+static const char *rt5640_stereo_adc1_src[] = {"DIG MIX", "ADC"};
+
+static const SOC_ENUM_SINGLE_DECL(
+       rt5640_stereo_adc1_enum, RT5640_STO_ADC_MIXER,
+       RT5640_ADC_1_SRC_SFT, rt5640_stereo_adc1_src);
+
+static const struct snd_kcontrol_new rt5640_sto_adc_l1_mux =
+       SOC_DAPM_ENUM("Stereo ADC L1 source", rt5640_stereo_adc1_enum);
+
+static const struct snd_kcontrol_new rt5640_sto_adc_r1_mux =
+       SOC_DAPM_ENUM("Stereo ADC R1 source", rt5640_stereo_adc1_enum);
+
+static const char *rt5640_stereo_adc2_src[] = {"DMIC1", "DMIC2", "DIG MIX"};
+
+static const SOC_ENUM_SINGLE_DECL(
+       rt5640_stereo_adc2_enum, RT5640_STO_ADC_MIXER,
+       RT5640_ADC_2_SRC_SFT, rt5640_stereo_adc2_src);
+
+static const struct snd_kcontrol_new rt5640_sto_adc_l2_mux =
+       SOC_DAPM_ENUM("Stereo ADC L2 source", rt5640_stereo_adc2_enum);
+
+static const struct snd_kcontrol_new rt5640_sto_adc_r2_mux =
+       SOC_DAPM_ENUM("Stereo ADC R2 source", rt5640_stereo_adc2_enum);
+
+/* Mono ADC source */
+static const char *rt5640_mono_adc_l1_src[] = {"Mono DAC MIXL", "ADCL"};
+
+static const SOC_ENUM_SINGLE_DECL(
+       rt5640_mono_adc_l1_enum, RT5640_MONO_ADC_MIXER,
+       RT5640_MONO_ADC_L1_SRC_SFT, rt5640_mono_adc_l1_src);
+
+static const struct snd_kcontrol_new rt5640_mono_adc_l1_mux =
+       SOC_DAPM_ENUM("Mono ADC1 left source", rt5640_mono_adc_l1_enum);
+
+static const char *rt5640_mono_adc_l2_src[] = {
+       "DMIC L1", "DMIC L2", "Mono DAC MIXL"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+       rt5640_mono_adc_l2_enum, RT5640_MONO_ADC_MIXER,
+       RT5640_MONO_ADC_L2_SRC_SFT, rt5640_mono_adc_l2_src);
+
+static const struct snd_kcontrol_new rt5640_mono_adc_l2_mux =
+       SOC_DAPM_ENUM("Mono ADC2 left source", rt5640_mono_adc_l2_enum);
+
+static const char *rt5640_mono_adc_r1_src[] = {"Mono DAC MIXR", "ADCR"};
+
+static const SOC_ENUM_SINGLE_DECL(
+       rt5640_mono_adc_r1_enum, RT5640_MONO_ADC_MIXER,
+       RT5640_MONO_ADC_R1_SRC_SFT, rt5640_mono_adc_r1_src);
+
+static const struct snd_kcontrol_new rt5640_mono_adc_r1_mux =
+       SOC_DAPM_ENUM("Mono ADC1 right source", rt5640_mono_adc_r1_enum);
+
+static const char *rt5640_mono_adc_r2_src[] = {
+       "DMIC R1", "DMIC R2", "Mono DAC MIXR"
+};
+
+static const SOC_ENUM_SINGLE_DECL(
+       rt5640_mono_adc_r2_enum, RT5640_MONO_ADC_MIXER,
+       RT5640_MONO_ADC_R2_SRC_SFT, rt5640_mono_adc_r2_src);
+
+static const struct snd_kcontrol_new rt5640_mono_adc_r2_mux =
+       SOC_DAPM_ENUM("Mono ADC2 right source", rt5640_mono_adc_r2_enum);
+
+/* DAC2 channel source */
+static const char *rt5640_dac_l2_src[] = {"IF2", "IF3", "TxDC", "Base L/R"};
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_dac_l2_enum, RT5640_DSP_PATH2,
+                               RT5640_DAC_L2_SEL_SFT, rt5640_dac_l2_src);
+
+static const struct snd_kcontrol_new rt5640_dac_l2_mux =
+       SOC_DAPM_ENUM("DAC2 left channel source", rt5640_dac_l2_enum);
+
+static const char *rt5640_dac_r2_src[] = {"IF2", "IF3", "TxDC"};
+
+static const SOC_ENUM_SINGLE_DECL(
+       rt5640_dac_r2_enum, RT5640_DSP_PATH2,
+       RT5640_DAC_R2_SEL_SFT, rt5640_dac_r2_src);
+
+static const struct snd_kcontrol_new rt5640_dac_r2_mux =
+       SOC_DAPM_ENUM("DAC2 right channel source", rt5640_dac_r2_enum);
+
+/* Interface 2  ADC channel source */
+static const char *rt5640_if2_adc_l_src[] = {"TxDP", "Mono ADC MIXL"};
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_if2_adc_l_enum, RT5640_DSP_PATH2,
+                       RT5640_IF2_ADC_L_SEL_SFT, rt5640_if2_adc_l_src);
+
+static const struct snd_kcontrol_new rt5640_if2_adc_l_mux =
+       SOC_DAPM_ENUM("IF2 ADC left channel source", rt5640_if2_adc_l_enum);
+
+static const char *rt5640_if2_adc_r_src[] = {"TxDP", "Mono ADC MIXR"};
+
+static const SOC_ENUM_SINGLE_DECL(rt5640_if2_adc_r_enum, RT5640_DSP_PATH2,
+                       RT5640_IF2_ADC_R_SEL_SFT, rt5640_if2_adc_r_src);
+
+static const struct snd_kcontrol_new rt5640_if2_adc_r_mux =
+       SOC_DAPM_ENUM("IF2 ADC right channel source", rt5640_if2_adc_r_enum);
+
+/* digital interface and iis interface map */
+static const char *rt5640_dai_iis_map[] = {"1:1|2:2|3:3", "1:1|2:3|3:2",
+       "1:3|2:1|3:2", "1:3|2:2|3:1", "1:2|2:3|3:1",
+       "1:2|2:1|3:3", "1:1|2:1|3:3", "1:2|2:2|3:3"};
+
+static const SOC_ENUM_SINGLE_DECL(
+       rt5640_dai_iis_map_enum, RT5640_I2S1_SDP,
+       RT5640_I2S_IF_SFT, rt5640_dai_iis_map);
+
+static const struct snd_kcontrol_new rt5640_dai_mux =
+       SOC_DAPM_ENUM("DAI select", rt5640_dai_iis_map_enum);
+
+/* SDI select */
+static const char *rt5640_sdi_sel[] = {"IF1", "IF2"};
+
+static const SOC_ENUM_SINGLE_DECL(
+       rt5640_sdi_sel_enum, RT5640_I2S2_SDP,
+       RT5640_I2S2_SDI_SFT, rt5640_sdi_sel);
+
+static const struct snd_kcontrol_new rt5640_sdi_mux =
+       SOC_DAPM_ENUM("SDI select", rt5640_sdi_sel_enum);
+
+static int spk_event(struct snd_soc_dapm_widget *w,
+       struct snd_kcontrol *kcontrol, int event)
+{
+       struct snd_soc_codec *codec = w->codec;
+       static unsigned int spkl_out_enable;
+       static unsigned int spkr_out_enable;
+
+       switch (event) {
+       case SND_SOC_DAPM_POST_PMU:
+               pr_info("spk_event --SND_SOC_DAPM_POST_PMU\n");
+               snd_soc_update_bits(codec, RT5640_PWR_DIG1, 0x0001, 0x0001);
+               rt5640_index_update_bits(codec, 0x1c, 0xf000, 0xf000);
+               /* rt5640_index_write(codec, 0x1c, 0xfd21); */
+               break;
+
+       case SND_SOC_DAPM_PRE_PMD:
+               pr_info("spk_event --SND_SOC_DAPM_POST_PMD\n");
+               /* rt5640_index_write(codec, 0x1c, 0xfd00); */
+               rt5640_index_update_bits(codec, 0x1c, 0xf000, 0x0000);
+               snd_soc_update_bits(codec, RT5640_PWR_DIG1, 0x0001, 0x0000);
+               break;
+
+       default:
+               return 0;
+       }
+       return 0;
+}
+
+static int hp_event(struct snd_soc_dapm_widget *w,
+       struct snd_kcontrol *kcontrol, int event)
+{
+       struct snd_soc_codec *codec = w->codec;
+       static unsigned int hp_out_enable;
+
+       switch (event) {
+       case SND_SOC_DAPM_POST_PMU:
+               pr_info("hp_event --SND_SOC_DAPM_POST_PMU\n");
+               break;
+
+       case SND_SOC_DAPM_PRE_PMD:
+               pr_info("hp_event --SND_SOC_DAPM_POST_PMD\n");
+               break;
+
+       default:
+               return 0;
+       }
+       return 0;
+}
+
+static const struct snd_soc_dapm_widget rt5640_dapm_widgets[] = {
+       SND_SOC_DAPM_SUPPLY("PLL1", RT5640_PWR_ANLG2,
+                       RT5640_PWR_PLL_BIT, 0, NULL, 0),
+       /* Input Side */
+       /* micbias */
+       SND_SOC_DAPM_SUPPLY("LDO2", RT5640_PWR_ANLG1,
+                       RT5640_PWR_LDO2_BIT, 0, NULL, 0),
+       SND_SOC_DAPM_MICBIAS("micbias1", RT5640_PWR_ANLG2,
+                       RT5640_PWR_MB1_BIT, 0),
+       SND_SOC_DAPM_MICBIAS("micbias2", RT5640_PWR_ANLG2,
+                       RT5640_PWR_MB2_BIT, 0),
+       /* Input Lines */
+
+       SND_SOC_DAPM_INPUT("MIC1"),
+       SND_SOC_DAPM_INPUT("MIC2"),
+       SND_SOC_DAPM_INPUT("DMIC1"),
+       SND_SOC_DAPM_INPUT("DMIC2"),
+       SND_SOC_DAPM_INPUT("IN1P"),
+       SND_SOC_DAPM_INPUT("IN1N"),
+       SND_SOC_DAPM_INPUT("IN2P"),
+       SND_SOC_DAPM_INPUT("IN2N"),
+       SND_SOC_DAPM_INPUT("DMIC L1"),
+       SND_SOC_DAPM_INPUT("DMIC R1"),
+       SND_SOC_DAPM_INPUT("DMIC L2"),
+       SND_SOC_DAPM_INPUT("DMIC R2"),
+       SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
+               set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
+       /* Boost */
+       SND_SOC_DAPM_PGA("BST1", RT5640_PWR_ANLG2,
+               RT5640_PWR_BST1_BIT, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("BST2", RT5640_PWR_ANLG2,
+               RT5640_PWR_BST4_BIT, 0, NULL, 0),
+       /* Input Volume */
+       SND_SOC_DAPM_PGA("INL VOL", RT5640_PWR_VOL,
+               RT5640_PWR_IN_L_BIT, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("INR VOL", RT5640_PWR_VOL,
+               RT5640_PWR_IN_R_BIT, 0, NULL, 0),
+       /* IN Mux */
+       SND_SOC_DAPM_MUX("INL Mux", SND_SOC_NOPM, 0, 0, &rt5640_inl_mux),
+       SND_SOC_DAPM_MUX("INR Mux", SND_SOC_NOPM, 0, 0, &rt5640_inr_mux),
+       /* REC Mixer */
+       SND_SOC_DAPM_MIXER("RECMIXL", RT5640_PWR_MIXER, RT5640_PWR_RM_L_BIT, 0,
+                       rt5640_rec_l_mix, ARRAY_SIZE(rt5640_rec_l_mix)),
+       SND_SOC_DAPM_MIXER("RECMIXR", RT5640_PWR_MIXER, RT5640_PWR_RM_R_BIT, 0,
+                       rt5640_rec_r_mix, ARRAY_SIZE(rt5640_rec_r_mix)),
+       /* ADCs */
+       SND_SOC_DAPM_ADC("ADC L", NULL, RT5640_PWR_DIG1,
+                       RT5640_PWR_ADC_L_BIT, 0),
+       SND_SOC_DAPM_ADC("ADC R", NULL, RT5640_PWR_DIG1,
+                       RT5640_PWR_ADC_R_BIT, 0),
+       /* ADC Mux */
+       SND_SOC_DAPM_MUX("Stereo ADC L2 Mux", SND_SOC_NOPM, 0, 0,
+                               &rt5640_sto_adc_l2_mux),
+       SND_SOC_DAPM_MUX("Stereo ADC R2 Mux", SND_SOC_NOPM, 0, 0,
+                               &rt5640_sto_adc_r2_mux),
+       SND_SOC_DAPM_MUX("Stereo ADC L1 Mux", SND_SOC_NOPM, 0, 0,
+                               &rt5640_sto_adc_l1_mux),
+       SND_SOC_DAPM_MUX("Stereo ADC R1 Mux", SND_SOC_NOPM, 0, 0,
+                               &rt5640_sto_adc_r1_mux),
+       SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
+                               &rt5640_mono_adc_l2_mux),
+       SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
+                               &rt5640_mono_adc_l1_mux),
+       SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
+                               &rt5640_mono_adc_r1_mux),
+       SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
+                               &rt5640_mono_adc_r2_mux),
+       /* ADC Mixer */
+       SND_SOC_DAPM_SUPPLY("stereo filter", RT5640_PWR_DIG2,
+               RT5640_PWR_ADC_SF_BIT, 0, NULL, 0),
+       SND_SOC_DAPM_MIXER("Stereo ADC MIXL", SND_SOC_NOPM, 0, 0,
+               rt5640_sto_adc_l_mix, ARRAY_SIZE(rt5640_sto_adc_l_mix)),
+       SND_SOC_DAPM_MIXER("Stereo ADC MIXR", SND_SOC_NOPM, 0, 0,
+               rt5640_sto_adc_r_mix, ARRAY_SIZE(rt5640_sto_adc_r_mix)),
+       SND_SOC_DAPM_SUPPLY("mono left filter", RT5640_PWR_DIG2,
+               RT5640_PWR_ADC_MF_L_BIT, 0, NULL, 0),
+       SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
+               rt5640_mono_adc_l_mix, ARRAY_SIZE(rt5640_mono_adc_l_mix)),
+       SND_SOC_DAPM_SUPPLY("mono right filter", RT5640_PWR_DIG2,
+               RT5640_PWR_ADC_MF_R_BIT, 0, NULL, 0),
+       SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
+               rt5640_mono_adc_r_mix, ARRAY_SIZE(rt5640_mono_adc_r_mix)),
+
+       /* IF2 Mux */
+       SND_SOC_DAPM_MUX("IF2 ADC L Mux", SND_SOC_NOPM, 0, 0,
+                               &rt5640_if2_adc_l_mux),
+       SND_SOC_DAPM_MUX("IF2 ADC R Mux", SND_SOC_NOPM, 0, 0,
+                               &rt5640_if2_adc_r_mux),
+
+       /* Digital Interface */
+       SND_SOC_DAPM_SUPPLY("I2S1", RT5640_PWR_DIG1,
+               RT5640_PWR_I2S1_BIT, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_SUPPLY("I2S2", RT5640_PWR_DIG1,
+               RT5640_PWR_I2S2_BIT, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_SUPPLY("I2S3", RT5640_PWR_DIG1,
+               RT5640_PWR_I2S3_BIT, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+       /* Digital Interface Select */
+       SND_SOC_DAPM_MUX("DAI1 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+       SND_SOC_DAPM_MUX("DAI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+       SND_SOC_DAPM_MUX("DAI1 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+       SND_SOC_DAPM_MUX("DAI1 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+       SND_SOC_DAPM_MUX("SDI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_sdi_mux),
+
+       SND_SOC_DAPM_MUX("DAI2 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+       SND_SOC_DAPM_MUX("DAI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+       SND_SOC_DAPM_MUX("DAI2 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+       SND_SOC_DAPM_MUX("DAI2 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+       SND_SOC_DAPM_MUX("SDI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_sdi_mux),
+
+       SND_SOC_DAPM_MUX("DAI3 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+       SND_SOC_DAPM_MUX("DAI3 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
+
+       /* Audio Interface */
+       SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
+       SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
+       SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
+       SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
+       SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
+       SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
+
+       /* Audio DSP */
+       SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+       /* ANC */
+       SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+       /* Output Side */
+       /* DAC mixer before sound effect  */
+       SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
+               rt5640_dac_l_mix, ARRAY_SIZE(rt5640_dac_l_mix)),
+       SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
+               rt5640_dac_r_mix, ARRAY_SIZE(rt5640_dac_r_mix)),
+
+       /* DAC2 channel Mux */
+       SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
+                               &rt5640_dac_l2_mux),
+       SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
+                               &rt5640_dac_r2_mux),
+
+       /* DAC Mixer */
+       SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
+               rt5640_sto_dac_l_mix, ARRAY_SIZE(rt5640_sto_dac_l_mix)),
+       SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
+               rt5640_sto_dac_r_mix, ARRAY_SIZE(rt5640_sto_dac_r_mix)),
+       SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
+               rt5640_mono_dac_l_mix, ARRAY_SIZE(rt5640_mono_dac_l_mix)),
+       SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
+               rt5640_mono_dac_r_mix, ARRAY_SIZE(rt5640_mono_dac_r_mix)),
+       SND_SOC_DAPM_MIXER("DIG MIXL", SND_SOC_NOPM, 0, 0,
+               rt5640_dig_l_mix, ARRAY_SIZE(rt5640_dig_l_mix)),
+       SND_SOC_DAPM_MIXER("DIG MIXR", SND_SOC_NOPM, 0, 0,
+               rt5640_dig_r_mix, ARRAY_SIZE(rt5640_dig_r_mix)),
+       /* DACs */
+       SND_SOC_DAPM_DAC("DAC L1", NULL, RT5640_PWR_DIG1,
+                       RT5640_PWR_DAC_L1_BIT, 0),
+       SND_SOC_DAPM_DAC("DAC L2", NULL, RT5640_PWR_DIG1,
+                       RT5640_PWR_DAC_L2_BIT, 0),
+       SND_SOC_DAPM_DAC("DAC R1", NULL, RT5640_PWR_DIG1,
+                       RT5640_PWR_DAC_R1_BIT, 0),
+       SND_SOC_DAPM_DAC("DAC R2", NULL, RT5640_PWR_DIG1,
+                       RT5640_PWR_DAC_R2_BIT, 0),
+       /* SPK/OUT Mixer */
+       SND_SOC_DAPM_MIXER("SPK MIXL", RT5640_PWR_MIXER, RT5640_PWR_SM_L_BIT,
+               0, rt5640_spk_l_mix, ARRAY_SIZE(rt5640_spk_l_mix)),
+       SND_SOC_DAPM_MIXER("SPK MIXR", RT5640_PWR_MIXER, RT5640_PWR_SM_R_BIT,
+               0, rt5640_spk_r_mix, ARRAY_SIZE(rt5640_spk_r_mix)),
+       SND_SOC_DAPM_MIXER("OUT MIXL", RT5640_PWR_MIXER, RT5640_PWR_OM_L_BIT,
+               0, rt5640_out_l_mix, ARRAY_SIZE(rt5640_out_l_mix)),
+       SND_SOC_DAPM_MIXER("OUT MIXR", RT5640_PWR_MIXER, RT5640_PWR_OM_R_BIT,
+               0, rt5640_out_r_mix, ARRAY_SIZE(rt5640_out_r_mix)),
+       /* Ouput Volume */
+       SND_SOC_DAPM_PGA("SPKVOL L", RT5640_PWR_VOL,
+               RT5640_PWR_SV_L_BIT, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("SPKVOL R", RT5640_PWR_VOL,
+               RT5640_PWR_SV_R_BIT, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("OUTVOL L", RT5640_PWR_VOL,
+               RT5640_PWR_OV_L_BIT, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("OUTVOL R", RT5640_PWR_VOL,
+               RT5640_PWR_OV_R_BIT, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("HPOVOL L", RT5640_PWR_VOL,
+               RT5640_PWR_HV_L_BIT, 0, NULL, 0),
+       SND_SOC_DAPM_PGA("HPOVOL R", RT5640_PWR_VOL,
+               RT5640_PWR_HV_R_BIT, 0, NULL, 0),
+       /* SPO/HPO/LOUT/Mono Mixer */
+       SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0,
+               0, rt5640_spo_l_mix, ARRAY_SIZE(rt5640_spo_l_mix)),
+       SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0,
+               0, rt5640_spo_r_mix, ARRAY_SIZE(rt5640_spo_r_mix)),
+
+       SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
+               rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
+       SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
+               rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
+       SND_SOC_DAPM_MIXER("LOUT MIX", RT5640_PWR_ANLG1, RT5640_PWR_LM_BIT, 0,
+               rt5640_lout_mix, ARRAY_SIZE(rt5640_lout_mix)),
+       SND_SOC_DAPM_MIXER("Mono MIX", RT5640_PWR_ANLG1, RT5640_PWR_MM_BIT, 0,
+               rt5640_mono_mix, ARRAY_SIZE(rt5640_mono_mix)),
+
+       SND_SOC_DAPM_SUPPLY("Improve mono amp drv", RT5640_PWR_ANLG1,
+               RT5640_PWR_MA_BIT, 0, NULL, 0),
+
+       SND_SOC_DAPM_SUPPLY("Improve HP amp drv", RT5640_PWR_ANLG1,
+       SND_SOC_NOPM, 0, hp_event, SND_SOC_DAPM_PRE_PMD |
+                                       SND_SOC_DAPM_POST_PMU),
+
+       SND_SOC_DAPM_PGA("HP L amp", RT5640_PWR_ANLG1,
+               RT5640_PWR_HP_L_BIT, 0, NULL, 0),
+
+       SND_SOC_DAPM_PGA("HP R amp", RT5640_PWR_ANLG1,
+               RT5640_PWR_HP_R_BIT, 0, NULL, 0),
+
+       SND_SOC_DAPM_SUPPLY("Improve SPK amp drv", RT5640_PWR_DIG1,
+               SND_SOC_NOPM, 0, spk_event,
+               SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
+
+       /* Output Lines */
+       SND_SOC_DAPM_OUTPUT("SPOLP"),
+       SND_SOC_DAPM_OUTPUT("SPOLN"),
+       SND_SOC_DAPM_OUTPUT("SPORP"),
+       SND_SOC_DAPM_OUTPUT("SPORN"),
+       SND_SOC_DAPM_OUTPUT("HPOL"),
+       SND_SOC_DAPM_OUTPUT("HPOR"),
+       SND_SOC_DAPM_OUTPUT("LOUTL"),
+       SND_SOC_DAPM_OUTPUT("LOUTR"),
+       SND_SOC_DAPM_OUTPUT("MonoP"),
+       SND_SOC_DAPM_OUTPUT("MonoN"),
+};
+
+static const struct snd_soc_dapm_route rt5640_dapm_routes[] = {
+       {"IN1P", NULL, "LDO2"},
+       {"IN2P", NULL, "LDO2"},
+
+       {"IN1P", NULL, "MIC1"},
+       {"IN1N", NULL, "MIC1"},
+       {"IN2P", NULL, "MIC2"},
+       {"IN2N", NULL, "MIC2"},
+
+       {"DMIC L1", NULL, "DMIC1"},
+       {"DMIC R1", NULL, "DMIC1"},
+       {"DMIC L2", NULL, "DMIC2"},
+       {"DMIC R2", NULL, "DMIC2"},
+
+       {"BST1", NULL, "IN1P"},
+       {"BST1", NULL, "IN1N"},
+       {"BST2", NULL, "IN2P"},
+       {"BST2", NULL, "IN2N"},
+
+       {"INL VOL", NULL, "IN2P"},
+       {"INR VOL", NULL, "IN2N"},
+
+       {"RECMIXL", "HPOL Switch", "HPOL"},
+       {"RECMIXL", "INL Switch", "INL VOL"},
+       {"RECMIXL", "BST2 Switch", "BST2"},
+       {"RECMIXL", "BST1 Switch", "BST1"},
+       {"RECMIXL", "OUT MIXL Switch", "OUT MIXL"},
+
+       {"RECMIXR", "HPOR Switch", "HPOR"},
+       {"RECMIXR", "INR Switch", "INR VOL"},
+       {"RECMIXR", "BST2 Switch", "BST2"},
+       {"RECMIXR", "BST1 Switch", "BST1"},
+       {"RECMIXR", "OUT MIXR Switch", "OUT MIXR"},
+
+       {"ADC L", NULL, "RECMIXL"},
+       {"ADC R", NULL, "RECMIXR"},
+
+       {"DMIC L1", NULL, "DMIC CLK"},
+       {"DMIC L2", NULL, "DMIC CLK"},
+
+       {"Stereo ADC L2 Mux", "DMIC1", "DMIC L1"},
+       {"Stereo ADC L2 Mux", "DMIC2", "DMIC L2"},
+       {"Stereo ADC L2 Mux", "DIG MIX", "DIG MIXL"},
+       {"Stereo ADC L1 Mux", "ADC", "ADC L"},
+       {"Stereo ADC L1 Mux", "DIG MIX", "DIG MIXL"},
+
+       {"Stereo ADC R1 Mux", "ADC", "ADC R"},
+       {"Stereo ADC R1 Mux", "DIG MIX", "DIG MIXR"},
+       {"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
+       {"Stereo ADC R2 Mux", "DMIC2", "DMIC R2"},
+       {"Stereo ADC R2 Mux", "DIG MIX", "DIG MIXR"},
+
+       {"Mono ADC L2 Mux", "DMIC L1", "DMIC L1"},
+       {"Mono ADC L2 Mux", "DMIC L2", "DMIC L2"},
+       {"Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
+       {"Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
+       {"Mono ADC L1 Mux", "ADCL", "ADC L"},
+
+       {"Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
+       {"Mono ADC R1 Mux", "ADCR", "ADC R"},
+       {"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
+       {"Mono ADC R2 Mux", "DMIC R2", "DMIC R2"},
+       {"Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
+
+       {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
+       {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
+       {"Stereo ADC MIXL", NULL, "stereo filter"},
+       {"stereo filter", NULL, "PLL1", check_sysclk1_source},
+
+       {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
+       {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
+       {"Stereo ADC MIXR", NULL, "stereo filter"},
+       {"stereo filter", NULL, "PLL1", check_sysclk1_source},
+
+       {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
+       {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
+       {"Mono ADC MIXL", NULL, "mono left filter"},
+       {"mono left filter", NULL, "PLL1", check_sysclk1_source},
+
+       {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
+       {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
+       {"Mono ADC MIXR", NULL, "mono right filter"},
+       {"mono right filter", NULL, "PLL1", check_sysclk1_source},
+
+       {"IF2 ADC L Mux", "Mono ADC MIXL", "Mono ADC MIXL"},
+       {"IF2 ADC R Mux", "Mono ADC MIXR", "Mono ADC MIXR"},
+
+       {"IF2 ADC L", NULL, "IF2 ADC L Mux"},
+       {"IF2 ADC R", NULL, "IF2 ADC R Mux"},
+       {"IF3 ADC L", NULL, "Mono ADC MIXL"},
+       {"IF3 ADC R", NULL, "Mono ADC MIXR"},
+       {"IF1 ADC L", NULL, "Stereo ADC MIXL"},
+       {"IF1 ADC R", NULL, "Stereo ADC MIXR"},
+
+       {"IF1 ADC", NULL, "I2S1"},
+       {"IF1 ADC", NULL, "IF1 ADC L"},
+       {"IF1 ADC", NULL, "IF1 ADC R"},
+       {"IF2 ADC", NULL, "I2S2"},
+       {"IF2 ADC", NULL, "IF2 ADC L"},
+       {"IF2 ADC", NULL, "IF2 ADC R"},
+       {"IF3 ADC", NULL, "I2S3"},
+       {"IF3 ADC", NULL, "IF3 ADC L"},
+       {"IF3 ADC", NULL, "IF3 ADC R"},
+
+       {"DAI1 TX Mux", "1:1|2:2|3:3", "IF1 ADC"},
+       {"DAI1 TX Mux", "1:1|2:3|3:2", "IF1 ADC"},
+       {"DAI1 TX Mux", "1:3|2:1|3:2", "IF2 ADC"},
+       {"DAI1 TX Mux", "1:2|2:1|3:3", "IF2 ADC"},
+       {"DAI1 TX Mux", "1:3|2:2|3:1", "IF3 ADC"},
+       {"DAI1 TX Mux", "1:2|2:3|3:1", "IF3 ADC"},
+       {"DAI1 IF1 Mux", "1:1|2:1|3:3", "IF1 ADC"},
+       {"DAI1 IF2 Mux", "1:1|2:1|3:3", "IF2 ADC"},
+       {"SDI1 TX Mux", "IF1", "DAI1 IF1 Mux"},
+       {"SDI1 TX Mux", "IF2", "DAI1 IF2 Mux"},
+
+       {"DAI2 TX Mux", "1:2|2:3|3:1", "IF1 ADC"},
+       {"DAI2 TX Mux", "1:2|2:1|3:3", "IF1 ADC"},
+       {"DAI2 TX Mux", "1:1|2:2|3:3", "IF2 ADC"},
+       {"DAI2 TX Mux", "1:3|2:2|3:1", "IF2 ADC"},
+       {"DAI2 TX Mux", "1:1|2:3|3:2", "IF3 ADC"},
+       {"DAI2 TX Mux", "1:3|2:1|3:2", "IF3 ADC"},
+       {"DAI2 IF1 Mux", "1:2|2:2|3:3", "IF1 ADC"},
+       {"DAI2 IF2 Mux", "1:2|2:2|3:3", "IF2 ADC"},
+       {"SDI2 TX Mux", "IF1", "DAI2 IF1 Mux"},
+       {"SDI2 TX Mux", "IF2", "DAI2 IF2 Mux"},
+
+       {"DAI3 TX Mux", "1:3|2:1|3:2", "IF1 ADC"},
+       {"DAI3 TX Mux", "1:3|2:2|3:1", "IF1 ADC"},
+       {"DAI3 TX Mux", "1:1|2:3|3:2", "IF2 ADC"},
+       {"DAI3 TX Mux", "1:2|2:3|3:1", "IF2 ADC"},
+       {"DAI3 TX Mux", "1:1|2:2|3:3", "IF3 ADC"},
+       {"DAI3 TX Mux", "1:2|2:1|3:3", "IF3 ADC"},
+       {"DAI3 TX Mux", "1:1|2:1|3:3", "IF3 ADC"},
+       {"DAI3 TX Mux", "1:2|2:2|3:3", "IF3 ADC"},
+
+       {"AIF1TX", NULL, "DAI1 TX Mux"},
+       {"AIF1TX", NULL, "SDI1 TX Mux"},
+       {"AIF2TX", NULL, "DAI2 TX Mux"},
+       {"AIF2TX", NULL, "SDI2 TX Mux"},
+       {"AIF3TX", NULL, "DAI3 TX Mux"},
+
+       {"DAI1 RX Mux", "1:1|2:2|3:3", "AIF1RX"},
+       {"DAI1 RX Mux", "1:1|2:3|3:2", "AIF1RX"},
+       {"DAI1 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
+       {"DAI1 RX Mux", "1:2|2:3|3:1", "AIF2RX"},
+       {"DAI1 RX Mux", "1:2|2:1|3:3", "AIF2RX"},
+       {"DAI1 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
+       {"DAI1 RX Mux", "1:3|2:1|3:2", "AIF3RX"},
+       {"DAI1 RX Mux", "1:3|2:2|3:1", "AIF3RX"},
+
+       {"DAI2 RX Mux", "1:3|2:1|3:2", "AIF1RX"},
+       {"DAI2 RX Mux", "1:2|2:1|3:3", "AIF1RX"},
+       {"DAI2 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
+       {"DAI2 RX Mux", "1:1|2:2|3:3", "AIF2RX"},
+       {"DAI2 RX Mux", "1:3|2:2|3:1", "AIF2RX"},
+       {"DAI2 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
+       {"DAI2 RX Mux", "1:1|2:3|3:2", "AIF3RX"},
+       {"DAI2 RX Mux", "1:2|2:3|3:1", "AIF3RX"},
+
+       {"DAI3 RX Mux", "1:3|2:2|3:1", "AIF1RX"},
+       {"DAI3 RX Mux", "1:2|2:3|3:1", "AIF1RX"},
+       {"DAI3 RX Mux", "1:1|2:3|3:2", "AIF2RX"},
+       {"DAI3 RX Mux", "1:3|2:1|3:2", "AIF2RX"},
+       {"DAI3 RX Mux", "1:1|2:2|3:3", "AIF3RX"},
+       {"DAI3 RX Mux", "1:2|2:1|3:3", "AIF3RX"},
+       {"DAI3 RX Mux", "1:1|2:1|3:3", "AIF3RX"},
+       {"DAI3 RX Mux", "1:2|2:2|3:3", "AIF3RX"},
+
+       {"IF1 DAC", NULL, "I2S1"},
+       {"IF1 DAC", NULL, "DAI1 RX Mux"},
+       {"IF2 DAC", NULL, "I2S2"},
+       {"IF2 DAC", NULL, "DAI2 RX Mux"},
+       {"IF3 DAC", NULL, "I2S3"},
+       {"IF3 DAC", NULL, "DAI3 RX Mux"},
+
+       {"IF1 DAC L", NULL, "IF1 DAC"},
+       {"IF1 DAC R", NULL, "IF1 DAC"},
+       {"IF2 DAC L", NULL, "IF2 DAC"},
+       {"IF2 DAC R", NULL, "IF2 DAC"},
+       {"IF3 DAC L", NULL, "IF3 DAC"},
+       {"IF3 DAC R", NULL, "IF3 DAC"},
+
+       {"DAC MIXL", "Stereo ADC Switch", "Stereo ADC MIXL"},
+       {"DAC MIXL", "INF1 Switch", "IF1 DAC L"},
+       {"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"},
+       {"DAC MIXR", "INF1 Switch", "IF1 DAC R"},
+
+       {"ANC", NULL, "Stereo ADC MIXL"},
+       {"ANC", NULL, "Stereo ADC MIXR"},
+
+       {"Audio DSP", NULL, "DAC MIXL"},
+       {"Audio DSP", NULL, "DAC MIXR"},
+
+       {"DAC L2 Mux", "IF2", "IF2 DAC L"},
+       {"DAC L2 Mux", "IF3", "IF3 DAC L"},
+       {"DAC L2 Mux", "Base L/R", "Audio DSP"},
+
+       {"DAC R2 Mux", "IF2", "IF2 DAC R"},
+       {"DAC R2 Mux", "IF3", "IF3 DAC R"},
+
+       {"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
+       {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
+       {"Stereo DAC MIXL", "ANC Switch", "ANC"},
+       {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
+       {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
+       {"Stereo DAC MIXR", "ANC Switch", "ANC"},
+
+       {"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
+       {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
+       {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
+       {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
+       {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
+       {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
+
+       {"DIG MIXL", "DAC L1 Switch", "DAC MIXL"},
+       {"DIG MIXL", "DAC L2 Switch", "DAC L2 Mux"},
+       {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
+       {"DIG MIXR", "DAC R2 Switch", "DAC R2 Mux"},
+
+       {"DAC L1", NULL, "Stereo DAC MIXL"},
+       {"DAC L1", NULL, "PLL1", check_sysclk1_source},
+       {"DAC R1", NULL, "Stereo DAC MIXR"},
+       {"DAC R1", NULL, "PLL1", check_sysclk1_source},
+       {"DAC L2", NULL, "Mono DAC MIXL"},
+       {"DAC L2", NULL, "PLL1", check_sysclk1_source},
+       {"DAC R2", NULL, "Mono DAC MIXR"},
+       {"DAC R2", NULL, "PLL1", check_sysclk1_source},
+
+       {"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
+       {"SPK MIXL", "INL Switch", "INL VOL"},
+       {"SPK MIXL", "DAC L1 Switch", "DAC L1"},
+       {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
+       {"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"},
+       {"SPK MIXR", "REC MIXR Switch", "RECMIXR"},
+       {"SPK MIXR", "INR Switch", "INR VOL"},
+       {"SPK MIXR", "DAC R1 Switch", "DAC R1"},
+       {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
+       {"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"},
+
+       {"OUT MIXL", "SPK MIXL Switch", "SPK MIXL"},
+       {"OUT MIXL", "BST1 Switch", "BST1"},
+       {"OUT MIXL", "INL Switch", "INL VOL"},
+       {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
+       {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
+       {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
+       {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
+
+       {"OUT MIXR", "SPK MIXR Switch", "SPK MIXR"},
+       {"OUT MIXR", "BST2 Switch", "BST2"},
+       {"OUT MIXR", "BST1 Switch", "BST1"},
+       {"OUT MIXR", "INR Switch", "INR VOL"},
+       {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
+       {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
+       {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
+       {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
+
+       {"SPKVOL L", NULL, "SPK MIXL"},
+       {"SPKVOL R", NULL, "SPK MIXR"},
+       {"HPOVOL L", NULL, "OUT MIXL"},
+       {"HPOVOL R", NULL, "OUT MIXR"},
+       {"OUTVOL L", NULL, "OUT MIXL"},
+       {"OUTVOL R", NULL, "OUT MIXR"},
+
+       {"SPOL MIX", "DAC R1 Switch", "DAC R1"},
+       {"SPOL MIX", "DAC L1 Switch", "DAC L1"},
+       {"SPOL MIX", "SPKVOL R Switch", "SPKVOL R"},
+       {"SPOL MIX", "SPKVOL L Switch", "SPKVOL L"},
+       {"SPOL MIX", "BST1 Switch", "BST1"},
+       {"SPOR MIX", "DAC R1 Switch", "DAC R1"},
+       {"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"},
+       {"SPOR MIX", "BST1 Switch", "BST1"},
+
+       {"HPOL MIX", "DAC2 Switch", "DAC L2"},
+       {"HPOL MIX", "DAC1 Switch", "DAC L1"},
+       {"HPOL MIX", "HPVOL Switch", "HPOVOL L"},
+       {"HPOR MIX", "DAC2 Switch", "DAC R2"},
+       {"HPOR MIX", "DAC1 Switch", "DAC R1"},
+       {"HPOR MIX", "HPVOL Switch", "HPOVOL R"},
+
+       {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
+       {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
+       {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
+       {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
+
+       {"Mono MIX", "DAC R2 Switch", "DAC R2"},
+       {"Mono MIX", "DAC L2 Switch", "DAC L2"},
+       {"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
+       {"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
+       {"Mono MIX", "BST1 Switch", "BST1"},
+
+       {"HP L amp", NULL, "HPOL MIX"},
+       {"HP R amp", NULL, "HPOR MIX"},
+
+/*     {"HP L amp", NULL, "Improve HP amp drv"},
+       {"HP R amp", NULL, "Improve HP amp drv"}, */
+
+       {"SPOLP", NULL, "SPOL MIX"},
+       {"SPOLN", NULL, "SPOL MIX"},
+       {"SPORP", NULL, "SPOR MIX"},
+       {"SPORN", NULL, "SPOR MIX"},
+
+       {"SPOLP", NULL, "Improve SPK amp drv"},
+       {"SPOLN", NULL, "Improve SPK amp drv"},
+       {"SPORP", NULL, "Improve SPK amp drv"},
+       {"SPORN", NULL, "Improve SPK amp drv"},
+
+       {"HPOL", NULL, "Improve HP amp drv"},
+       {"HPOR", NULL, "Improve HP amp drv"},
+
+       {"HPOL", NULL, "HP L amp"},
+       {"HPOR", NULL, "HP R amp"},
+       {"LOUTL", NULL, "LOUT MIX"},
+       {"LOUTR", NULL, "LOUT MIX"},
+       {"MonoP", NULL, "Mono MIX"},
+       {"MonoN", NULL, "Mono MIX"},
+       {"MonoP", NULL, "Improve mono amp drv"},
+};
+
+static int get_sdp_info(struct snd_soc_codec *codec, int dai_id)
+{
+       int ret = 0, val = snd_soc_read(codec, RT5640_I2S1_SDP);
+
+       if (codec == NULL)
+               return -EINVAL;
+
+       val = (val & RT5640_I2S_IF_MASK) >> RT5640_I2S_IF_SFT;
+       switch (dai_id) {
+       case RT5640_AIF1:
+               if (val == RT5640_IF_123 || val == RT5640_IF_132 ||
+                       val == RT5640_IF_113)
+                       ret |= RT5640_U_IF1;
+               if (val == RT5640_IF_312 || val == RT5640_IF_213 ||
+                       val == RT5640_IF_113)
+                       ret |= RT5640_U_IF2;
+               if (val == RT5640_IF_321 || val == RT5640_IF_231)
+                       ret |= RT5640_U_IF3;
+               break;
+
+       case RT5640_AIF2:
+               if (val == RT5640_IF_231 || val == RT5640_IF_213 ||
+                       val == RT5640_IF_223)
+                       ret |= RT5640_U_IF1;
+               if (val == RT5640_IF_123 || val == RT5640_IF_321 ||
+                       val == RT5640_IF_223)
+                       ret |= RT5640_U_IF2;
+               if (val == RT5640_IF_132 || val == RT5640_IF_312)
+                       ret |= RT5640_U_IF3;
+               break;
+
+#if (CONFIG_SND_SOC_RT5643_MODULE | CONFIG_SND_SOC_RT5643 | \
+                       CONFIG_SND_SOC_RT5646_MODULE | CONFIG_SND_SOC_RT5646)
+
+       case RT5640_AIF3:
+               if (val == RT5640_IF_312 || val == RT5640_IF_321)
+                       ret |= RT5640_U_IF1;
+               if (val == RT5640_IF_132 || val == RT5640_IF_231)
+                       ret |= RT5640_U_IF2;
+               if (val == RT5640_IF_123 || val == RT5640_IF_213 ||
+                       val == RT5640_IF_113 || val == RT5640_IF_223)
+                       ret |= RT5640_U_IF3;
+               break;
+#endif
+
+       default:
+               ret = -EINVAL;
+               break;
+       }
+
+       return ret;
+}
+
+static int get_clk_info(int sclk, int rate)
+{
+       int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
+
+       if (sclk <= 0 || rate <= 0)
+               return -EINVAL;
+
+       rate = rate << 8;
+       for (i = 0; i < ARRAY_SIZE(pd); i++)
+               if (sclk == rate * pd[i])
+                       return i;
+
+       return -EINVAL;
+}
+
+static int rt5640_hw_params(struct snd_pcm_substream *substream,
+       struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
+{
+       struct snd_soc_pcm_runtime *rtd = substream->private_data;
+       struct snd_soc_codec *codec = rtd->codec;
+       struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+       unsigned int val_len = 0, val_clk, mask_clk, dai_sel;
+       int pre_div, bclk_ms, frame_size;
+
+       rt5640->lrck[dai->id] = params_rate(params);
+       pre_div = get_clk_info(rt5640->sysclk, rt5640->lrck[dai->id]);
+       if (pre_div < 0) {
+               dev_err(codec->dev, "Unsupported clock setting\n");
+               return -EINVAL;
+       }
+       frame_size = snd_soc_params_to_frame_size(params);
+       if (frame_size < 0) {
+               dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
+               return -EINVAL;
+       }
+       bclk_ms = frame_size > 32 ? 1 : 0;
+       rt5640->bclk[dai->id] = rt5640->lrck[dai->id] * (32 << bclk_ms);
+
+       dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
+               rt5640->bclk[dai->id], rt5640->lrck[dai->id]);
+       dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
+                               bclk_ms, pre_div, dai->id);
+
+       switch (params_format(params)) {
+       case SNDRV_PCM_FORMAT_S16_LE:
+               break;
+       case SNDRV_PCM_FORMAT_S20_3LE:
+               val_len |= RT5640_I2S_DL_20;
+               break;
+       case SNDRV_PCM_FORMAT_S24_LE:
+               val_len |= RT5640_I2S_DL_24;
+               break;
+       case SNDRV_PCM_FORMAT_S8:
+               val_len |= RT5640_I2S_DL_8;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       dai_sel = get_sdp_info(codec, dai->id);
+       if (dai_sel < 0) {
+               dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
+               return -EINVAL;
+       }
+       if (dai_sel & RT5640_U_IF1) {
+               mask_clk = RT5640_I2S_BCLK_MS1_MASK | RT5640_I2S_PD1_MASK;
+               val_clk = bclk_ms << RT5640_I2S_BCLK_MS1_SFT |
+                       pre_div << RT5640_I2S_PD1_SFT;
+               snd_soc_update_bits(codec, RT5640_I2S1_SDP,
+                       RT5640_I2S_DL_MASK, val_len);
+               snd_soc_update_bits(codec, RT5640_ADDA_CLK1, mask_clk, val_clk);
+       }
+       if (dai_sel & RT5640_U_IF2) {
+               mask_clk = RT5640_I2S_BCLK_MS2_MASK | RT5640_I2S_PD2_MASK;
+               val_clk = bclk_ms << RT5640_I2S_BCLK_MS2_SFT |
+                       pre_div << RT5640_I2S_PD2_SFT;
+               snd_soc_update_bits(codec, RT5640_I2S2_SDP,
+                       RT5640_I2S_DL_MASK, val_len);
+               snd_soc_update_bits(codec, RT5640_ADDA_CLK1, mask_clk, val_clk);
+       }
+#if (CONFIG_SND_SOC_RT5643_MODULE | CONFIG_SND_SOC_RT5643 | \
+                       CONFIG_SND_SOC_RT5646_MODULE | CONFIG_SND_SOC_RT5646)
+       if (dai_sel & RT5640_U_IF3) {
+               mask_clk = RT5640_I2S_BCLK_MS3_MASK | RT5640_I2S_PD3_MASK;
+               val_clk = bclk_ms << RT5640_I2S_BCLK_MS3_SFT |
+                       pre_div << RT5640_I2S_PD3_SFT;
+               snd_soc_update_bits(codec, RT5640_I2S3_SDP,
+                       RT5640_I2S_DL_MASK, val_len);
+               snd_soc_update_bits(codec, RT5640_ADDA_CLK1, mask_clk, val_clk);
+       }
+#endif
+       return 0;
+}
+
+static int rt5640_prepare(struct snd_pcm_substream *substream,
+                               struct snd_soc_dai *dai)
+{
+       struct snd_soc_pcm_runtime *rtd = substream->private_data;
+       struct snd_soc_codec *codec = rtd->codec;
+       struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+
+       rt5640->aif_pu = dai->id;
+       return 0;
+}
+
+static int rt5640_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+       struct snd_soc_codec *codec = dai->codec;
+       struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+       unsigned int reg_val = 0, dai_sel;
+
+       switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+       case SND_SOC_DAIFMT_CBM_CFM:
+               rt5640->master[dai->id] = 1;
+               break;
+       case SND_SOC_DAIFMT_CBS_CFS:
+               reg_val |= RT5640_I2S_MS_S;
+               rt5640->master[dai->id] = 0;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+       case SND_SOC_DAIFMT_NB_NF:
+               break;
+       case SND_SOC_DAIFMT_IB_NF:
+               reg_val |= RT5640_I2S_BP_INV;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+       case SND_SOC_DAIFMT_I2S:
+               break;
+       case SND_SOC_DAIFMT_LEFT_J:
+               reg_val |= RT5640_I2S_DF_LEFT;
+               break;
+       case SND_SOC_DAIFMT_DSP_A:
+               reg_val |= RT5640_I2S_DF_PCM_A;
+               break;
+       case SND_SOC_DAIFMT_DSP_B:
+               reg_val  |= RT5640_I2S_DF_PCM_B;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       dai_sel = get_sdp_info(codec, dai->id);
+       if (dai_sel < 0) {
+               dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
+               return -EINVAL;
+       }
+       if (dai_sel & RT5640_U_IF1) {
+               snd_soc_update_bits(codec, RT5640_I2S1_SDP,
+                       RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
+                       RT5640_I2S_DF_MASK, reg_val);
+       }
+       if (dai_sel & RT5640_U_IF2) {
+               snd_soc_update_bits(codec, RT5640_I2S2_SDP,
+                       RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
+                       RT5640_I2S_DF_MASK, reg_val);
+       }
+#if (CONFIG_SND_SOC_RT5643_MODULE | CONFIG_SND_SOC_RT5643 | \
+                       CONFIG_SND_SOC_RT5646_MODULE | CONFIG_SND_SOC_RT5646)
+       if (dai_sel & RT5640_U_IF3) {
+               snd_soc_update_bits(codec, RT5640_I2S3_SDP,
+                       RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
+                       RT5640_I2S_DF_MASK, reg_val);
+       }
+#endif
+       return 0;
+}
+
+static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai,
+               int clk_id, unsigned int freq, int dir)
+{
+       struct snd_soc_codec *codec = dai->codec;
+       struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+       unsigned int reg_val = 0;
+
+       if (freq == rt5640->sysclk && clk_id == rt5640->sysclk_src)
+               return 0;
+
+       switch (clk_id) {
+       case RT5640_SCLK_S_MCLK:
+               reg_val |= RT5640_SCLK_SRC_MCLK;
+               break;
+       case RT5640_SCLK_S_PLL1:
+               reg_val |= RT5640_SCLK_SRC_PLL1;
+               break;
+       case RT5640_SCLK_S_PLL1_TK:
+               reg_val |= RT5640_SCLK_SRC_PLL1T;
+               break;
+       case RT5640_SCLK_S_RCCLK:
+               reg_val |= RT5640_SCLK_SRC_RCCLK;
+               break;
+       default:
+               dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
+               return -EINVAL;
+       }
+       snd_soc_update_bits(codec, RT5640_GLB_CLK,
+               RT5640_SCLK_SRC_MASK, reg_val);
+       rt5640->sysclk = freq;
+       rt5640->sysclk_src = clk_id;
+
+       dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
+       return 0;
+}
+
+/**
+ * rt5640_pll_calc - Calcualte PLL M/N/K code.
+ * @freq_in: external clock provided to codec.
+ * @freq_out: target clock which codec works on.
+ * @pll_code: Pointer to structure with M, N, K and bypass flag.
+ *
+ * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
+ * which make calculation more efficiently.
+ *
+ * Returns 0 for success or negative error code.
+ */
+static int rt5640_pll_calc(const unsigned int freq_in,
+       const unsigned int freq_out, struct rt5640_pll_code *pll_code)
+{
+       int max_n = RT5640_PLL_N_MAX, max_m = RT5640_PLL_M_MAX;
+       int n, m, red, n_t, m_t, in_t, out_t, red_t = abs(freq_out - freq_in);
+       bool bypass = false;
+
+       if (RT5640_PLL_INP_MAX < freq_in || RT5640_PLL_INP_MIN > freq_in)
+               return -EINVAL;
+
+       for (n_t = 0; n_t <= max_n; n_t++) {
+               in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
+               if (in_t < 0)
+                       continue;
+               if (in_t == freq_out) {
+                       bypass = true;
+                       n = n_t;
+                       goto code_find;
+               }
+               for (m_t = 0; m_t <= max_m; m_t++) {
+                       out_t = in_t / (m_t + 2);
+                       red = abs(out_t - freq_out);
+                       if (red < red_t) {
+                               n = n_t;
+                               m = m_t;
+                               if (red == 0)
+                                       goto code_find;
+                               red_t = red;
+                       }
+               }
+       }
+       pr_debug("Only get approximation about PLL\n");
+
+code_find:
+
+       pll_code->m_bp = bypass;
+       pll_code->m_code = m;
+       pll_code->n_code = n;
+       pll_code->k_code = 2;
+       return 0;
+}
+
+static int rt5640_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
+                       unsigned int freq_in, unsigned int freq_out)
+{
+       struct snd_soc_codec *codec = dai->codec;
+       struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+       struct rt5640_pll_code pll_code;
+       int ret, dai_sel;
+
+       if (source == rt5640->pll_src && freq_in == rt5640->pll_in &&
+           freq_out == rt5640->pll_out)
+               return 0;
+
+       if (!freq_in || !freq_out) {
+               dev_dbg(codec->dev, "PLL disabled\n");
+
+               rt5640->pll_in = 0;
+               rt5640->pll_out = 0;
+               snd_soc_update_bits(codec, RT5640_GLB_CLK,
+                       RT5640_SCLK_SRC_MASK, RT5640_SCLK_SRC_MCLK);
+               return 0;
+       }
+
+       switch (source) {
+       case RT5640_PLL1_S_MCLK:
+               snd_soc_update_bits(codec, RT5640_GLB_CLK,
+                       RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_MCLK);
+               break;
+       case RT5640_PLL1_S_BCLK1:
+       case RT5640_PLL1_S_BCLK2:
+
+#if (CONFIG_SND_SOC_RT5643_MODULE | CONFIG_SND_SOC_RT5643 | \
+                       CONFIG_SND_SOC_RT5646_MODULE | CONFIG_SND_SOC_RT5646)
+
+       case RT5640_PLL1_S_BCLK3:
+
+#endif
+               dai_sel = get_sdp_info(codec, dai->id);
+               if (dai_sel < 0) {
+                       dev_err(codec->dev,
+                               "Failed to get sdp info: %d\n", dai_sel);
+                       return -EINVAL;
+               }
+               if (dai_sel & RT5640_U_IF1) {
+                       snd_soc_update_bits(codec, RT5640_GLB_CLK,
+                               RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK1);
+               }
+               if (dai_sel & RT5640_U_IF2) {
+                       snd_soc_update_bits(codec, RT5640_GLB_CLK,
+                               RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK2);
+               }
+               if (dai_sel & RT5640_U_IF3) {
+                       snd_soc_update_bits(codec, RT5640_GLB_CLK,
+                               RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK3);
+               }
+               break;
+       default:
+               dev_err(codec->dev, "Unknown PLL source %d\n", source);
+               return -EINVAL;
+       }
+
+       ret = rt5640_pll_calc(freq_in, freq_out, &pll_code);
+       if (ret < 0) {
+               dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
+               return ret;
+       }
+
+       dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code.m_bp,
+               (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code);
+
+       snd_soc_write(codec, RT5640_PLL_CTRL1,
+               pll_code.n_code << RT5640_PLL_N_SFT | pll_code.k_code);
+       snd_soc_write(codec, RT5640_PLL_CTRL2,
+               (pll_code.m_bp ? 0 : pll_code.m_code) << RT5640_PLL_M_SFT |
+               pll_code.m_bp << RT5640_PLL_M_BP_SFT);
+
+       rt5640->pll_in = freq_in;
+       rt5640->pll_out = freq_out;
+       rt5640->pll_src = source;
+
+       return 0;
+}
+
+/**
+ * rt5640_index_show - Dump private registers.
+ * @dev: codec device.
+ * @attr: device attribute.
+ * @buf: buffer for display.
+ *
+ * To show non-zero values of all private registers.
+ *
+ * Returns buffer length.
+ */
+static ssize_t rt5640_index_show(struct device *dev,
+       struct device_attribute *attr, char *buf)
+{
+       struct i2c_client *client = to_i2c_client(dev);
+       struct rt5640_priv *rt5640 = i2c_get_clientdata(client);
+       struct snd_soc_codec *codec = rt5640->codec;
+       unsigned int val;
+       int cnt = 0, i;
+
+       cnt += sprintf(buf, "RT5640 index register\n");
+       for (i = 0; i < 0xb4; i++) {
+               if (cnt + 9 >= PAGE_SIZE - 1)
+                       break;
+               val = rt5640_index_read(codec, i);
+               if (!val)
+                       continue;
+               cnt += snprintf(buf + cnt, 10, "%02x: %04x\n", i, val);
+       }
+
+       if (cnt >= PAGE_SIZE)
+               cnt = PAGE_SIZE - 1;
+
+       return cnt;
+}
+static DEVICE_ATTR(index_reg, 0444, rt5640_index_show, NULL);
+
+static int rt5640_set_bias_level(struct snd_soc_codec *codec,
+                       enum snd_soc_bias_level level)
+{
+       switch (level) {
+       case SND_SOC_BIAS_ON:
+#ifdef RT5640_DEMO
+               snd_soc_update_bits(codec, RT5640_SPK_VOL,
+                       RT5640_L_MUTE | RT5640_R_MUTE, 0);
+               snd_soc_update_bits(codec, RT5640_HP_VOL,
+                       RT5640_L_MUTE | RT5640_R_MUTE, 0);
+               break;
+#endif
+       case SND_SOC_BIAS_PREPARE:
+#ifdef RT5640_DEMO
+               snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
+                       RT5640_PWR_VREF1 | RT5640_PWR_MB |
+                       RT5640_PWR_BG | RT5640_PWR_VREF2,
+                       RT5640_PWR_VREF1 | RT5640_PWR_MB |
+                       RT5640_PWR_BG | RT5640_PWR_VREF2);
+               msleep(100);
+
+               snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
+                       RT5640_PWR_FV1 | RT5640_PWR_FV2,
+                       RT5640_PWR_FV1 | RT5640_PWR_FV2);
+
+               snd_soc_update_bits(codec, RT5640_PWR_ANLG2,
+                       RT5640_PWR_MB1 | RT5640_PWR_MB2,
+                       RT5640_PWR_MB1 | RT5640_PWR_MB2);
+#endif
+               break;
+
+       case SND_SOC_BIAS_STANDBY:
+#ifdef RT5640_DEMO
+               snd_soc_update_bits(codec, RT5640_SPK_VOL, RT5640_L_MUTE |
+                       RT5640_R_MUTE, RT5640_L_MUTE | RT5640_R_MUTE);
+               snd_soc_update_bits(codec, RT5640_HP_VOL, RT5640_L_MUTE |
+                       RT5640_R_MUTE, RT5640_L_MUTE | RT5640_R_MUTE);
+
+               snd_soc_update_bits(codec, RT5640_PWR_ANLG2,
+                       RT5640_PWR_MB1 | RT5640_PWR_MB2,
+                       0);
+#endif
+               if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
+                       snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
+                               RT5640_PWR_VREF1 | RT5640_PWR_MB |
+                               RT5640_PWR_BG | RT5640_PWR_VREF2,
+                               RT5640_PWR_VREF1 | RT5640_PWR_MB |
+                               RT5640_PWR_BG | RT5640_PWR_VREF2);
+                       msleep(10);
+                       snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
+                               RT5640_PWR_FV1 | RT5640_PWR_FV2,
+                               RT5640_PWR_FV1 | RT5640_PWR_FV2);
+                       codec->cache_only = false;
+                       snd_soc_cache_sync(codec);
+               }
+               break;
+
+       case SND_SOC_BIAS_OFF:
+#ifdef RT5640_DEMO
+               snd_soc_update_bits(codec, RT5640_SPK_VOL, RT5640_L_MUTE |
+                       RT5640_R_MUTE, RT5640_L_MUTE | RT5640_R_MUTE);
+               snd_soc_update_bits(codec, RT5640_HP_VOL, RT5640_L_MUTE |
+                       RT5640_R_MUTE, RT5640_L_MUTE | RT5640_R_MUTE);
+               snd_soc_update_bits(codec, RT5640_OUTPUT, RT5640_L_MUTE |
+                       RT5640_R_MUTE, RT5640_L_MUTE | RT5640_R_MUTE);
+               snd_soc_update_bits(codec, RT5640_MONO_OUT,
+                       RT5640_L_MUTE, RT5640_L_MUTE);
+#endif
+               snd_soc_write(codec, RT5640_PWR_DIG1, 0x0000);
+               snd_soc_write(codec, RT5640_PWR_DIG2, 0x0000);
+               snd_soc_write(codec, RT5640_PWR_VOL, 0x0000);
+               snd_soc_write(codec, RT5640_PWR_MIXER, 0x0000);
+               snd_soc_write(codec, RT5640_PWR_ANLG1, 0x0000);
+               snd_soc_write(codec, RT5640_PWR_ANLG2, 0x0000);
+               break;
+
+       default:
+               break;
+       }
+       codec->dapm.bias_level = level;
+
+       return 0;
+}
+
+static int rt5640_probe(struct snd_soc_codec *codec)
+{
+       struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
+       int ret;
+       u16 val;
+
+       ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
+       if (ret != 0) {
+               dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
+               return ret;
+       }
+
+       val = snd_soc_read(codec, RT5640_RESET);
+       if (val != rt5640_reg[RT5640_RESET]) {
+               dev_err(codec->dev,
+                       "Device with ID register %x is not a rt5640\n", val);
+               return -ENODEV;
+       }
+
+       rt5640_reset(codec);
+       snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
+               RT5640_PWR_VREF1 | RT5640_PWR_MB |
+               RT5640_PWR_BG | RT5640_PWR_VREF2,
+               RT5640_PWR_VREF1 | RT5640_PWR_MB |
+               RT5640_PWR_BG | RT5640_PWR_VREF2);
+       msleep(100);
+       snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
+               RT5640_PWR_FV1 | RT5640_PWR_FV2,
+               RT5640_PWR_FV1 | RT5640_PWR_FV2);
+       /* DMIC */
+       if (rt5640->dmic_en == RT5640_DMIC1) {
+               snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
+                       RT5640_GP2_PIN_MASK, RT5640_GP2_PIN_DMIC1_SCL);
+               snd_soc_update_bits(codec, RT5640_DMIC,
+                       RT5640_DMIC_1L_LH_MASK | RT5640_DMIC_1R_LH_MASK,
+                       RT5640_DMIC_1L_LH_FALLING | RT5640_DMIC_1R_LH_RISING);
+       } else if (rt5640->dmic_en == RT5640_DMIC2) {
+               snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
+                       RT5640_GP2_PIN_MASK, RT5640_GP2_PIN_DMIC1_SCL);
+               snd_soc_update_bits(codec, RT5640_DMIC,
+                       RT5640_DMIC_2L_LH_MASK | RT5640_DMIC_2R_LH_MASK,
+                       RT5640_DMIC_2L_LH_FALLING | RT5640_DMIC_2R_LH_RISING);
+       }
+
+#ifdef RT5640_DEMO
+       rt5640_reg_init(codec);
+#endif
+
+
+#if (CONFIG_SND_SOC_RT5642_MODULE | CONFIG_SND_SOC_RT5642)
+       rt5640_register_dsp(codec);
+#endif
+
+       codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
+
+       snd_soc_add_controls(codec, rt5640_snd_controls,
+               ARRAY_SIZE(rt5640_snd_controls));
+
+       rt5640->codec = codec;
+       ret = device_create_file(codec->dev, &dev_attr_index_reg);
+       if (ret != 0) {
+               dev_err(codec->dev,
+                       "Failed to create index_reg sysfs files: %d\n", ret);
+               return ret;
+       }
+
+       return 0;
+}
+
+static int rt5640_remove(struct snd_soc_codec *codec)
+{
+       rt5640_set_bias_level(codec, SND_SOC_BIAS_OFF);
+       return 0;
+}
+
+#ifdef CONFIG_PM
+static int rt5640_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+       rt5640_set_bias_level(codec, SND_SOC_BIAS_OFF);
+       return 0;
+}
+
+static int rt5640_resume(struct snd_soc_codec *codec)
+{
+       rt5640_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+       return 0;
+}
+#else
+#define rt5640_suspend NULL
+#define rt5640_resume NULL
+#endif
+
+#define RT5640_STEREO_RATES SNDRV_PCM_RATE_8000_96000
+#define RT5640_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
+                       SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
+
+struct snd_soc_dai_ops rt5640_aif_dai_ops = {
+       .hw_params = rt5640_hw_params,
+       .prepare = rt5640_prepare,
+       .set_fmt = rt5640_set_dai_fmt,
+       .set_sysclk = rt5640_set_dai_sysclk,
+       .set_pll = rt5640_set_dai_pll,
+};
+
+struct snd_soc_dai_driver rt5640_dai[] = {
+       {
+               .name = "rt5640-aif1",
+               .id = RT5640_AIF1,
+               .playback = {
+                       .stream_name = "AIF1 Playback",
+                       .channels_min = 1,
+                       .channels_max = 2,
+                       .rates = RT5640_STEREO_RATES,
+                       .formats = RT5640_FORMATS,
+               },
+               .capture = {
+                       .stream_name = "AIF1 Capture",
+                       .channels_min = 1,
+                       .channels_max = 2,
+                       .rates = RT5640_STEREO_RATES,
+                       .formats = RT5640_FORMATS,
+               },
+               .ops = &rt5640_aif_dai_ops,
+       },
+       {
+               .name = "rt5640-aif2",
+               .id = RT5640_AIF2,
+               .playback = {
+                       .stream_name = "AIF2 Playback",
+                       .channels_min = 1,
+                       .channels_max = 2,
+                       .rates = RT5640_STEREO_RATES,
+                       .formats = RT5640_FORMATS,
+               },
+               .capture = {
+                       .stream_name = "AIF2 Capture",
+                       .channels_min = 1,
+                       .channels_max = 2,
+                       .rates = RT5640_STEREO_RATES,
+                       .formats = RT5640_FORMATS,
+               },
+               .ops = &rt5640_aif_dai_ops,
+       },
+#if (CONFIG_SND_SOC_RT5643_MODULE | CONFIG_SND_SOC_RT5643 | \
+                       CONFIG_SND_SOC_RT5646_MODULE | CONFIG_SND_SOC_RT5646)
+       {
+               .name = "rt5640-aif3",
+               .id = RT5640_AIF3,
+               .playback = {
+                       .stream_name = "AIF3 Playback",
+                       .channels_min = 1,
+                       .channels_max = 2,
+                       .rates = RT5640_STEREO_RATES,
+                       .formats = RT5640_FORMATS,
+               },
+               .capture = {
+                       .stream_name = "AIF3 Capture",
+                       .channels_min = 1,
+                       .channels_max = 2,
+                       .rates = RT5640_STEREO_RATES,
+                       .formats = RT5640_FORMATS,
+               },
+               .ops = &rt5640_aif_dai_ops,
+       },
+#endif
+};
+
+static struct snd_soc_codec_driver soc_codec_dev_rt5640 = {
+       .probe = rt5640_probe,
+       .remove = rt5640_remove,
+       .suspend = rt5640_suspend,
+       .resume = rt5640_resume,
+       .set_bias_level = rt5640_set_bias_level,
+       .reg_cache_size = RT5640_VENDOR_ID2 + 1,
+       .reg_word_size = sizeof(u16),
+       .reg_cache_default = rt5640_reg,
+       .volatile_register = rt5640_volatile_register,
+       .readable_register = rt5640_readable_register,
+       .reg_cache_step = 1,
+       .dapm_widgets = rt5640_dapm_widgets,
+       .num_dapm_widgets = ARRAY_SIZE(rt5640_dapm_widgets),
+       .dapm_routes = rt5640_dapm_routes,
+       .num_dapm_routes = ARRAY_SIZE(rt5640_dapm_routes),
+};
+
+static const struct i2c_device_id rt5640_i2c_id[] = {
+       { "rt5640", 0 },
+       { }
+};
+MODULE_DEVICE_TABLE(i2c, rt5640_i2c_id);
+
+static int rt5640_i2c_probe(struct i2c_client *i2c,
+                   const struct i2c_device_id *id)
+{
+       struct rt5640_priv *rt5640;
+       int ret;
+
+       rt5640 = kzalloc(sizeof(struct rt5640_priv), GFP_KERNEL);
+       if (NULL == rt5640)
+               return -ENOMEM;
+
+       i2c_set_clientdata(i2c, rt5640);
+
+       ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5640,
+                       rt5640_dai, ARRAY_SIZE(rt5640_dai));
+       if (ret < 0)
+               kfree(rt5640);
+
+       return ret;
+}
+
+static __devexit int rt5640_i2c_remove(struct i2c_client *i2c)
+{
+       snd_soc_unregister_codec(&i2c->dev);
+       kfree(i2c_get_clientdata(i2c));
+       return 0;
+}
+
+struct i2c_driver rt5640_i2c_driver = {
+       .driver = {
+               .name = "rt5640",
+               .owner = THIS_MODULE,
+       },
+       .probe = rt5640_i2c_probe,
+       .remove   = __devexit_p(rt5640_i2c_remove),
+       .id_table = rt5640_i2c_id,
+};
+
+static int __init rt5640_modinit(void)
+{
+       return i2c_add_driver(&rt5640_i2c_driver);
+}
+module_init(rt5640_modinit);
+
+static void __exit rt5640_modexit(void)
+{
+       i2c_del_driver(&rt5640_i2c_driver);
+}
+module_exit(rt5640_modexit);
+
+MODULE_DESCRIPTION("ASoC RT5640 driver");
+MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/rt5640.h b/sound/soc/codecs/rt5640.h
new file mode 100644 (file)
index 0000000..ba9ac7f
--- /dev/null
@@ -0,0 +1,2094 @@
+/*
+ * rt5640.h  --  RT5640 ALSA SoC audio driver
+ *
+ * Copyright 2011 Realtek Microelectronics
+ * Author: Johnny Hsu <johnnyhsu@realtek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __RT5640_H__
+#define __RT5640_H__
+
+/* Info */
+#define RT5640_RESET                           0x00
+#define RT5640_VENDOR_ID                       0xfd
+#define RT5640_VENDOR_ID1                      0xfe
+#define RT5640_VENDOR_ID2                      0xff
+/*  I/O - Output */
+#define RT5640_SPK_VOL                         0x01
+#define RT5640_HP_VOL                          0x02
+#define RT5640_OUTPUT                          0x03
+#define RT5640_MONO_OUT                        0x04
+/* I/O - Input */
+#define RT5640_IN1_IN2                         0x0d
+#define RT5640_IN3_IN4                         0x0e
+#define RT5640_INL_INR_VOL                     0x0f
+/* I/O - ADC/DAC/DMIC */
+#define RT5640_DAC1_DIG_VOL                    0x19
+#define RT5640_DAC2_DIG_VOL                    0x1a
+#define RT5640_DAC2_CTRL                       0x1b
+#define RT5640_ADC_DIG_VOL                     0x1c
+#define RT5640_ADC_DATA                        0x1d
+#define RT5640_ADC_BST_VOL                     0x1e
+/* Mixer - D-D */
+#define RT5640_STO_ADC_MIXER                   0x27
+#define RT5640_MONO_ADC_MIXER                  0x28
+#define RT5640_AD_DA_MIXER                     0x29
+#define RT5640_STO_DAC_MIXER                   0x2a
+#define RT5640_MONO_DAC_MIXER                  0x2b
+#define RT5640_DIG_MIXER                       0x2c
+#define RT5640_DSP_PATH1                       0x2d
+#define RT5640_DSP_PATH2                       0x2e
+#define RT5640_DIG_INF_DATA                    0x2f
+/* Mixer - ADC */
+#define RT5640_REC_L1_MIXER                    0x3b
+#define RT5640_REC_L2_MIXER                    0x3c
+#define RT5640_REC_R1_MIXER                    0x3d
+#define RT5640_REC_R2_MIXER                    0x3e
+/* Mixer - DAC */
+#define RT5640_HPO_MIXER                       0x45
+#define RT5640_SPK_L_MIXER                     0x46
+#define RT5640_SPK_R_MIXER                     0x47
+#define RT5640_SPO_L_MIXER                     0x48
+#define RT5640_SPO_R_MIXER                     0x49
+#define RT5640_SPO_CLSD_RATIO                  0x4a
+#define RT5640_MONO_MIXER                      0x4c
+#define RT5640_OUT_L1_MIXER                    0x4d
+#define RT5640_OUT_L2_MIXER                    0x4e
+#define RT5640_OUT_L3_MIXER                    0x4f
+#define RT5640_OUT_R1_MIXER                    0x50
+#define RT5640_OUT_R2_MIXER                    0x51
+#define RT5640_OUT_R3_MIXER                    0x52
+#define RT5640_LOUT_MIXER                      0x53
+/* Power */
+#define RT5640_PWR_DIG1                        0x61
+#define RT5640_PWR_DIG2                        0x62
+#define RT5640_PWR_ANLG1                       0x63
+#define RT5640_PWR_ANLG2                       0x64
+#define RT5640_PWR_MIXER                       0x65
+#define RT5640_PWR_VOL                         0x66
+/* Private Register Control */
+#define RT5640_PRIV_INDEX                      0x6a
+#define RT5640_PRIV_DATA                       0x6c
+/* Format - ADC/DAC */
+#define RT5640_I2S1_SDP                                0x70
+#define RT5640_I2S2_SDP                                0x71
+#define RT5640_I2S3_SDP                                0x72
+#define RT5640_ADDA_CLK1                       0x73
+#define RT5640_ADDA_CLK2                       0x74
+#define RT5640_DMIC                            0x75
+/* Function - Analog */
+#define RT5640_GLB_CLK                         0x80
+#define RT5640_PLL_CTRL1                       0x81
+#define RT5640_PLL_CTRL2                       0x82
+#define RT5640_ASRC_1                          0x83
+#define RT5640_ASRC_2                          0x84
+#define RT5640_ASRC_3                          0x85
+#define RT5640_ASRC_4                          0x89
+#define RT5640_ASRC_5                          0x8a
+#define RT5640_HP_OVCD                         0x8b
+#define RT5640_CLS_D_OVCD                      0x8c
+#define RT5640_CLS_D_OUT                       0x8d
+#define RT5640_DEPOP_M1                        0x8e
+#define RT5640_DEPOP_M2                        0x8f
+#define RT5640_DEPOP_M3                        0x90
+#define RT5640_CHARGE_PUMP                     0x91
+#define RT5640_PV_DET_SPK_G                    0x92
+#define RT5640_MICBIAS                         0x93
+/* Function - Digital */
+#define RT5640_EQ_CTRL1                                0xb0
+#define RT5640_EQ_CTRL2                                0xb1
+#define RT5640_WIND_FILTER                     0xb2
+#define RT5640_DRC_AGC_1                       0xb4
+#define RT5640_DRC_AGC_2                       0xb5
+#define RT5640_DRC_AGC_3                       0xb6
+#define RT5640_SVOL_ZC                         0xb7
+#define RT5640_ANC_CTRL1                       0xb8
+#define RT5640_ANC_CTRL2                       0xb9
+#define RT5640_ANC_CTRL3                       0xba
+#define RT5640_JD_CTRL                         0xbb
+#define RT5640_ANC_JD                          0xbc
+#define RT5640_IRQ_CTRL1                       0xbd
+#define RT5640_IRQ_CTRL2                       0xbe
+#define RT5640_INT_IRQ_ST                      0xbf
+#define RT5640_GPIO_CTRL1                      0xc0
+#define RT5640_GPIO_CTRL2                      0xc1
+#define RT5640_GPIO_CTRL3                      0xc2
+#define RT5640_DSP_CTRL1                       0xc4
+#define RT5640_DSP_CTRL2                       0xc5
+#define RT5640_DSP_CTRL3                       0xc6
+#define RT5640_DSP_CTRL4                       0xc7
+#define RT5640_PGM_REG_ARR1                    0xc8
+#define RT5640_PGM_REG_ARR2                    0xc9
+#define RT5640_PGM_REG_ARR3                    0xca
+#define RT5640_PGM_REG_ARR4                    0xcb
+#define RT5640_PGM_REG_ARR5                    0xcc
+#define RT5640_SCB_FUNC                        0xcd
+#define RT5640_SCB_CTRL                                0xce
+#define RT5640_BASE_BACK                       0xcf
+#define RT5640_MP3_PLUS1                       0xd0
+#define RT5640_MP3_PLUS2                       0xd1
+#define RT5640_3D_HP                           0xd2
+#define RT5640_ADJ_HPF                         0xd3
+#define RT5640_HP_CALIB_AMP_DET                0xd6
+#define RT5640_HP_CALIB2                       0xd7
+#define RT5640_SV_ZCD1                         0xd9
+#define RT5640_SV_ZCD2                         0xda
+/* Dummy Register */
+#define RT5640_DUMMY1                          0xfa
+#define RT5640_DUMMY2                          0xfb
+#define RT5640_DUMMY3                          0xfc
+
+
+/* Index of Codec Private Register definition */
+#define RT5640_3D_SPK                          0x63
+#define RT5640_WND_1                           0x6c
+#define RT5640_WND_2                           0x6d
+#define RT5640_WND_3                           0x6e
+#define RT5640_WND_4                           0x6f
+#define RT5640_WND_5                           0x70
+#define RT5640_WND_8                           0x73
+#define RT5640_DIP_SPK_INF                     0x75
+#define RT5640_EQ_BW_LOP                       0xa0
+#define RT5640_EQ_GN_LOP                       0xa1
+#define RT5640_EQ_FC_BP1                       0xa2
+#define RT5640_EQ_BW_BP1                       0xa3
+#define RT5640_EQ_GN_BP1                       0xa4
+#define RT5640_EQ_FC_BP2                       0xa5
+#define RT5640_EQ_BW_BP2                       0xa6
+#define RT5640_EQ_GN_BP2                       0xa7
+#define RT5640_EQ_FC_BP3                       0xa8
+#define RT5640_EQ_BW_BP3                       0xa9
+#define RT5640_EQ_GN_BP3                       0xaa
+#define RT5640_EQ_FC_BP4                       0xab
+#define RT5640_EQ_BW_BP4                       0xac
+#define RT5640_EQ_GN_BP4                       0xad
+#define RT5640_EQ_FC_HIP1                      0xae
+#define RT5640_EQ_GN_HIP1                      0xaf
+#define RT5640_EQ_FC_HIP2                      0xb0
+#define RT5640_EQ_BW_HIP2                      0xb1
+#define RT5640_EQ_GN_HIP2                      0xb2
+#define RT5640_EQ_PRE_VOL                      0xb3
+#define RT5640_EQ_PST_VOL                      0xb4
+
+
+/* global definition */
+#define RT5640_L_MUTE                          (0x1 << 15)
+#define RT5640_L_MUTE_SFT                      15
+#define RT5640_VOL_L_MUTE                      (0x1 << 14)
+#define RT5640_VOL_L_SFT                       14
+#define RT5640_R_MUTE                          (0x1 << 7)
+#define RT5640_R_MUTE_SFT                      7
+#define RT5640_VOL_R_MUTE                      (0x1 << 6)
+#define RT5640_VOL_R_SFT                       6
+#define RT5640_L_VOL_MASK                      (0x3f << 8)
+#define RT5640_L_VOL_SFT                       8
+#define RT5640_R_VOL_MASK                      (0x3f)
+#define RT5640_R_VOL_SFT                       0
+
+/* IN1 and IN2 Control (0x0d) */
+/* IN3 and IN4 Control (0x0e) */
+#define RT5640_BST_SFT1                                12
+#define RT5640_BST_SFT2                                8
+#define RT5640_IN_DF1                          (0x1 << 7)
+#define RT5640_IN_SFT1                         7
+#define RT5640_IN_DF2                          (0x1 << 6)
+#define RT5640_IN_SFT2                         6
+
+/* INL and INR Volume Control (0x0f) */
+#define RT5640_INL_SEL_MASK                    (0x1 << 15)
+#define RT5640_INL_SEL_SFT                     15
+#define RT5640_INL_SEL_IN4P                    (0x0 << 15)
+#define RT5640_INL_SEL_MONOP                   (0x1 << 15)
+#define RT5640_INL_VOL_MASK                    (0x1f << 8)
+#define RT5640_INL_VOL_SFT                     8
+#define RT5640_INR_SEL_MASK                    (0x1 << 7)
+#define RT5640_INR_SEL_SFT                     7
+#define RT5640_INR_SEL_IN4N                    (0x0 << 7)
+#define RT5640_INR_SEL_MONON                   (0x1 << 7)
+#define RT5640_INR_VOL_MASK                    (0x1f)
+#define RT5640_INR_VOL_SFT                     0
+
+/* DAC1 Digital Volume (0x19) */
+#define RT5640_DAC_L1_VOL_MASK         (0xff << 8)
+#define RT5640_DAC_L1_VOL_SFT                  8
+#define RT5640_DAC_R1_VOL_MASK         (0xff)
+#define RT5640_DAC_R1_VOL_SFT                  0
+
+/* DAC2 Digital Volume (0x1a) */
+#define RT5640_DAC_L2_VOL_MASK         (0xff << 8)
+#define RT5640_DAC_L2_VOL_SFT                  8
+#define RT5640_DAC_R2_VOL_MASK         (0xff)
+#define RT5640_DAC_R2_VOL_SFT                  0
+
+/* DAC2 Control (0x1b) */
+#define RT5640_M_DAC_L2_VOL                    (0x1 << 13)
+#define RT5640_M_DAC_L2_VOL_SFT                13
+#define RT5640_M_DAC_R2_VOL                    (0x1 << 12)
+#define RT5640_M_DAC_R2_VOL_SFT                12
+
+/* ADC Digital Volume Control (0x1c) */
+#define RT5640_ADC_L_VOL_MASK                  (0x7f << 8)
+#define RT5640_ADC_L_VOL_SFT                   8
+#define RT5640_ADC_R_VOL_MASK                  (0x7f)
+#define RT5640_ADC_R_VOL_SFT                   0
+
+/* Mono ADC Digital Volume Control (0x1d) */
+#define RT5640_MONO_ADC_L_VOL_MASK             (0x7f << 8)
+#define RT5640_MONO_ADC_L_VOL_SFT              8
+#define RT5640_MONO_ADC_R_VOL_MASK             (0x7f)
+#define RT5640_MONO_ADC_R_VOL_SFT              0
+
+/* ADC Boost Volume Control (0x1e) */
+#define RT5640_ADC_L_BST_MASK                  (0x3 << 14)
+#define RT5640_ADC_L_BST_SFT                   14
+#define RT5640_ADC_R_BST_MASK                  (0x3 << 12)
+#define RT5640_ADC_R_BST_SFT                   12
+#define RT5640_ADC_COMP_MASK                   (0x3 << 10)
+#define RT5640_ADC_COMP_SFT                    10
+
+/* Stereo ADC Mixer Control (0x27) */
+#define RT5640_M_ADC_L1                        (0x1 << 14)
+#define RT5640_M_ADC_L1_SFT                    14
+#define RT5640_M_ADC_L2                        (0x1 << 13)
+#define RT5640_M_ADC_L2_SFT                    13
+#define RT5640_ADC_1_SRC_MASK                  (0x1 << 12)
+#define RT5640_ADC_1_SRC_SFT                   12
+#define RT5640_ADC_1_SRC_ADC                   (0x1 << 12)
+#define RT5640_ADC_1_SRC_DACMIX                (0x0 << 12)
+#define RT5640_ADC_2_SRC_MASK                  (0x3 << 10)
+#define RT5640_ADC_2_SRC_SFT                   10
+#define RT5640_ADC_2_SRC_DMIC1         (0x0 << 10)
+#define RT5640_ADC_2_SRC_DMIC2         (0x1 << 10)
+#define RT5640_ADC_2_SRC_DACMIX                (0x2 << 10)
+#define RT5640_M_ADC_R1                        (0x1 << 6)
+#define RT5640_M_ADC_R1_SFT                    6
+#define RT5640_M_ADC_R2                        (0x1 << 5)
+#define RT5640_M_ADC_R2_SFT                    5
+
+/* Mono ADC Mixer Control (0x28) */
+#define RT5640_M_MONO_ADC_L1                   (0x1 << 14)
+#define RT5640_M_MONO_ADC_L1_SFT               14
+#define RT5640_M_MONO_ADC_L2                   (0x1 << 13)
+#define RT5640_M_MONO_ADC_L2_SFT               13
+#define RT5640_MONO_ADC_L1_SRC_MASK            (0x1 << 12)
+#define RT5640_MONO_ADC_L1_SRC_SFT             12
+#define RT5640_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
+#define RT5640_MONO_ADC_L1_SRC_ADCL            (0x1 << 12)
+#define RT5640_MONO_ADC_L2_SRC_MASK            (0x3 << 10)
+#define RT5640_MONO_ADC_L2_SRC_SFT             10
+#define RT5640_MONO_ADC_L2_SRC_DMIC_L1 (0x0 << 10)
+#define RT5640_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10)
+#define RT5640_MONO_ADC_L2_SRC_DACMIXL (0x2 << 10)
+#define RT5640_M_MONO_ADC_R1                   (0x1 << 6)
+#define RT5640_M_MONO_ADC_R1_SFT               6
+#define RT5640_M_MONO_ADC_R2                   (0x1 << 5)
+#define RT5640_M_MONO_ADC_R2_SFT               5
+#define RT5640_MONO_ADC_R1_SRC_MASK            (0x1 << 4)
+#define RT5640_MONO_ADC_R1_SRC_SFT             4
+#define RT5640_MONO_ADC_R1_SRC_ADCR            (0x1 << 4)
+#define RT5640_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
+#define RT5640_MONO_ADC_R2_SRC_MASK            (0x3 << 2)
+#define RT5640_MONO_ADC_R2_SRC_SFT             2
+#define RT5640_MONO_ADC_R2_SRC_DMIC_R1 (0x0 << 2)
+#define RT5640_MONO_ADC_R2_SRC_DMIC_R2 (0x1 << 2)
+#define RT5640_MONO_ADC_R2_SRC_DACMIXR (0x2 << 2)
+
+/* ADC Mixer to DAC Mixer Control (0x29) */
+#define RT5640_M_ADCMIX_L                      (0x1 << 15)
+#define RT5640_M_ADCMIX_L_SFT                  15
+#define RT5640_M_IF1_DAC_L                     (0x1 << 14)
+#define RT5640_M_IF1_DAC_L_SFT                 14
+#define RT5640_M_ADCMIX_R                      (0x1 << 7)
+#define RT5640_M_ADCMIX_R_SFT                  7
+#define RT5640_M_IF1_DAC_R                     (0x1 << 6)
+#define RT5640_M_IF1_DAC_R_SFT                 6
+
+/* Stereo DAC Mixer Control (0x2a) */
+#define RT5640_M_DAC_L1                        (0x1 << 14)
+#define RT5640_M_DAC_L1_SFT                    14
+#define RT5640_DAC_L1_STO_L_VOL_MASK           (0x1 << 13)
+#define RT5640_DAC_L1_STO_L_VOL_SFT            13
+#define RT5640_M_DAC_L2                        (0x1 << 12)
+#define RT5640_M_DAC_L2_SFT                    12
+#define RT5640_DAC_L2_STO_L_VOL_MASK           (0x1 << 11)
+#define RT5640_DAC_L2_STO_L_VOL_SFT            11
+#define RT5640_M_ANC_DAC_L                     (0x1 << 10)
+#define RT5640_M_ANC_DAC_L_SFT         10
+#define RT5640_M_DAC_R1                        (0x1 << 6)
+#define RT5640_M_DAC_R1_SFT                    6
+#define RT5640_DAC_R1_STO_R_VOL_MASK           (0x1 << 5)
+#define RT5640_DAC_R1_STO_R_VOL_SFT            5
+#define RT5640_M_DAC_R2                        (0x1 << 4)
+#define RT5640_M_DAC_R2_SFT                    4
+#define RT5640_DAC_R2_STO_R_VOL_MASK           (0x1 << 3)
+#define RT5640_DAC_R2_STO_R_VOL_SFT            3
+#define RT5640_M_ANC_DAC_R                     (0x1 << 2)
+#define RT5640_M_ANC_DAC_R_SFT         2
+
+/* Mono DAC Mixer Control (0x2b) */
+#define RT5640_M_DAC_L1_MONO_L         (0x1 << 14)
+#define RT5640_M_DAC_L1_MONO_L_SFT             14
+#define RT5640_DAC_L1_MONO_L_VOL_MASK  (0x1 << 13)
+#define RT5640_DAC_L1_MONO_L_VOL_SFT           13
+#define RT5640_M_DAC_L2_MONO_L         (0x1 << 12)
+#define RT5640_M_DAC_L2_MONO_L_SFT             12
+#define RT5640_DAC_L2_MONO_L_VOL_MASK  (0x1 << 11)
+#define RT5640_DAC_L2_MONO_L_VOL_SFT           11
+#define RT5640_M_DAC_R2_MONO_L         (0x1 << 10)
+#define RT5640_M_DAC_R2_MONO_L_SFT             10
+#define RT5640_DAC_R2_MONO_L_VOL_MASK  (0x1 << 9)
+#define RT5640_DAC_R2_MONO_L_VOL_SFT           9
+#define RT5640_M_DAC_R1_MONO_R         (0x1 << 6)
+#define RT5640_M_DAC_R1_MONO_R_SFT             6
+#define RT5640_DAC_R1_MONO_R_VOL_MASK  (0x1 << 5)
+#define RT5640_DAC_R1_MONO_R_VOL_SFT           5
+#define RT5640_M_DAC_R2_MONO_R         (0x1 << 4)
+#define RT5640_M_DAC_R2_MONO_R_SFT             4
+#define RT5640_DAC_R2_MONO_R_VOL_MASK  (0x1 << 3)
+#define RT5640_DAC_R2_MONO_R_VOL_SFT           3
+#define RT5640_M_DAC_L2_MONO_R         (0x1 << 2)
+#define RT5640_M_DAC_L2_MONO_R_SFT             2
+#define RT5640_DAC_L2_MONO_R_VOL_MASK  (0x1 << 1)
+#define RT5640_DAC_L2_MONO_R_VOL_SFT           1
+
+/* Digital Mixer Control (0x2c) */
+#define RT5640_M_STO_L_DAC_L                   (0x1 << 15)
+#define RT5640_M_STO_L_DAC_L_SFT               15
+#define RT5640_STO_L_DAC_L_VOL_MASK            (0x1 << 14)
+#define RT5640_STO_L_DAC_L_VOL_SFT             14
+#define RT5640_M_DAC_L2_DAC_L                  (0x1 << 13)
+#define RT5640_M_DAC_L2_DAC_L_SFT              13
+#define RT5640_DAC_L2_DAC_L_VOL_MASK           (0x1 << 12)
+#define RT5640_DAC_L2_DAC_L_VOL_SFT            12
+#define RT5640_M_STO_R_DAC_R                   (0x1 << 11)
+#define RT5640_M_STO_R_DAC_R_SFT               11
+#define RT5640_STO_R_DAC_R_VOL_MASK            (0x1 << 10)
+#define RT5640_STO_R_DAC_R_VOL_SFT             10
+#define RT5640_M_DAC_R2_DAC_R                  (0x1 << 9)
+#define RT5640_M_DAC_R2_DAC_R_SFT              9
+#define RT5640_DAC_R2_DAC_R_VOL_MASK           (0x1 << 8)
+#define RT5640_DAC_R2_DAC_R_VOL_SFT            8
+
+/* DSP Path Control 1 (0x2d) */
+#define RT5640_RXDP_SRC_MASK                   (0x1 << 15)
+#define RT5640_RXDP_SRC_SFT                    15
+#define RT5640_RXDP_SRC_NOR                    (0x0 << 15)
+#define RT5640_RXDP_SRC_DIV3                   (0x1 << 15)
+#define RT5640_TXDP_SRC_MASK                   (0x1 << 14)
+#define RT5640_TXDP_SRC_SFT                    14
+#define RT5640_TXDP_SRC_NOR                    (0x0 << 14)
+#define RT5640_TXDP_SRC_DIV3                   (0x1 << 14)
+
+/* DSP Path Control 2 (0x2e) */
+#define RT5640_DAC_L2_SEL_MASK         (0x3 << 14)
+#define RT5640_DAC_L2_SEL_SFT                  14
+#define RT5640_DAC_L2_SEL_IF2                  (0x0 << 14)
+#define RT5640_DAC_L2_SEL_IF3                  (0x1 << 14)
+#define RT5640_DAC_L2_SEL_TXDC                 (0x2 << 14)
+#define RT5640_DAC_L2_SEL_BASS                 (0x3 << 14)
+#define RT5640_DAC_R2_SEL_MASK         (0x3 << 12)
+#define RT5640_DAC_R2_SEL_SFT                  12
+#define RT5640_DAC_R2_SEL_IF2                  (0x0 << 12)
+#define RT5640_DAC_R2_SEL_IF3                  (0x1 << 12)
+#define RT5640_DAC_R2_SEL_TXDC         (0x2 << 12)
+#define RT5640_IF2_ADC_L_SEL_MASK              (0x1 << 11)
+#define RT5640_IF2_ADC_L_SEL_SFT               11
+#define RT5640_IF2_ADC_L_SEL_TXDP              (0x0 << 11)
+#define RT5640_IF2_ADC_L_SEL_PASS              (0x1 << 11)
+#define RT5640_IF2_ADC_R_SEL_MASK              (0x1 << 10)
+#define RT5640_IF2_ADC_R_SEL_SFT               10
+#define RT5640_IF2_ADC_R_SEL_TXDP              (0x0 << 10)
+#define RT5640_IF2_ADC_R_SEL_PASS              (0x1 << 10)
+#define RT5640_RXDC_SEL_MASK                   (0x3 << 8)
+#define RT5640_RXDC_SEL_SFT                    8
+#define RT5640_RXDC_SEL_NOR                    (0x0 << 8)
+#define RT5640_RXDC_SEL_L2R                    (0x1 << 8)
+#define RT5640_RXDC_SEL_R2L                    (0x2 << 8)
+#define RT5640_RXDC_SEL_SWAP                   (0x3 << 8)
+#define RT5640_RXDP_SEL_MASK                   (0x3 << 6)
+#define RT5640_RXDP_SEL_SFT                    6
+#define RT5640_RXDP_SEL_NOR                    (0x0 << 6)
+#define RT5640_RXDP_SEL_L2R                    (0x1 << 6)
+#define RT5640_RXDP_SEL_R2L                    (0x2 << 6)
+#define RT5640_RXDP_SEL_SWAP                   (0x3 << 6)
+#define RT5640_TXDC_SEL_MASK                   (0x3 << 4)
+#define RT5640_TXDC_SEL_SFT                    4
+#define RT5640_TXDC_SEL_NOR                    (0x0 << 4)
+#define RT5640_TXDC_SEL_L2R                    (0x1 << 4)
+#define RT5640_TXDC_SEL_R2L                    (0x2 << 4)
+#define RT5640_TXDC_SEL_SWAP                   (0x3 << 4)
+#define RT5640_TXDP_SEL_MASK                   (0x3 << 2)
+#define RT5640_TXDP_SEL_SFT                    2
+#define RT5640_TXDP_SEL_NOR                    (0x0 << 2)
+#define RT5640_TXDP_SEL_L2R                    (0x1 << 2)
+#define RT5640_TXDP_SEL_R2L                    (0x2 << 2)
+#define RT5640_TRXDP_SEL_SWAP                  (0x3 << 2)
+
+/* Digital Interface Data Control (0x2f) */
+#define RT5640_IF1_DAC_SEL_MASK                (0x3 << 14)
+#define RT5640_IF1_DAC_SEL_SFT                 14
+#define RT5640_IF1_DAC_SEL_NOR                 (0x0 << 14)
+#define RT5640_IF1_DAC_SEL_L2R                 (0x1 << 14)
+#define RT5640_IF1_DAC_SEL_R2L                 (0x2 << 14)
+#define RT5640_IF1_DAC_SEL_SWAP                (0x3 << 14)
+#define RT5640_IF1_ADC_SEL_MASK                (0x3 << 12)
+#define RT5640_IF1_ADC_SEL_SFT                 12
+#define RT5640_IF1_ADC_SEL_NOR                 (0x0 << 12)
+#define RT5640_IF1_ADC_SEL_L2R                 (0x1 << 12)
+#define RT5640_IF1_ADC_SEL_R2L                 (0x2 << 12)
+#define RT5640_IF1_ADC_SEL_SWAP                (0x3 << 12)
+#define RT5640_IF2_DAC_SEL_MASK                (0x3 << 10)
+#define RT5640_IF2_DAC_SEL_SFT                 10
+#define RT5640_IF2_DAC_SEL_NOR                 (0x0 << 10)
+#define RT5640_IF2_DAC_SEL_L2R                 (0x1 << 10)
+#define RT5640_IF2_DAC_SEL_R2L                 (0x2 << 10)
+#define RT5640_IF2_DAC_SEL_SWAP                (0x3 << 10)
+#define RT5640_IF2_ADC_SEL_MASK                (0x3 << 8)
+#define RT5640_IF2_ADC_SEL_SFT                 8
+#define RT5640_IF2_ADC_SEL_NOR                 (0x0 << 8)
+#define RT5640_IF2_ADC_SEL_L2R                 (0x1 << 8)
+#define RT5640_IF2_ADC_SEL_R2L                 (0x2 << 8)
+#define RT5640_IF2_ADC_SEL_SWAP                (0x3 << 8)
+#define RT5640_IF3_DAC_SEL_MASK                (0x3 << 6)
+#define RT5640_IF3_DAC_SEL_SFT                 6
+#define RT5640_IF3_DAC_SEL_NOR                 (0x0 << 6)
+#define RT5640_IF3_DAC_SEL_L2R                 (0x1 << 6)
+#define RT5640_IF3_DAC_SEL_R2L                 (0x2 << 6)
+#define RT5640_IF3_DAC_SEL_SWAP                (0x3 << 6)
+#define RT5640_IF3_ADC_SEL_MASK                (0x3 << 4)
+#define RT5640_IF3_ADC_SEL_SFT                 4
+#define RT5640_IF3_ADC_SEL_NOR                 (0x0 << 4)
+#define RT5640_IF3_ADC_SEL_L2R                 (0x1 << 4)
+#define RT5640_IF3_ADC_SEL_R2L                 (0x2 << 4)
+#define RT5640_IF3_ADC_SEL_SWAP                (0x3 << 4)
+
+/* REC Left Mixer Control 1 (0x3b) */
+#define RT5640_G_HP_L_RM_L_MASK                (0x7 << 13)
+#define RT5640_G_HP_L_RM_L_SFT                 13
+#define RT5640_G_IN_L_RM_L_MASK                (0x7 << 10)
+#define RT5640_G_IN_L_RM_L_SFT                 10
+#define RT5640_G_BST4_RM_L_MASK                (0x7 << 7)
+#define RT5640_G_BST4_RM_L_SFT                 7
+#define RT5640_G_BST3_RM_L_MASK                (0x7 << 4)
+#define RT5640_G_BST3_RM_L_SFT                 4
+#define RT5640_G_BST2_RM_L_MASK                (0x7 << 1)
+#define RT5640_G_BST2_RM_L_SFT                 1
+
+/* REC Left Mixer Control 2 (0x3c) */
+#define RT5640_G_BST1_RM_L_MASK                (0x7 << 13)
+#define RT5640_G_BST1_RM_L_SFT                 13
+#define RT5640_G_OM_L_RM_L_MASK                (0x7 << 10)
+#define RT5640_G_OM_L_RM_L_SFT         10
+#define RT5640_M_HP_L_RM_L                     (0x1 << 6)
+#define RT5640_M_HP_L_RM_L_SFT         6
+#define RT5640_M_IN_L_RM_L                     (0x1 << 5)
+#define RT5640_M_IN_L_RM_L_SFT                 5
+#define RT5640_M_BST4_RM_L                     (0x1 << 4)
+#define RT5640_M_BST4_RM_L_SFT         4
+#define RT5640_M_BST3_RM_L                     (0x1 << 3)
+#define RT5640_M_BST3_RM_L_SFT         3
+#define RT5640_M_BST2_RM_L                     (0x1 << 2)
+#define RT5640_M_BST2_RM_L_SFT         2
+#define RT5640_M_BST1_RM_L                     (0x1 << 1)
+#define RT5640_M_BST1_RM_L_SFT         1
+#define RT5640_M_OM_L_RM_L                     (0x1)
+#define RT5640_M_OM_L_RM_L_SFT         0
+
+/* REC Right Mixer Control 1 (0x3d) */
+#define RT5640_G_HP_R_RM_R_MASK                (0x7 << 13)
+#define RT5640_G_HP_R_RM_R_SFT         13
+#define RT5640_G_IN_R_RM_R_MASK                (0x7 << 10)
+#define RT5640_G_IN_R_RM_R_SFT                 10
+#define RT5640_G_BST4_RM_R_MASK                (0x7 << 7)
+#define RT5640_G_BST4_RM_R_SFT                 7
+#define RT5640_G_BST3_RM_R_MASK                (0x7 << 4)
+#define RT5640_G_BST3_RM_R_SFT                 4
+#define RT5640_G_BST2_RM_R_MASK                (0x7 << 1)
+#define RT5640_G_BST2_RM_R_SFT                 1
+
+/* REC Right Mixer Control 2 (0x3e) */
+#define RT5640_G_BST1_RM_R_MASK                (0x7 << 13)
+#define RT5640_G_BST1_RM_R_SFT                 13
+#define RT5640_G_OM_R_RM_R_MASK                (0x7 << 10)
+#define RT5640_G_OM_R_RM_R_SFT         10
+#define RT5640_M_HP_R_RM_R                     (0x1 << 6)
+#define RT5640_M_HP_R_RM_R_SFT         6
+#define RT5640_M_IN_R_RM_R                     (0x1 << 5)
+#define RT5640_M_IN_R_RM_R_SFT                 5
+#define RT5640_M_BST4_RM_R                     (0x1 << 4)
+#define RT5640_M_BST4_RM_R_SFT         4
+#define RT5640_M_BST3_RM_R                     (0x1 << 3)
+#define RT5640_M_BST3_RM_R_SFT         3
+#define RT5640_M_BST2_RM_R                     (0x1 << 2)
+#define RT5640_M_BST2_RM_R_SFT         2
+#define RT5640_M_BST1_RM_R                     (0x1 << 1)
+#define RT5640_M_BST1_RM_R_SFT         1
+#define RT5640_M_OM_R_RM_R                     (0x1)
+#define RT5640_M_OM_R_RM_R_SFT         0
+
+/* HPMIX Control (0x45) */
+#define RT5640_M_DAC2_HM                       (0x1 << 15)
+#define RT5640_M_DAC2_HM_SFT                   15
+#define RT5640_M_DAC1_HM                       (0x1 << 14)
+#define RT5640_M_DAC1_HM_SFT                   14
+#define RT5640_M_HPVOL_HM                      (0x1 << 13)
+#define RT5640_M_HPVOL_HM_SFT                  13
+#define RT5640_G_HPOMIX_MASK                   (0x1 << 12)
+#define RT5640_G_HPOMIX_SFT                    12
+
+/* SPK Left Mixer Control (0x46) */
+#define RT5640_G_RM_L_SM_L_MASK                (0x3 << 14)
+#define RT5640_G_RM_L_SM_L_SFT         14
+#define RT5640_G_IN_L_SM_L_MASK                (0x3 << 12)
+#define RT5640_G_IN_L_SM_L_SFT                 12
+#define RT5640_G_DAC_L1_SM_L_MASK              (0x3 << 10)
+#define RT5640_G_DAC_L1_SM_L_SFT               10
+#define RT5640_G_DAC_L2_SM_L_MASK              (0x3 << 8)
+#define RT5640_G_DAC_L2_SM_L_SFT               8
+#define RT5640_G_OM_L_SM_L_MASK                (0x3 << 6)
+#define RT5640_G_OM_L_SM_L_SFT         6
+#define RT5640_M_RM_L_SM_L                     (0x1 << 5)
+#define RT5640_M_RM_L_SM_L_SFT         5
+#define RT5640_M_IN_L_SM_L                     (0x1 << 4)
+#define RT5640_M_IN_L_SM_L_SFT                 4
+#define RT5640_M_DAC_L1_SM_L                   (0x1 << 3)
+#define RT5640_M_DAC_L1_SM_L_SFT               3
+#define RT5640_M_DAC_L2_SM_L                   (0x1 << 2)
+#define RT5640_M_DAC_L2_SM_L_SFT               2
+#define RT5640_M_OM_L_SM_L                     (0x1 << 1)
+#define RT5640_M_OM_L_SM_L_SFT         1
+
+/* SPK Right Mixer Control (0x47) */
+#define RT5640_G_RM_R_SM_R_MASK                (0x3 << 14)
+#define RT5640_G_RM_R_SM_R_SFT         14
+#define RT5640_G_IN_R_SM_R_MASK                (0x3 << 12)
+#define RT5640_G_IN_R_SM_R_SFT                 12
+#define RT5640_G_DAC_R1_SM_R_MASK              (0x3 << 10)
+#define RT5640_G_DAC_R1_SM_R_SFT               10
+#define RT5640_G_DAC_R2_SM_R_MASK              (0x3 << 8)
+#define RT5640_G_DAC_R2_SM_R_SFT               8
+#define RT5640_G_OM_R_SM_R_MASK                (0x3 << 6)
+#define RT5640_G_OM_R_SM_R_SFT         6
+#define RT5640_M_RM_R_SM_R                     (0x1 << 5)
+#define RT5640_M_RM_R_SM_R_SFT         5
+#define RT5640_M_IN_R_SM_R                     (0x1 << 4)
+#define RT5640_M_IN_R_SM_R_SFT                 4
+#define RT5640_M_DAC_R1_SM_R                   (0x1 << 3)
+#define RT5640_M_DAC_R1_SM_R_SFT               3
+#define RT5640_M_DAC_R2_SM_R                   (0x1 << 2)
+#define RT5640_M_DAC_R2_SM_R_SFT               2
+#define RT5640_M_OM_R_SM_R                     (0x1 << 1)
+#define RT5640_M_OM_R_SM_R_SFT         1
+
+/* SPOLMIX Control (0x48) */
+#define RT5640_M_DAC_R1_SPM_L                  (0x1 << 15)
+#define RT5640_M_DAC_R1_SPM_L_SFT              15
+#define RT5640_M_DAC_L1_SPM_L                  (0x1 << 14)
+#define RT5640_M_DAC_L1_SPM_L_SFT              14
+#define RT5640_M_SV_R_SPM_L                    (0x1 << 13)
+#define RT5640_M_SV_R_SPM_L_SFT                13
+#define RT5640_M_SV_L_SPM_L                    (0x1 << 12)
+#define RT5640_M_SV_L_SPM_L_SFT                12
+#define RT5640_M_BST1_SPM_L                    (0x1 << 11)
+#define RT5640_M_BST1_SPM_L_SFT                11
+
+/* SPORMIX Control (0x49) */
+#define RT5640_M_DAC_R1_SPM_R                  (0x1 << 13)
+#define RT5640_M_DAC_R1_SPM_R_SFT              13
+#define RT5640_M_SV_R_SPM_R                    (0x1 << 12)
+#define RT5640_M_SV_R_SPM_R_SFT                12
+#define RT5640_M_BST1_SPM_R                    (0x1 << 11)
+#define RT5640_M_BST1_SPM_R_SFT                11
+
+/* SPOLMIX / SPORMIX Ratio Control (0x4a) */
+#define RT5640_SPO_CLSD_RATIO_MASK             (0x7)
+#define RT5640_SPO_CLSD_RATIO_SFT              0
+
+/* Mono Output Mixer Control (0x4c) */
+#define RT5640_M_DAC_R2_MM                     (0x1 << 15)
+#define RT5640_M_DAC_R2_MM_SFT         15
+#define RT5640_M_DAC_L2_MM                     (0x1 << 14)
+#define RT5640_M_DAC_L2_MM_SFT         14
+#define RT5640_M_OV_R_MM                       (0x1 << 13)
+#define RT5640_M_OV_R_MM_SFT                   13
+#define RT5640_M_OV_L_MM                       (0x1 << 12)
+#define RT5640_M_OV_L_MM_SFT                   12
+#define RT5640_M_BST1_MM                       (0x1 << 11)
+#define RT5640_M_BST1_MM_SFT                   11
+#define RT5640_G_MONOMIX_MASK          (0x1 << 10)
+#define RT5640_G_MONOMIX_SFT                   10
+
+/* Output Left Mixer Control 1 (0x4d) */
+#define RT5640_G_BST3_OM_L_MASK                (0x7 << 13)
+#define RT5640_G_BST3_OM_L_SFT         13
+#define RT5640_G_BST2_OM_L_MASK                (0x7 << 10)
+#define RT5640_G_BST2_OM_L_SFT         10
+#define RT5640_G_BST1_OM_L_MASK                (0x7 << 7)
+#define RT5640_G_BST1_OM_L_SFT         7
+#define RT5640_G_IN_L_OM_L_MASK                (0x7 << 4)
+#define RT5640_G_IN_L_OM_L_SFT                 4
+#define RT5640_G_RM_L_OM_L_MASK                (0x7 << 1)
+#define RT5640_G_RM_L_OM_L_SFT         1
+
+/* Output Left Mixer Control 2 (0x4e) */
+#define RT5640_G_DAC_R2_OM_L_MASK              (0x7 << 13)
+#define RT5640_G_DAC_R2_OM_L_SFT               13
+#define RT5640_G_DAC_L2_OM_L_MASK              (0x7 << 10)
+#define RT5640_G_DAC_L2_OM_L_SFT               10
+#define RT5640_G_DAC_L1_OM_L_MASK              (0x7 << 7)
+#define RT5640_G_DAC_L1_OM_L_SFT               7
+
+/* Output Left Mixer Control 3 (0x4f) */
+#define RT5640_M_SM_L_OM_L                     (0x1 << 8)
+#define RT5640_M_SM_L_OM_L_SFT         8
+#define RT5640_M_BST3_OM_L                     (0x1 << 7)
+#define RT5640_M_BST3_OM_L_SFT         7
+#define RT5640_M_BST2_OM_L                     (0x1 << 6)
+#define RT5640_M_BST2_OM_L_SFT         6
+#define RT5640_M_BST1_OM_L                     (0x1 << 5)
+#define RT5640_M_BST1_OM_L_SFT         5
+#define RT5640_M_IN_L_OM_L                     (0x1 << 4)
+#define RT5640_M_IN_L_OM_L_SFT                 4
+#define RT5640_M_RM_L_OM_L                     (0x1 << 3)
+#define RT5640_M_RM_L_OM_L_SFT         3
+#define RT5640_M_DAC_R2_OM_L                   (0x1 << 2)
+#define RT5640_M_DAC_R2_OM_L_SFT               2
+#define RT5640_M_DAC_L2_OM_L                   (0x1 << 1)
+#define RT5640_M_DAC_L2_OM_L_SFT               1
+#define RT5640_M_DAC_L1_OM_L                   (0x1)
+#define RT5640_M_DAC_L1_OM_L_SFT               0
+
+/* Output Right Mixer Control 1 (0x50) */
+#define RT5640_G_BST4_OM_R_MASK                (0x7 << 13)
+#define RT5640_G_BST4_OM_R_SFT         13
+#define RT5640_G_BST2_OM_R_MASK                (0x7 << 10)
+#define RT5640_G_BST2_OM_R_SFT         10
+#define RT5640_G_BST1_OM_R_MASK                (0x7 << 7)
+#define RT5640_G_BST1_OM_R_SFT         7
+#define RT5640_G_IN_R_OM_R_MASK                (0x7 << 4)
+#define RT5640_G_IN_R_OM_R_SFT                 4
+#define RT5640_G_RM_R_OM_R_MASK                (0x7 << 1)
+#define RT5640_G_RM_R_OM_R_SFT         1
+
+/* Output Right Mixer Control 2 (0x51) */
+#define RT5640_G_DAC_L2_OM_R_MASK              (0x7 << 13)
+#define RT5640_G_DAC_L2_OM_R_SFT               13
+#define RT5640_G_DAC_R2_OM_R_MASK              (0x7 << 10)
+#define RT5640_G_DAC_R2_OM_R_SFT               10
+#define RT5640_G_DAC_R1_OM_R_MASK              (0x7 << 7)
+#define RT5640_G_DAC_R1_OM_R_SFT               7
+
+/* Output Right Mixer Control 3 (0x52) */
+#define RT5640_M_SM_L_OM_R                     (0x1 << 8)
+#define RT5640_M_SM_L_OM_R_SFT         8
+#define RT5640_M_BST4_OM_R                     (0x1 << 7)
+#define RT5640_M_BST4_OM_R_SFT         7
+#define RT5640_M_BST2_OM_R                     (0x1 << 6)
+#define RT5640_M_BST2_OM_R_SFT         6
+#define RT5640_M_BST1_OM_R                     (0x1 << 5)
+#define RT5640_M_BST1_OM_R_SFT         5
+#define RT5640_M_IN_R_OM_R                     (0x1 << 4)
+#define RT5640_M_IN_R_OM_R_SFT         4
+#define RT5640_M_RM_R_OM_R                     (0x1 << 3)
+#define RT5640_M_RM_R_OM_R_SFT         3
+#define RT5640_M_DAC_L2_OM_R                   (0x1 << 2)
+#define RT5640_M_DAC_L2_OM_R_SFT               2
+#define RT5640_M_DAC_R2_OM_R                   (0x1 << 1)
+#define RT5640_M_DAC_R2_OM_R_SFT               1
+#define RT5640_M_DAC_R1_OM_R                   (0x1)
+#define RT5640_M_DAC_R1_OM_R_SFT               0
+
+/* LOUT Mixer Control (0x53) */
+#define RT5640_M_DAC_L1_LM                     (0x1 << 15)
+#define RT5640_M_DAC_L1_LM_SFT         15
+#define RT5640_M_DAC_R1_LM                     (0x1 << 14)
+#define RT5640_M_DAC_R1_LM_SFT         14
+#define RT5640_M_OV_L_LM                       (0x1 << 13)
+#define RT5640_M_OV_L_LM_SFT                   13
+#define RT5640_M_OV_R_LM                       (0x1 << 12)
+#define RT5640_M_OV_R_LM_SFT                   12
+#define RT5640_G_LOUTMIX_MASK                  (0x1 << 11)
+#define RT5640_G_LOUTMIX_SFT                   11
+
+/* Power Management for Digital 1 (0x61) */
+#define RT5640_PWR_I2S1                                (0x1 << 15)
+#define RT5640_PWR_I2S1_BIT                    15
+#define RT5640_PWR_I2S2                                (0x1 << 14)
+#define RT5640_PWR_I2S2_BIT                    14
+#define RT5640_PWR_I2S3                                (0x1 << 13)
+#define RT5640_PWR_I2S3_BIT                    13
+#define RT5640_PWR_DAC_L1                      (0x1 << 12)
+#define RT5640_PWR_DAC_L1_BIT                  12
+#define RT5640_PWR_DAC_R1                      (0x1 << 11)
+#define RT5640_PWR_DAC_R1_BIT                  11
+#define RT5640_PWR_DAC_L2                      (0x1 << 7)
+#define RT5640_PWR_DAC_L2_BIT                  7
+#define RT5640_PWR_DAC_R2                      (0x1 << 6)
+#define RT5640_PWR_DAC_R2_BIT                  6
+#define RT5640_PWR_ADC_L                       (0x1 << 2)
+#define RT5640_PWR_ADC_L_BIT                   2
+#define RT5640_PWR_ADC_R                       (0x1 << 1)
+#define RT5640_PWR_ADC_R_BIT                   1
+#define RT5640_PWR_CLS_D                       (0x1)
+#define RT5640_PWR_CLS_D_BIT                   0
+
+/* Power Management for Digital 2 (0x62) */
+#define RT5640_PWR_ADC_SF                      (0x1 << 15)
+#define RT5640_PWR_ADC_SF_BIT                  15
+#define RT5640_PWR_ADC_MF_L                    (0x1 << 14)
+#define RT5640_PWR_ADC_MF_L_BIT                14
+#define RT5640_PWR_ADC_MF_R                    (0x1 << 13)
+#define RT5640_PWR_ADC_MF_R_BIT                13
+#define RT5640_PWR_I2S_DSP                     (0x1 << 12)
+#define RT5640_PWR_I2S_DSP_BIT                 12
+
+/* Power Management for Analog 1 (0x63) */
+#define RT5640_PWR_VREF1                       (0x1 << 15)
+#define RT5640_PWR_VREF1_BIT                   15
+#define RT5640_PWR_FV1                         (0x1 << 14)
+#define RT5640_PWR_FV1_BIT                     14
+#define RT5640_PWR_MB                          (0x1 << 13)
+#define RT5640_PWR_MB_BIT                      13
+#define RT5640_PWR_LM                          (0x1 << 12)
+#define RT5640_PWR_LM_BIT                      12
+#define RT5640_PWR_BG                          (0x1 << 11)
+#define RT5640_PWR_BG_BIT                      11
+#define RT5640_PWR_MM                          (0x1 << 10)
+#define RT5640_PWR_MM_BIT                      10
+#define RT5640_PWR_MA                          (0x1 << 8)
+#define RT5640_PWR_MA_BIT                      8
+#define RT5640_PWR_HP_L                        (0x1 << 7)
+#define RT5640_PWR_HP_L_BIT                    7
+#define RT5640_PWR_HP_R                        (0x1 << 6)
+#define RT5640_PWR_HP_R_BIT                    6
+#define RT5640_PWR_HA                          (0x1 << 5)
+#define RT5640_PWR_HA_BIT                      5
+#define RT5640_PWR_VREF2                       (0x1 << 4)
+#define RT5640_PWR_VREF2_BIT                   4
+#define RT5640_PWR_FV2                         (0x1 << 3)
+#define RT5640_PWR_FV2_BIT                     3
+#define RT5640_PWR_LDO2                        (0x1 << 2)
+#define RT5640_PWR_LDO2_BIT                    2
+
+/* Power Management for Analog 2 (0x64) */
+#define RT5640_PWR_BST1                        (0x1 << 15)
+#define RT5640_PWR_BST1_BIT                    15
+#define RT5640_PWR_BST2                        (0x1 << 14)
+#define RT5640_PWR_BST2_BIT                    14
+#define RT5640_PWR_BST3                        (0x1 << 13)
+#define RT5640_PWR_BST3_BIT                    13
+#define RT5640_PWR_BST4                        (0x1 << 12)
+#define RT5640_PWR_BST4_BIT                    12
+#define RT5640_PWR_MB1                         (0x1 << 11)
+#define RT5640_PWR_MB1_BIT                     11
+#define RT5640_PWR_MB2                         (0x1 << 10)
+#define RT5640_PWR_MB2_BIT                     10
+#define RT5640_PWR_PLL                         (0x1 << 9)
+#define RT5640_PWR_PLL_BIT                     9
+
+/* Power Management for Mixer (0x65) */
+#define RT5640_PWR_OM_L                        (0x1 << 15)
+#define RT5640_PWR_OM_L_BIT                    15
+#define RT5640_PWR_OM_R                        (0x1 << 14)
+#define RT5640_PWR_OM_R_BIT                    14
+#define RT5640_PWR_SM_L                        (0x1 << 13)
+#define RT5640_PWR_SM_L_BIT                    13
+#define RT5640_PWR_SM_R                        (0x1 << 12)
+#define RT5640_PWR_SM_R_BIT                    12
+#define RT5640_PWR_RM_L                        (0x1 << 11)
+#define RT5640_PWR_RM_L_BIT                    11
+#define RT5640_PWR_RM_R                        (0x1 << 10)
+#define RT5640_PWR_RM_R_BIT                    10
+
+/* Power Management for Volume (0x66) */
+#define RT5640_PWR_SV_L                        (0x1 << 15)
+#define RT5640_PWR_SV_L_BIT                    15
+#define RT5640_PWR_SV_R                        (0x1 << 14)
+#define RT5640_PWR_SV_R_BIT                    14
+#define RT5640_PWR_OV_L                        (0x1 << 13)
+#define RT5640_PWR_OV_L_BIT                    13
+#define RT5640_PWR_OV_R                        (0x1 << 12)
+#define RT5640_PWR_OV_R_BIT                    12
+#define RT5640_PWR_HV_L                        (0x1 << 11)
+#define RT5640_PWR_HV_L_BIT                    11
+#define RT5640_PWR_HV_R                        (0x1 << 10)
+#define RT5640_PWR_HV_R_BIT                    10
+#define RT5640_PWR_IN_L                                (0x1 << 9)
+#define RT5640_PWR_IN_L_BIT                    9
+#define RT5640_PWR_IN_R                        (0x1 << 8)
+#define RT5640_PWR_IN_R_BIT                    8
+
+/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
+#define RT5640_I2S_MS_MASK                     (0x1 << 15)
+#define RT5640_I2S_MS_SFT                      15
+#define RT5640_I2S_MS_M                        (0x0 << 15)
+#define RT5640_I2S_MS_S                                (0x1 << 15)
+#define RT5640_I2S_IF_MASK                     (0x7 << 12)
+#define RT5640_I2S_IF_SFT                      12
+#define RT5640_I2S_O_CP_MASK                   (0x3 << 10)
+#define RT5640_I2S_O_CP_SFT                    10
+#define RT5640_I2S_O_CP_OFF                    (0x0 << 10)
+#define RT5640_I2S_O_CP_U_LAW                  (0x1 << 10)
+#define RT5640_I2S_O_CP_A_LAW                  (0x2 << 10)
+#define RT5640_I2S_I_CP_MASK                   (0x3 << 8)
+#define RT5640_I2S_I_CP_SFT                    8
+#define RT5640_I2S_I_CP_OFF                    (0x0 << 8)
+#define RT5640_I2S_I_CP_U_LAW                  (0x1 << 8)
+#define RT5640_I2S_I_CP_A_LAW                  (0x2 << 8)
+#define RT5640_I2S_BP_MASK                     (0x1 << 7)
+#define RT5640_I2S_BP_SFT                      7
+#define RT5640_I2S_BP_NOR                      (0x0 << 7)
+#define RT5640_I2S_BP_INV                      (0x1 << 7)
+#define RT5640_I2S_DL_MASK                     (0x3 << 2)
+#define RT5640_I2S_DL_SFT                      2
+#define RT5640_I2S_DL_16                       (0x0 << 2)
+#define RT5640_I2S_DL_20                       (0x1 << 2)
+#define RT5640_I2S_DL_24                       (0x2 << 2)
+#define RT5640_I2S_DL_8                                (0x3 << 2)
+#define RT5640_I2S_DF_MASK                     (0x3)
+#define RT5640_I2S_DF_SFT                      0
+#define RT5640_I2S_DF_I2S                      (0x0)
+#define RT5640_I2S_DF_LEFT                     (0x1)
+#define RT5640_I2S_DF_PCM_A                    (0x2)
+#define RT5640_I2S_DF_PCM_B                    (0x3)
+
+/* I2S2 Audio Serial Data Port Control (0x71) */
+#define RT5640_I2S2_SDI_MASK                   (0x1 << 6)
+#define RT5640_I2S2_SDI_SFT                    6
+#define RT5640_I2S2_SDI_I2S1                   (0x0 << 6)
+#define RT5640_I2S2_SDI_I2S2                   (0x1 << 6)
+
+/* ADC/DAC Clock Control 1 (0x73) */
+#define RT5640_I2S_BCLK_MS1_MASK               (0x1 << 15)
+#define RT5640_I2S_BCLK_MS1_SFT                15
+#define RT5640_I2S_BCLK_MS1_32                 (0x0 << 15)
+#define RT5640_I2S_BCLK_MS1_64                 (0x1 << 15)
+#define RT5640_I2S_PD1_MASK                    (0x7 << 12)
+#define RT5640_I2S_PD1_SFT                     12
+#define RT5640_I2S_PD1_1                       (0x0 << 12)
+#define RT5640_I2S_PD1_2                       (0x1 << 12)
+#define RT5640_I2S_PD1_3                       (0x2 << 12)
+#define RT5640_I2S_PD1_4                       (0x3 << 12)
+#define RT5640_I2S_PD1_6                       (0x4 << 12)
+#define RT5640_I2S_PD1_8                       (0x5 << 12)
+#define RT5640_I2S_PD1_12                      (0x6 << 12)
+#define RT5640_I2S_PD1_16                      (0x7 << 12)
+#define RT5640_I2S_BCLK_MS2_MASK               (0x1 << 11)
+#define RT5640_I2S_BCLK_MS2_SFT                11
+#define RT5640_I2S_BCLK_MS2_32                 (0x0 << 11)
+#define RT5640_I2S_BCLK_MS2_64                 (0x1 << 11)
+#define RT5640_I2S_PD2_MASK                    (0x7 << 8)
+#define RT5640_I2S_PD2_SFT                     8
+#define RT5640_I2S_PD2_1                       (0x0 << 8)
+#define RT5640_I2S_PD2_2                       (0x1 << 8)
+#define RT5640_I2S_PD2_3                       (0x2 << 8)
+#define RT5640_I2S_PD2_4                       (0x3 << 8)
+#define RT5640_I2S_PD2_6                       (0x4 << 8)
+#define RT5640_I2S_PD2_8                       (0x5 << 8)
+#define RT5640_I2S_PD2_12                      (0x6 << 8)
+#define RT5640_I2S_PD2_16                      (0x7 << 8)
+#define RT5640_I2S_BCLK_MS3_MASK               (0x1 << 7)
+#define RT5640_I2S_BCLK_MS3_SFT                7
+#define RT5640_I2S_BCLK_MS3_32                 (0x0 << 7)
+#define RT5640_I2S_BCLK_MS3_64                 (0x1 << 7)
+#define RT5640_I2S_PD3_MASK                    (0x7 << 4)
+#define RT5640_I2S_PD3_SFT                     4
+#define RT5640_I2S_PD3_1                       (0x0 << 4)
+#define RT5640_I2S_PD3_2                       (0x1 << 4)
+#define RT5640_I2S_PD3_3                       (0x2 << 4)
+#define RT5640_I2S_PD3_4                       (0x3 << 4)
+#define RT5640_I2S_PD3_6                       (0x4 << 4)
+#define RT5640_I2S_PD3_8                       (0x5 << 4)
+#define RT5640_I2S_PD3_12                      (0x6 << 4)
+#define RT5640_I2S_PD3_16                      (0x7 << 4)
+#define RT5640_DAC_OSR_MASK                    (0x3 << 2)
+#define RT5640_DAC_OSR_SFT                     2
+#define RT5640_DAC_OSR_128                     (0x0 << 2)
+#define RT5640_DAC_OSR_64                      (0x1 << 2)
+#define RT5640_DAC_OSR_32                      (0x2 << 2)
+#define RT5640_DAC_OSR_16                      (0x3 << 2)
+#define RT5640_ADC_OSR_MASK                    (0x3)
+#define RT5640_ADC_OSR_SFT                     0
+#define RT5640_ADC_OSR_128                     (0x0)
+#define RT5640_ADC_OSR_64                      (0x1)
+#define RT5640_ADC_OSR_32                      (0x2)
+#define RT5640_ADC_OSR_16                      (0x3)
+
+/* ADC/DAC Clock Control 2 (0x74) */
+#define RT5640_DAC_L_OSR_MASK                  (0x3 << 14)
+#define RT5640_DAC_L_OSR_SFT                   14
+#define RT5640_DAC_L_OSR_128                   (0x0 << 14)
+#define RT5640_DAC_L_OSR_64                    (0x1 << 14)
+#define RT5640_DAC_L_OSR_32                    (0x2 << 14)
+#define RT5640_DAC_L_OSR_16                    (0x3 << 14)
+#define RT5640_ADC_R_OSR_MASK                  (0x3 << 12)
+#define RT5640_ADC_R_OSR_SFT                   12
+#define RT5640_ADC_R_OSR_128                   (0x0 << 12)
+#define RT5640_ADC_R_OSR_64                    (0x1 << 12)
+#define RT5640_ADC_R_OSR_32                    (0x2 << 12)
+#define RT5640_ADC_R_OSR_16                    (0x3 << 12)
+#define RT5640_DAHPF_EN                        (0x1 << 11)
+#define RT5640_DAHPF_EN_SFT                    11
+#define RT5640_ADHPF_EN                        (0x1 << 10)
+#define RT5640_ADHPF_EN_SFT                    10
+
+/* Digital Microphone Control (0x75) */
+#define RT5640_DMIC_1_EN_MASK                  (0x1 << 15)
+#define RT5640_DMIC_1_EN_SFT                   15
+#define RT5640_DMIC_1_DIS                      (0x0 << 15)
+#define RT5640_DMIC_1_EN                       (0x1 << 15)
+#define RT5640_DMIC_2_EN_MASK                  (0x1 << 14)
+#define RT5640_DMIC_2_EN_SFT                   14
+#define RT5640_DMIC_2_DIS                      (0x0 << 14)
+#define RT5640_DMIC_2_EN                       (0x1 << 14)
+#define RT5640_DMIC_1L_LH_MASK         (0x1 << 13)
+#define RT5640_DMIC_1L_LH_SFT                  13
+#define RT5640_DMIC_1L_LH_FALLING              (0x0 << 13)
+#define RT5640_DMIC_1L_LH_RISING               (0x1 << 13)
+#define RT5640_DMIC_1R_LH_MASK         (0x1 << 12)
+#define RT5640_DMIC_1R_LH_SFT                  12
+#define RT5640_DMIC_1R_LH_FALLING              (0x0 << 12)
+#define RT5640_DMIC_1R_LH_RISING               (0x1 << 12)
+#define RT5640_DMIC_1_DP_MASK                  (0x1 << 11)
+#define RT5640_DMIC_1_DP_SFT                   11
+#define RT5640_DMIC_1_DP_GPIO3                 (0x0 << 11)
+#define RT5640_DMIC_1_DP_IN1P                  (0x1 << 11)
+#define RT5640_DMIC_2_DP_MASK                  (0x1 << 10)
+#define RT5640_DMIC_2_DP_SFT                   10
+#define RT5640_DMIC_2_DP_GPIO4                 (0x0 << 10)
+#define RT5640_DMIC_2_DP_IN1N                  (0x1 << 10)
+#define RT5640_DMIC_2L_LH_MASK         (0x1 << 9)
+#define RT5640_DMIC_2L_LH_SFT                  9
+#define RT5640_DMIC_2L_LH_FALLING              (0x0 << 9)
+#define RT5640_DMIC_2L_LH_RISING               (0x1 << 9)
+#define RT5640_DMIC_2R_LH_MASK         (0x1 << 8)
+#define RT5640_DMIC_2R_LH_SFT                  8
+#define RT5640_DMIC_2R_LH_FALLING              (0x0 << 8)
+#define RT5640_DMIC_2R_LH_RISING               (0x1 << 8)
+#define RT5640_DMIC_CLK_MASK                   (0x7 << 5)
+#define RT5640_DMIC_CLK_SFT                    5
+
+/* Global Clock Control (0x80) */
+#define RT5640_SCLK_SRC_MASK                   (0x3 << 14)
+#define RT5640_SCLK_SRC_SFT                    14
+#define RT5640_SCLK_SRC_MCLK                   (0x0 << 14)
+#define RT5640_SCLK_SRC_PLL1                   (0x1 << 14)
+#define RT5640_SCLK_SRC_PLL1T                  (0x2 << 14)
+#define RT5640_SCLK_SRC_RCCLK                  (0x3 << 14) /* 15MHz */
+#define RT5640_PLL1_SRC_MASK                   (0x3 << 12)
+#define RT5640_PLL1_SRC_SFT                    12
+#define RT5640_PLL1_SRC_MCLK                   (0x0 << 12)
+#define RT5640_PLL1_SRC_BCLK1                  (0x1 << 12)
+#define RT5640_PLL1_SRC_BCLK2                  (0x2 << 12)
+#define RT5640_PLL1_SRC_BCLK3                  (0x3 << 12)
+#define RT5640_PLL1_PD_MASK                    (0x1 << 3)
+#define RT5640_PLL1_PD_SFT                     3
+#define RT5640_PLL1_PD_1                       (0x0 << 3)
+#define RT5640_PLL1_PD_2                       (0x1 << 3)
+
+#define RT5640_PLL_INP_MAX                     40000000
+#define RT5640_PLL_INP_MIN                     256000
+/* PLL M/N/K Code Control 1 (0x81) */
+#define RT5640_PLL_N_MAX                       0x1ff
+#define RT5640_PLL_N_MASK                      (RT5640_PLL_N_MAX << 7)
+#define RT5640_PLL_N_SFT                       7
+#define RT5640_PLL_K_MAX                       0x1f
+#define RT5640_PLL_K_MASK                      (RT5640_PLL_K_MAX)
+#define RT5640_PLL_K_SFT                       0
+
+/* PLL M/N/K Code Control 2 (0x82) */
+#define RT5640_PLL_M_MAX                       0xf
+#define RT5640_PLL_M_MASK                      (RT5640_PLL_M_MAX << 12)
+#define RT5640_PLL_M_SFT                       12
+#define RT5640_PLL_M_BP                                (0x1 << 11)
+#define RT5640_PLL_M_BP_SFT                    11
+
+/* ASRC Control 1 (0x83) */
+#define RT5640_STO_T_MASK                      (0x1 << 15)
+#define RT5640_STO_T_SFT                       15
+#define RT5640_STO_T_SCLK                      (0x0 << 15)
+#define RT5640_STO_T_LRCK1                     (0x1 << 15)
+#define RT5640_M1_T_MASK                       (0x1 << 14)
+#define RT5640_M1_T_SFT                                14
+#define RT5640_M1_T_I2S2                       (0x0 << 14)
+#define RT5640_M1_T_I2S2_D3                    (0x1 << 14)
+#define RT5640_I2S2_F_MASK                     (0x1 << 12)
+#define RT5640_I2S2_F_SFT                      12
+#define RT5640_I2S2_F_I2S2_D2                  (0x0 << 12)
+#define RT5640_I2S2_F_I2S1_TCLK                        (0x1 << 12)
+#define RT5640_DMIC_1_M_MASK                   (0x1 << 9)
+#define RT5640_DMIC_1_M_SFT                    9
+#define RT5640_DMIC_1_M_NOR                    (0x0 << 9)
+#define RT5640_DMIC_1_M_ASYN                   (0x1 << 9)
+#define RT5640_DMIC_2_M_MASK                   (0x1 << 8)
+#define RT5640_DMIC_2_M_SFT                    8
+#define RT5640_DMIC_2_M_NOR                    (0x0 << 8)
+#define RT5640_DMIC_2_M_ASYN                   (0x1 << 8)
+
+/* ASRC Control 2 (0x84) */
+#define RT5640_MDA_L_M_MASK                    (0x1 << 15)
+#define RT5640_MDA_L_M_SFT                     15
+#define RT5640_MDA_L_M_NOR                     (0x0 << 15)
+#define RT5640_MDA_L_M_ASYN                    (0x1 << 15)
+#define RT5640_MDA_R_M_MASK                    (0x1 << 14)
+#define RT5640_MDA_R_M_SFT                     14
+#define RT5640_MDA_R_M_NOR                     (0x0 << 14)
+#define RT5640_MDA_R_M_ASYN                    (0x1 << 14)
+#define RT5640_MAD_L_M_MASK                    (0x1 << 13)
+#define RT5640_MAD_L_M_SFT                     13
+#define RT5640_MAD_L_M_NOR                     (0x0 << 13)
+#define RT5640_MAD_L_M_ASYN                    (0x1 << 13)
+#define RT5640_MAD_R_M_MASK                    (0x1 << 12)
+#define RT5640_MAD_R_M_SFT                     12
+#define RT5640_MAD_R_M_NOR                     (0x0 << 12)
+#define RT5640_MAD_R_M_ASYN                    (0x1 << 12)
+#define RT5640_ADC_M_MASK                      (0x1 << 11)
+#define RT5640_ADC_M_SFT                       11
+#define RT5640_ADC_M_NOR                       (0x0 << 11)
+#define RT5640_ADC_M_ASYN                      (0x1 << 11)
+#define RT5640_STO_DAC_M_MASK                  (0x1 << 5)
+#define RT5640_STO_DAC_M_SFT                   5
+#define RT5640_STO_DAC_M_NOR                   (0x0 << 5)
+#define RT5640_STO_DAC_M_ASYN                  (0x1 << 5)
+#define RT5640_I2S1_R_D_MASK                   (0x1 << 4)
+#define RT5640_I2S1_R_D_SFT                    4
+#define RT5640_I2S1_R_D_DIS                    (0x0 << 4)
+#define RT5640_I2S1_R_D_EN                     (0x1 << 4)
+#define RT5640_I2S2_R_D_MASK                   (0x1 << 3)
+#define RT5640_I2S2_R_D_SFT                    3
+#define RT5640_I2S2_R_D_DIS                    (0x0 << 3)
+#define RT5640_I2S2_R_D_EN                     (0x1 << 3)
+#define RT5640_PRE_SCLK_MASK                   (0x3)
+#define RT5640_PRE_SCLK_SFT                    0
+#define RT5640_PRE_SCLK_512                    (0x0)
+#define RT5640_PRE_SCLK_1024                   (0x1)
+#define RT5640_PRE_SCLK_2048                   (0x2)
+
+/* ASRC Control 3 (0x85) */
+#define RT5640_I2S1_RATE_MASK                  (0xf << 12)
+#define RT5640_I2S1_RATE_SFT                   12
+#define RT5640_I2S2_RATE_MASK                  (0xf << 8)
+#define RT5640_I2S2_RATE_SFT                   8
+
+/* ASRC Control 4 (0x89) */
+#define RT5640_I2S1_PD_MASK                    (0x7 << 12)
+#define RT5640_I2S1_PD_SFT                     12
+#define RT5640_I2S2_PD_MASK                    (0x7 << 8)
+#define RT5640_I2S2_PD_SFT                     8
+
+/* HPOUT Over Current Detection (0x8b) */
+#define RT5640_HP_OVCD_MASK                    (0x1 << 10)
+#define RT5640_HP_OVCD_SFT                     10
+#define RT5640_HP_OVCD_DIS                     (0x0 << 10)
+#define RT5640_HP_OVCD_EN                      (0x1 << 10)
+#define RT5640_HP_OC_TH_MASK                   (0x3 << 8)
+#define RT5640_HP_OC_TH_SFT                    8
+#define RT5640_HP_OC_TH_90                     (0x0 << 8)
+#define RT5640_HP_OC_TH_105                    (0x1 << 8)
+#define RT5640_HP_OC_TH_120                    (0x2 << 8)
+#define RT5640_HP_OC_TH_135                    (0x3 << 8)
+
+/* Class D Over Current Control (0x8c) */
+#define RT5640_CLSD_OC_MASK                    (0x1 << 9)
+#define RT5640_CLSD_OC_SFT                     9
+#define RT5640_CLSD_OC_PU                      (0x0 << 9)
+#define RT5640_CLSD_OC_PD                      (0x1 << 9)
+#define RT5640_AUTO_PD_MASK                    (0x1 << 8)
+#define RT5640_AUTO_PD_SFT                     8
+#define RT5640_AUTO_PD_DIS                     (0x0 << 8)
+#define RT5640_AUTO_PD_EN                      (0x1 << 8)
+#define RT5640_CLSD_OC_TH_MASK         (0x3f)
+#define RT5640_CLSD_OC_TH_SFT                  0
+
+/* Class D Output Control (0x8d) */
+#define RT5640_CLSD_RATIO_MASK         (0xf << 12)
+#define RT5640_CLSD_RATIO_SFT                  12
+#define RT5640_CLSD_OM_MASK                    (0x1 << 11)
+#define RT5640_CLSD_OM_SFT                     11
+#define RT5640_CLSD_OM_MONO                    (0x0 << 11)
+#define RT5640_CLSD_OM_STO                     (0x1 << 11)
+#define RT5640_CLSD_SCH_MASK                   (0x1 << 10)
+#define RT5640_CLSD_SCH_SFT                    10
+#define RT5640_CLSD_SCH_L                      (0x0 << 10)
+#define RT5640_CLSD_SCH_S                      (0x1 << 10)
+
+/* Depop Mode Control 1 (0x8e) */
+#define RT5640_SMT_TRIG_MASK                   (0x1 << 15)
+#define RT5640_SMT_TRIG_SFT                    15
+#define RT5640_SMT_TRIG_DIS                    (0x0 << 15)
+#define RT5640_SMT_TRIG_EN                     (0x1 << 15)
+#define RT5640_HP_L_SMT_MASK                   (0x1 << 9)
+#define RT5640_HP_L_SMT_SFT                    9
+#define RT5640_HP_L_SMT_DIS                    (0x0 << 9)
+#define RT5640_HP_L_SMT_EN                     (0x1 << 9)
+#define RT5640_HP_R_SMT_MASK                   (0x1 << 8)
+#define RT5640_HP_R_SMT_SFT                    8
+#define RT5640_HP_R_SMT_DIS                    (0x0 << 8)
+#define RT5640_HP_R_SMT_EN                     (0x1 << 8)
+#define RT5640_HP_CD_PD_MASK                   (0x1 << 7)
+#define RT5640_HP_CD_PD_SFT                    7
+#define RT5640_HP_CD_PD_DIS                    (0x0 << 7)
+#define RT5640_HP_CD_PD_EN                     (0x1 << 7)
+#define RT5640_RSTN_MASK                       (0x1 << 6)
+#define RT5640_RSTN_SFT                                6
+#define RT5640_RSTN_DIS                                (0x0 << 6)
+#define RT5640_RSTN_EN                         (0x1 << 6)
+#define RT5640_RSTP_MASK                       (0x1 << 5)
+#define RT5640_RSTP_SFT                                5
+#define RT5640_RSTP_DIS                                (0x0 << 5)
+#define RT5640_RSTP_EN                         (0x1 << 5)
+#define RT5640_HP_CO_MASK                      (0x1 << 4)
+#define RT5640_HP_CO_SFT                       4
+#define RT5640_HP_CO_DIS                       (0x0 << 4)
+#define RT5640_HP_CO_EN                        (0x1 << 4)
+#define RT5640_HP_CP_MASK                      (0x1 << 3)
+#define RT5640_HP_CP_SFT                       3
+#define RT5640_HP_CP_PD                        (0x0 << 3)
+#define RT5640_HP_CP_PU                        (0x1 << 3)
+#define RT5640_HP_SG_MASK                      (0x1 << 2)
+#define RT5640_HP_SG_SFT                       2
+#define RT5640_HP_SG_DIS                       (0x0 << 2)
+#define RT5640_HP_SG_EN                        (0x1 << 2)
+#define RT5640_HP_DP_MASK                      (0x1 << 1)
+#define RT5640_HP_DP_SFT                       1
+#define RT5640_HP_DP_PD                        (0x0 << 1)
+#define RT5640_HP_DP_PU                        (0x1 << 1)
+#define RT5640_HP_CB_MASK                      (0x1)
+#define RT5640_HP_CB_SFT                       0
+#define RT5640_HP_CB_PD                        (0x0)
+#define RT5640_HP_CB_PU                        (0x1)
+
+/* Depop Mode Control 2 (0x8f) */
+#define RT5640_DEPOP_MASK                      (0x1 << 13)
+#define RT5640_DEPOP_SFT                       13
+#define RT5640_DEPOP_AUTO                      (0x0 << 13)
+#define RT5640_DEPOP_MAN                       (0x1 << 13)
+#define RT5640_RAMP_MASK                       (0x1 << 12)
+#define RT5640_RAMP_SFT                        12
+#define RT5640_RAMP_DIS                                (0x0 << 12)
+#define RT5640_RAMP_EN                         (0x1 << 12)
+#define RT5640_BPS_MASK                        (0x1 << 11)
+#define RT5640_BPS_SFT                         11
+#define RT5640_BPS_DIS                         (0x0 << 11)
+#define RT5640_BPS_EN                          (0x1 << 11)
+#define RT5640_FAST_UPDN_MASK                  (0x1 << 10)
+#define RT5640_FAST_UPDN_SFT                   10
+#define RT5640_FAST_UPDN_DIS                   (0x0 << 10)
+#define RT5640_FAST_UPDN_EN                    (0x1 << 10)
+#define RT5640_MRES_MASK                       (0x3 << 8)
+#define RT5640_MRES_SFT                                8
+#define RT5640_MRES_15MO                       (0x0 << 8)
+#define RT5640_MRES_25MO                       (0x1 << 8)
+#define RT5640_MRES_35MO                       (0x2 << 8)
+#define RT5640_MRES_45MO                       (0x3 << 8)
+#define RT5640_VLO_MASK                        (0x1 << 7)
+#define RT5640_VLO_SFT                         7
+#define RT5640_VLO_3V                          (0x0 << 7)
+#define RT5640_VLO_32V                         (0x1 << 7)
+#define RT5640_DIG_DP_MASK                     (0x1 << 6)
+#define RT5640_DIG_DP_SFT                      6
+#define RT5640_DIG_DP_DIS                      (0x0 << 6)
+#define RT5640_DIG_DP_EN                       (0x1 << 6)
+#define RT5640_DP_TH_MASK                      (0x3 << 4)
+#define RT5640_DP_TH_SFT                       4
+
+/* Depop Mode Control 3 (0x90) */
+#define RT5640_CP_SYS_MASK                     (0x7 << 12)
+#define RT5640_CP_SYS_SFT                      12
+#define RT5640_CP_FQ1_MASK                     (0x7 << 8)
+#define RT5640_CP_FQ1_SFT                      8
+#define RT5640_CP_FQ2_MASK                     (0x7 << 4)
+#define RT5640_CP_FQ2_SFT                      4
+#define RT5640_CP_FQ3_MASK                     (0x7)
+#define RT5640_CP_FQ3_SFT                      0
+
+/* HPOUT charge pump (0x91) */
+#define RT5640_OSW_L_MASK                      (0x1 << 11)
+#define RT5640_OSW_L_SFT                       11
+#define RT5640_OSW_L_DIS                       (0x0 << 11)
+#define RT5640_OSW_L_EN                        (0x1 << 11)
+#define RT5640_OSW_R_MASK                      (0x1 << 10)
+#define RT5640_OSW_R_SFT                       10
+#define RT5640_OSW_R_DIS                       (0x0 << 10)
+#define RT5640_OSW_R_EN                        (0x1 << 10)
+#define RT5640_PM_HP_MASK                      (0x3 << 8)
+#define RT5640_PM_HP_SFT                       8
+#define RT5640_PM_HP_LV                        (0x0 << 8)
+#define RT5640_PM_HP_MV                        (0x1 << 8)
+#define RT5640_PM_HP_HV                        (0x2 << 8)
+#define RT5640_IB_HP_MASK                      (0x3 << 6)
+#define RT5640_IB_HP_SFT                       6
+#define RT5640_IB_HP_125IL                     (0x0 << 6)
+#define RT5640_IB_HP_25IL                      (0x1 << 6)
+#define RT5640_IB_HP_5IL                       (0x2 << 6)
+#define RT5640_IB_HP_1IL                       (0x3 << 6)
+
+/* PV detection and SPK gain control (0x92) */
+#define RT5640_PVDD_DET_MASK                   (0x1 << 15)
+#define RT5640_PVDD_DET_SFT                    15
+#define RT5640_PVDD_DET_DIS                    (0x0 << 15)
+#define RT5640_PVDD_DET_EN                     (0x1 << 15)
+#define RT5640_SPK_AG_MASK                     (0x1 << 14)
+#define RT5640_SPK_AG_SFT                      14
+#define RT5640_SPK_AG_DIS                      (0x0 << 14)
+#define RT5640_SPK_AG_EN                       (0x1 << 14)
+
+/* Micbias Control (0x93) */
+#define RT5640_MIC1_BS_MASK                    (0x1 << 15)
+#define RT5640_MIC1_BS_SFT                     15
+#define RT5640_MIC1_BS_9AV                     (0x0 << 15)
+#define RT5640_MIC1_BS_75AV                    (0x1 << 15)
+#define RT5640_MIC2_BS_MASK                    (0x1 << 14)
+#define RT5640_MIC2_BS_SFT                     14
+#define RT5640_MIC2_BS_9AV                     (0x0 << 14)
+#define RT5640_MIC2_BS_75AV                    (0x1 << 14)
+#define RT5640_MIC1_CLK_MASK                   (0x1 << 13)
+#define RT5640_MIC1_CLK_SFT                    13
+#define RT5640_MIC1_CLK_DIS                    (0x0 << 13)
+#define RT5640_MIC1_CLK_EN                     (0x1 << 13)
+#define RT5640_MIC2_CLK_MASK                   (0x1 << 12)
+#define RT5640_MIC2_CLK_SFT                    12
+#define RT5640_MIC2_CLK_DIS                    (0x0 << 12)
+#define RT5640_MIC2_CLK_EN                     (0x1 << 12)
+#define RT5640_MIC1_OVCD_MASK                  (0x1 << 11)
+#define RT5640_MIC1_OVCD_SFT                   11
+#define RT5640_MIC1_OVCD_DIS                   (0x0 << 11)
+#define RT5640_MIC1_OVCD_EN                    (0x1 << 11)
+#define RT5640_MIC1_OVTH_MASK                  (0x3 << 9)
+#define RT5640_MIC1_OVTH_SFT                   9
+#define RT5640_MIC1_OVTH_600UA         (0x0 << 9)
+#define RT5640_MIC1_OVTH_1500UA                (0x1 << 9)
+#define RT5640_MIC1_OVTH_2000UA                (0x2 << 9)
+#define RT5640_MIC2_OVCD_MASK                  (0x1 << 8)
+#define RT5640_MIC2_OVCD_SFT                   8
+#define RT5640_MIC2_OVCD_DIS                   (0x0 << 8)
+#define RT5640_MIC2_OVCD_EN                    (0x1 << 8)
+#define RT5640_MIC2_OVTH_MASK                  (0x3 << 6)
+#define RT5640_MIC2_OVTH_SFT                   6
+#define RT5640_MIC2_OVTH_600UA         (0x0 << 6)
+#define RT5640_MIC2_OVTH_1500UA                (0x1 << 6)
+#define RT5640_MIC2_OVTH_2000UA                (0x2 << 6)
+#define RT5640_PWR_MB_MASK                     (0x1 << 5)
+#define RT5640_PWR_MB_SFT                      5
+#define RT5640_PWR_MB_PD                       (0x0 << 5)
+#define RT5640_PWR_MB_PU                       (0x1 << 5)
+#define RT5640_PWR_CLK25M_MASK         (0x1 << 4)
+#define RT5640_PWR_CLK25M_SFT                  4
+#define RT5640_PWR_CLK25M_PD                   (0x0 << 4)
+#define RT5640_PWR_CLK25M_PU                   (0x1 << 4)
+
+/* EQ Control 1 (0xb0) */
+#define RT5640_EQ_SRC_MASK                     (0x1 << 15)
+#define RT5640_EQ_SRC_SFT                      15
+#define RT5640_EQ_SRC_DAC                      (0x0 << 15)
+#define RT5640_EQ_SRC_ADC                      (0x1 << 15)
+#define RT5640_EQ_UPD                          (0x1 << 14)
+#define RT5640_EQ_UPD_BIT                      14
+#define RT5640_EQ_CD_MASK                      (0x1 << 13)
+#define RT5640_EQ_CD_SFT                       13
+#define RT5640_EQ_CD_DIS                       (0x0 << 13)
+#define RT5640_EQ_CD_EN                        (0x1 << 13)
+#define RT5640_EQ_DITH_MASK                    (0x3 << 8)
+#define RT5640_EQ_DITH_SFT                     8
+#define RT5640_EQ_DITH_NOR                     (0x0 << 8)
+#define RT5640_EQ_DITH_LSB                     (0x1 << 8)
+#define RT5640_EQ_DITH_LSB_1                   (0x2 << 8)
+#define RT5640_EQ_DITH_LSB_2                   (0x3 << 8)
+
+/* EQ Control 2 (0xb1) */
+#define RT5640_EQ_HPF1_M_MASK                  (0x1 << 8)
+#define RT5640_EQ_HPF1_M_SFT                   8
+#define RT5640_EQ_HPF1_M_HI                    (0x0 << 8)
+#define RT5640_EQ_HPF1_M_1ST                   (0x1 << 8)
+#define RT5640_EQ_LPF1_M_MASK                  (0x1 << 7)
+#define RT5640_EQ_LPF1_M_SFT                   7
+#define RT5640_EQ_LPF1_M_LO                    (0x0 << 7)
+#define RT5640_EQ_LPF1_M_1ST                   (0x1 << 7)
+#define RT5640_EQ_HPF2_MASK                    (0x1 << 6)
+#define RT5640_EQ_HPF2_SFT                     6
+#define RT5640_EQ_HPF2_DIS                     (0x0 << 6)
+#define RT5640_EQ_HPF2_EN                      (0x1 << 6)
+#define RT5640_EQ_HPF1_MASK                    (0x1 << 5)
+#define RT5640_EQ_HPF1_SFT                     5
+#define RT5640_EQ_HPF1_DIS                     (0x0 << 5)
+#define RT5640_EQ_HPF1_EN                      (0x1 << 5)
+#define RT5640_EQ_BPF4_MASK                    (0x1 << 4)
+#define RT5640_EQ_BPF4_SFT                     4
+#define RT5640_EQ_BPF4_DIS                     (0x0 << 4)
+#define RT5640_EQ_BPF4_EN                      (0x1 << 4)
+#define RT5640_EQ_BPF3_MASK                    (0x1 << 3)
+#define RT5640_EQ_BPF3_SFT                     3
+#define RT5640_EQ_BPF3_DIS                     (0x0 << 3)
+#define RT5640_EQ_BPF3_EN                      (0x1 << 3)
+#define RT5640_EQ_BPF2_MASK                    (0x1 << 2)
+#define RT5640_EQ_BPF2_SFT                     2
+#define RT5640_EQ_BPF2_DIS                     (0x0 << 2)
+#define RT5640_EQ_BPF2_EN                      (0x1 << 2)
+#define RT5640_EQ_BPF1_MASK                    (0x1 << 1)
+#define RT5640_EQ_BPF1_SFT                     1
+#define RT5640_EQ_BPF1_DIS                     (0x0 << 1)
+#define RT5640_EQ_BPF1_EN                      (0x1 << 1)
+#define RT5640_EQ_LPF_MASK                     (0x1)
+#define RT5640_EQ_LPF_SFT                      0
+#define RT5640_EQ_LPF_DIS                      (0x0)
+#define RT5640_EQ_LPF_EN                       (0x1)
+
+/* Memory Test (0xb2) */
+#define RT5640_MT_MASK                         (0x1 << 15)
+#define RT5640_MT_SFT                          15
+#define RT5640_MT_DIS                          (0x0 << 15)
+#define RT5640_MT_EN                           (0x1 << 15)
+
+/* DRC/AGC Control 1 (0xb4) */
+#define RT5640_DRC_AGC_P_MASK                  (0x1 << 15)
+#define RT5640_DRC_AGC_P_SFT                   15
+#define RT5640_DRC_AGC_P_DAC                   (0x0 << 15)
+#define RT5640_DRC_AGC_P_ADC                   (0x1 << 15)
+#define RT5640_DRC_AGC_MASK                    (0x1 << 14)
+#define RT5640_DRC_AGC_SFT                     14
+#define RT5640_DRC_AGC_DIS                     (0x0 << 14)
+#define RT5640_DRC_AGC_EN                      (0x1 << 14)
+#define RT5640_DRC_AGC_UPD                     (0x1 << 13)
+#define RT5640_DRC_AGC_UPD_BIT         13
+#define RT5640_DRC_AGC_AR_MASK         (0x1f << 8)
+#define RT5640_DRC_AGC_AR_SFT                  8
+#define RT5640_DRC_AGC_R_MASK                  (0x7 << 5)
+#define RT5640_DRC_AGC_R_SFT                   5
+#define RT5640_DRC_AGC_R_48K                   (0x1 << 5)
+#define RT5640_DRC_AGC_R_96K                   (0x2 << 5)
+#define RT5640_DRC_AGC_R_192K                  (0x3 << 5)
+#define RT5640_DRC_AGC_R_441K                  (0x5 << 5)
+#define RT5640_DRC_AGC_R_882K                  (0x6 << 5)
+#define RT5640_DRC_AGC_R_1764K         (0x7 << 5)
+#define RT5640_DRC_AGC_RC_MASK         (0x1f)
+#define RT5640_DRC_AGC_RC_SFT                  0
+
+/* DRC/AGC Control 2 (0xb5) */
+#define RT5640_DRC_AGC_POB_MASK                (0x3f << 8)
+#define RT5640_DRC_AGC_POB_SFT         8
+#define RT5640_DRC_AGC_CP_MASK         (0x1 << 7)
+#define RT5640_DRC_AGC_CP_SFT                  7
+#define RT5640_DRC_AGC_CP_DIS                  (0x0 << 7)
+#define RT5640_DRC_AGC_CP_EN                   (0x1 << 7)
+#define RT5640_DRC_AGC_CPR_MASK                (0x3 << 5)
+#define RT5640_DRC_AGC_CPR_SFT         5
+#define RT5640_DRC_AGC_CPR_1_1         (0x0 << 5)
+#define RT5640_DRC_AGC_CPR_1_2         (0x1 << 5)
+#define RT5640_DRC_AGC_CPR_1_3         (0x2 << 5)
+#define RT5640_DRC_AGC_CPR_1_4         (0x3 << 5)
+#define RT5640_DRC_AGC_PRB_MASK                (0x1f)
+#define RT5640_DRC_AGC_PRB_SFT         0
+
+/* DRC/AGC Control 3 (0xb6) */
+#define RT5640_DRC_AGC_NGB_MASK                (0xf << 12)
+#define RT5640_DRC_AGC_NGB_SFT         12
+#define RT5640_DRC_AGC_TAR_MASK                (0x1f << 7)
+#define RT5640_DRC_AGC_TAR_SFT         7
+#define RT5640_DRC_AGC_NG_MASK         (0x1 << 6)
+#define RT5640_DRC_AGC_NG_SFT                  6
+#define RT5640_DRC_AGC_NG_DIS                  (0x0 << 6)
+#define RT5640_DRC_AGC_NG_EN                   (0x1 << 6)
+#define RT5640_DRC_AGC_NGH_MASK                (0x1 << 5)
+#define RT5640_DRC_AGC_NGH_SFT         5
+#define RT5640_DRC_AGC_NGH_DIS         (0x0 << 5)
+#define RT5640_DRC_AGC_NGH_EN                  (0x1 << 5)
+#define RT5640_DRC_AGC_NGT_MASK                (0x1f)
+#define RT5640_DRC_AGC_NGT_SFT         0
+
+/* ANC Control 1 (0xb8) */
+#define RT5640_ANC_M_MASK                      (0x1 << 15)
+#define RT5640_ANC_M_SFT                       15
+#define RT5640_ANC_M_NOR                       (0x0 << 15)
+#define RT5640_ANC_M_REV                       (0x1 << 15)
+#define RT5640_ANC_MASK                        (0x1 << 14)
+#define RT5640_ANC_SFT                         14
+#define RT5640_ANC_DIS                         (0x0 << 14)
+#define RT5640_ANC_EN                          (0x1 << 14)
+#define RT5640_ANC_MD_MASK                     (0x3 << 12)
+#define RT5640_ANC_MD_SFT                      12
+#define RT5640_ANC_MD_DIS                      (0x0 << 12)
+#define RT5640_ANC_MD_67MS                     (0x1 << 12)
+#define RT5640_ANC_MD_267MS                    (0x2 << 12)
+#define RT5640_ANC_MD_1067MS                   (0x3 << 12)
+#define RT5640_ANC_SN_MASK                     (0x1 << 11)
+#define RT5640_ANC_SN_SFT                      11
+#define RT5640_ANC_SN_DIS                      (0x0 << 11)
+#define RT5640_ANC_SN_EN                       (0x1 << 11)
+#define RT5640_ANC_CLK_MASK                    (0x1 << 10)
+#define RT5640_ANC_CLK_SFT                     10
+#define RT5640_ANC_CLK_ANC                     (0x0 << 10)
+#define RT5640_ANC_CLK_REG                     (0x1 << 10)
+#define RT5640_ANC_ZCD_MASK                    (0x3 << 8)
+#define RT5640_ANC_ZCD_SFT                     8
+#define RT5640_ANC_ZCD_DIS                     (0x0 << 8)
+#define RT5640_ANC_ZCD_T1                      (0x1 << 8)
+#define RT5640_ANC_ZCD_T2                      (0x2 << 8)
+#define RT5640_ANC_ZCD_WT                      (0x3 << 8)
+#define RT5640_ANC_CS_MASK                     (0x1 << 7)
+#define RT5640_ANC_CS_SFT                      7
+#define RT5640_ANC_CS_DIS                      (0x0 << 7)
+#define RT5640_ANC_CS_EN                       (0x1 << 7)
+#define RT5640_ANC_SW_MASK                     (0x1 << 6)
+#define RT5640_ANC_SW_SFT                      6
+#define RT5640_ANC_SW_NOR                      (0x0 << 6)
+#define RT5640_ANC_SW_AUTO                     (0x1 << 6)
+#define RT5640_ANC_CO_L_MASK                   (0x3f)
+#define RT5640_ANC_CO_L_SFT                    0
+
+/* ANC Control 2 (0xb6) */
+#define RT5640_ANC_FG_R_MASK                   (0xf << 12)
+#define RT5640_ANC_FG_R_SFT                    12
+#define RT5640_ANC_FG_L_MASK                   (0xf << 8)
+#define RT5640_ANC_FG_L_SFT                    8
+#define RT5640_ANC_CG_R_MASK                   (0xf << 4)
+#define RT5640_ANC_CG_R_SFT                    4
+#define RT5640_ANC_CG_L_MASK                   (0xf)
+#define RT5640_ANC_CG_L_SFT                    0
+
+/* ANC Control 3 (0xb6) */
+#define RT5640_ANC_CD_MASK                     (0x1 << 6)
+#define RT5640_ANC_CD_SFT                      6
+#define RT5640_ANC_CD_BOTH                     (0x0 << 6)
+#define RT5640_ANC_CD_IND                      (0x1 << 6)
+#define RT5640_ANC_CO_R_MASK                   (0x3f)
+#define RT5640_ANC_CO_R_SFT                    0
+
+/* Jack Detect Control (0xbb) */
+#define RT5640_JD_MASK                         (0x7 << 13)
+#define RT5640_JD_SFT                          13
+#define RT5640_JD_DIS                          (0x0 << 13)
+#define RT5640_JD_GPIO1                                (0x1 << 13)
+#define RT5640_JD_JD1_IN4P                     (0x2 << 13)
+#define RT5640_JD_JD2_IN4N                     (0x3 << 13)
+#define RT5640_JD_GPIO2                                (0x4 << 13)
+#define RT5640_JD_GPIO3                                (0x5 << 13)
+#define RT5640_JD_GPIO4                                (0x6 << 13)
+#define RT5640_JD_HP_MASK                      (0x1 << 11)
+#define RT5640_JD_HP_SFT                       11
+#define RT5640_JD_HP_DIS                       (0x0 << 11)
+#define RT5640_JD_HP_EN                                (0x1 << 11)
+#define RT5640_JD_HP_TRG_MASK                  (0x1 << 10)
+#define RT5640_JD_HP_TRG_SFT                   10
+#define RT5640_JD_HP_TRG_LO                    (0x0 << 10)
+#define RT5640_JD_HP_TRG_HI                    (0x1 << 10)
+#define RT5640_JD_SPL_MASK                     (0x1 << 9)
+#define RT5640_JD_SPL_SFT                      9
+#define RT5640_JD_SPL_DIS                      (0x0 << 9)
+#define RT5640_JD_SPL_EN                       (0x1 << 9)
+#define RT5640_JD_SPL_TRG_MASK                 (0x1 << 8)
+#define RT5640_JD_SPL_TRG_SFT                  8
+#define RT5640_JD_SPL_TRG_LO                   (0x0 << 8)
+#define RT5640_JD_SPL_TRG_HI                   (0x1 << 8)
+#define RT5640_JD_SPR_MASK                     (0x1 << 7)
+#define RT5640_JD_SPR_SFT                      7
+#define RT5640_JD_SPR_DIS                      (0x0 << 7)
+#define RT5640_JD_SPR_EN                       (0x1 << 7)
+#define RT5640_JD_SPR_TRG_MASK                 (0x1 << 6)
+#define RT5640_JD_SPR_TRG_SFT                  6
+#define RT5640_JD_SPR_TRG_LO                   (0x0 << 6)
+#define RT5640_JD_SPR_TRG_HI                   (0x1 << 6)
+#define RT5640_JD_MO_MASK                      (0x1 << 5)
+#define RT5640_JD_MO_SFT                       5
+#define RT5640_JD_MO_DIS                       (0x0 << 5)
+#define RT5640_JD_MO_EN                        (0x1 << 5)
+#define RT5640_JD_MO_TRG_MASK                  (0x1 << 4)
+#define RT5640_JD_MO_TRG_SFT                   4
+#define RT5640_JD_MO_TRG_LO                    (0x0 << 4)
+#define RT5640_JD_MO_TRG_HI                    (0x1 << 4)
+#define RT5640_JD_LO_MASK                      (0x1 << 3)
+#define RT5640_JD_LO_SFT                       3
+#define RT5640_JD_LO_DIS                       (0x0 << 3)
+#define RT5640_JD_LO_EN                                (0x1 << 3)
+#define RT5640_JD_LO_TRG_MASK                  (0x1 << 2)
+#define RT5640_JD_LO_TRG_SFT                   2
+#define RT5640_JD_LO_TRG_LO                    (0x0 << 2)
+#define RT5640_JD_LO_TRG_HI                    (0x1 << 2)
+#define RT5640_JD1_IN4P_MASK                   (0x1 << 1)
+#define RT5640_JD1_IN4P_SFT                    1
+#define RT5640_JD1_IN4P_DIS                    (0x0 << 1)
+#define RT5640_JD1_IN4P_EN                     (0x1 << 1)
+#define RT5640_JD2_IN4N_MASK                   (0x1)
+#define RT5640_JD2_IN4N_SFT                    0
+#define RT5640_JD2_IN4N_DIS                    (0x0)
+#define RT5640_JD2_IN4N_EN                     (0x1)
+
+/* Jack detect for ANC (0xbc) */
+#define RT5640_ANC_DET_MASK                    (0x3 << 4)
+#define RT5640_ANC_DET_SFT                     4
+#define RT5640_ANC_DET_DIS                     (0x0 << 4)
+#define RT5640_ANC_DET_MB1                     (0x1 << 4)
+#define RT5640_ANC_DET_MB2                     (0x2 << 4)
+#define RT5640_ANC_DET_JD                      (0x3 << 4)
+#define RT5640_AD_TRG_MASK                     (0x1 << 3)
+#define RT5640_AD_TRG_SFT                      3
+#define RT5640_AD_TRG_LO                       (0x0 << 3)
+#define RT5640_AD_TRG_HI                       (0x1 << 3)
+#define RT5640_ANCM_DET_MASK                   (0x3 << 4)
+#define RT5640_ANCM_DET_SFT                    4
+#define RT5640_ANCM_DET_DIS                    (0x0 << 4)
+#define RT5640_ANCM_DET_MB1                    (0x1 << 4)
+#define RT5640_ANCM_DET_MB2                    (0x2 << 4)
+#define RT5640_ANCM_DET_JD                     (0x3 << 4)
+#define RT5640_AMD_TRG_MASK                    (0x1 << 3)
+#define RT5640_AMD_TRG_SFT                     3
+#define RT5640_AMD_TRG_LO                      (0x0 << 3)
+#define RT5640_AMD_TRG_HI                      (0x1 << 3)
+
+/* IRQ Control 1 (0xbd) */
+#define RT5640_IRQ_JD_MASK                     (0x1 << 15)
+#define RT5640_IRQ_JD_SFT                      15
+#define RT5640_IRQ_JD_BP                       (0x0 << 15)
+#define RT5640_IRQ_JD_NOR                      (0x1 << 15)
+#define RT5640_IRQ_OT_MASK                     (0x1 << 14)
+#define RT5640_IRQ_OT_SFT                      14
+#define RT5640_IRQ_OT_BP                       (0x0 << 14)
+#define RT5640_IRQ_OT_NOR                      (0x1 << 14)
+#define RT5640_JD_STKY_MASK                    (0x1 << 13)
+#define RT5640_JD_STKY_SFT                     13
+#define RT5640_JD_STKY_DIS                     (0x0 << 13)
+#define RT5640_JD_STKY_EN                      (0x1 << 13)
+#define RT5640_OT_STKY_MASK                    (0x1 << 12)
+#define RT5640_OT_STKY_SFT                     12
+#define RT5640_OT_STKY_DIS                     (0x0 << 12)
+#define RT5640_OT_STKY_EN                      (0x1 << 12)
+#define RT5640_JD_P_MASK                       (0x1 << 11)
+#define RT5640_JD_P_SFT                                11
+#define RT5640_JD_P_NOR                                (0x0 << 11)
+#define RT5640_JD_P_INV                                (0x1 << 11)
+#define RT5640_OT_P_MASK                       (0x1 << 10)
+#define RT5640_OT_P_SFT                                10
+#define RT5640_OT_P_NOR                        (0x0 << 10)
+#define RT5640_OT_P_INV                                (0x1 << 10)
+
+/* IRQ Control 2 (0xbe) */
+#define RT5640_IRQ_MB1_OC_MASK         (0x1 << 15)
+#define RT5640_IRQ_MB1_OC_SFT                  15
+#define RT5640_IRQ_MB1_OC_BP                   (0x0 << 15)
+#define RT5640_IRQ_MB1_OC_NOR                  (0x1 << 15)
+#define RT5640_IRQ_MB2_OC_MASK         (0x1 << 14)
+#define RT5640_IRQ_MB2_OC_SFT                  14
+#define RT5640_IRQ_MB2_OC_BP                   (0x0 << 14)
+#define RT5640_IRQ_MB2_OC_NOR                  (0x1 << 14)
+#define RT5640_MB1_OC_STKY_MASK                (0x1 << 11)
+#define RT5640_MB1_OC_STKY_SFT         11
+#define RT5640_MB1_OC_STKY_DIS         (0x0 << 11)
+#define RT5640_MB1_OC_STKY_EN                  (0x1 << 11)
+#define RT5640_MB2_OC_STKY_MASK                (0x1 << 10)
+#define RT5640_MB2_OC_STKY_SFT         10
+#define RT5640_MB2_OC_STKY_DIS         (0x0 << 10)
+#define RT5640_MB2_OC_STKY_EN                  (0x1 << 10)
+#define RT5640_MB1_OC_P_MASK                   (0x1 << 7)
+#define RT5640_MB1_OC_P_SFT                    7
+#define RT5640_MB1_OC_P_NOR                    (0x0 << 7)
+#define RT5640_MB1_OC_P_INV                    (0x1 << 7)
+#define RT5640_MB2_OC_P_MASK                   (0x1 << 6)
+#define RT5640_MB2_OC_P_SFT                    6
+#define RT5640_MB2_OC_P_NOR                    (0x0 << 6)
+#define RT5640_MB2_OC_P_INV                    (0x1 << 6)
+#define RT5640_MB1_OC_CLR                      (0x1 << 3)
+#define RT5640_MB1_OC_CLR_SFT                  3
+#define RT5640_MB2_OC_CLR                      (0x1 << 2)
+#define RT5640_MB2_OC_CLR_SFT                  2
+
+/* GPIO Control 1 (0xc0) */
+#define RT5640_GP1_PIN_MASK                    (0x1 << 15)
+#define RT5640_GP1_PIN_SFT                     15
+#define RT5640_GP1_PIN_GPIO1                   (0x0 << 15)
+#define RT5640_GP1_PIN_IRQ                     (0x1 << 15)
+#define RT5640_GP2_PIN_MASK                    (0x1 << 14)
+#define RT5640_GP2_PIN_SFT                     14
+#define RT5640_GP2_PIN_GPIO2                   (0x0 << 14)
+#define RT5640_GP2_PIN_DMIC1_SCL               (0x1 << 14)
+#define RT5640_GP3_PIN_MASK                    (0x3 << 12)
+#define RT5640_GP3_PIN_SFT                     12
+#define RT5640_GP3_PIN_GPIO3                   (0x0 << 12)
+#define RT5640_GP3_PIN_DMIC1_SDA               (0x1 << 12)
+#define RT5640_GP3_PIN_IRQ                     (0x2 << 12)
+#define RT5640_GP4_PIN_MASK                    (0x1 << 11)
+#define RT5640_GP4_PIN_SFT                     11
+#define RT5640_GP4_PIN_GPIO4                   (0x0 << 11)
+#define RT5640_GP4_PIN_DMIC2_SDA               (0x1 << 11)
+#define RT5640_DP_SIG_MASK                     (0x1 << 10)
+#define RT5640_DP_SIG_SFT                      10
+#define RT5640_DP_SIG_TEST                     (0x0 << 10)
+#define RT5640_DP_SIG_AP                       (0x1 << 10)
+#define RT5640_GPIO_M_MASK                     (0x1 << 9)
+#define RT5640_GPIO_M_SFT                      9
+#define RT5640_GPIO_M_FLT                      (0x0 << 9)
+#define RT5640_GPIO_M_PH                       (0x1 << 9)
+
+/* GPIO Control 3 (0xc2) */
+#define RT5640_GP4_PF_MASK                     (0x1 << 11)
+#define RT5640_GP4_PF_SFT                      11
+#define RT5640_GP4_PF_IN                       (0x0 << 11)
+#define RT5640_GP4_PF_OUT                      (0x1 << 11)
+#define RT5640_GP4_OUT_MASK                    (0x1 << 10)
+#define RT5640_GP4_OUT_SFT                     10
+#define RT5640_GP4_OUT_LO                      (0x0 << 10)
+#define RT5640_GP4_OUT_HI                      (0x1 << 10)
+#define RT5640_GP4_P_MASK                      (0x1 << 9)
+#define RT5640_GP4_P_SFT                       9
+#define RT5640_GP4_P_NOR                       (0x0 << 9)
+#define RT5640_GP4_P_INV                       (0x1 << 9)
+#define RT5640_GP3_PF_MASK                     (0x1 << 8)
+#define RT5640_GP3_PF_SFT                      8
+#define RT5640_GP3_PF_IN                       (0x0 << 8)
+#define RT5640_GP3_PF_OUT                      (0x1 << 8)
+#define RT5640_GP3_OUT_MASK                    (0x1 << 7)
+#define RT5640_GP3_OUT_SFT                     7
+#define RT5640_GP3_OUT_LO                      (0x0 << 7)
+#define RT5640_GP3_OUT_HI                      (0x1 << 7)
+#define RT5640_GP3_P_MASK                      (0x1 << 6)
+#define RT5640_GP3_P_SFT                       6
+#define RT5640_GP3_P_NOR                       (0x0 << 6)
+#define RT5640_GP3_P_INV                       (0x1 << 6)
+#define RT5640_GP2_PF_MASK                     (0x1 << 5)
+#define RT5640_GP2_PF_SFT                      5
+#define RT5640_GP2_PF_IN                       (0x0 << 5)
+#define RT5640_GP2_PF_OUT                      (0x1 << 5)
+#define RT5640_GP2_OUT_MASK                    (0x1 << 4)
+#define RT5640_GP2_OUT_SFT                     4
+#define RT5640_GP2_OUT_LO                      (0x0 << 4)
+#define RT5640_GP2_OUT_HI                      (0x1 << 4)
+#define RT5640_GP2_P_MASK                      (0x1 << 3)
+#define RT5640_GP2_P_SFT                       3
+#define RT5640_GP2_P_NOR                       (0x0 << 3)
+#define RT5640_GP2_P_INV                       (0x1 << 3)
+#define RT5640_GP1_PF_MASK                     (0x1 << 2)
+#define RT5640_GP1_PF_SFT                      2
+#define RT5640_GP1_PF_IN                       (0x0 << 2)
+#define RT5640_GP1_PF_OUT                      (0x1 << 2)
+#define RT5640_GP1_OUT_MASK                    (0x1 << 1)
+#define RT5640_GP1_OUT_SFT                     1
+#define RT5640_GP1_OUT_LO                      (0x0 << 1)
+#define RT5640_GP1_OUT_HI                      (0x1 << 1)
+#define RT5640_GP1_P_MASK                      (0x1)
+#define RT5640_GP1_P_SFT                       0
+#define RT5640_GP1_P_NOR                       (0x0)
+#define RT5640_GP1_P_INV                       (0x1)
+
+/* FM34-500 Register Control 1 (0xc4) */
+#define RT5640_DSP_ADD_SFT                     0
+
+/* FM34-500 Register Control 2 (0xc5) */
+#define RT5640_DSP_DAT_SFT                     0
+
+/* FM34-500 Register Control 3 (0xc6) */
+#define RT5640_DSP_BUSY_MASK                   (0x1 << 15)
+#define RT5640_DSP_BUSY_BIT                    15
+#define RT5640_DSP_DS_MASK                     (0x1 << 14)
+#define RT5640_DSP_DS_SFT                      14
+#define RT5640_DSP_DS_FM3010                   (0x1 << 14)
+#define RT5640_DSP_DS_TEMP                     (0x1 << 14)
+#define RT5640_DSP_CLK_MASK                    (0x3 << 12)
+#define RT5640_DSP_CLK_SFT                     12
+#define RT5640_DSP_CLK_384K                    (0x0 << 12)
+#define RT5640_DSP_CLK_192K                    (0x1 << 12)
+#define RT5640_DSP_CLK_96K                     (0x2 << 12)
+#define RT5640_DSP_CLK_64K                     (0x3 << 12)
+#define RT5640_DSP_PD_PIN_MASK         (0x1 << 11)
+#define RT5640_DSP_PD_PIN_SFT                  11
+#define RT5640_DSP_PD_PIN_LO                   (0x0 << 11)
+#define RT5640_DSP_PD_PIN_HI                   (0x1 << 11)
+#define RT5640_DSP_RST_PIN_MASK                (0x1 << 10)
+#define RT5640_DSP_RST_PIN_SFT                 10
+#define RT5640_DSP_RST_PIN_LO                  (0x0 << 10)
+#define RT5640_DSP_RST_PIN_HI                  (0x1 << 10)
+#define RT5640_DSP_R_EN                                (0x1 << 9)
+#define RT5640_DSP_R_EN_BIT                    9
+#define RT5640_DSP_W_EN                        (0x1 << 8)
+#define RT5640_DSP_W_EN_BIT                    8
+#define RT5640_DSP_CMD_MASK                    (0xff)
+#define RT5640_DSP_CMD_SFT                     0
+#define RT5640_DSP_CMD_MW                      (0x3B)  /* Memory Write */
+#define RT5640_DSP_CMD_MR                      (0x37)  /* Memory Read */
+#define RT5640_DSP_CMD_RR                      (0x60)  /* Register Read */
+#define RT5640_DSP_CMD_RW                      (0x68)  /* Register Write */
+
+/* Programmable Register Array Control 1 (0xc8) */
+#define RT5640_REG_SEQ_MASK                    (0xf << 12)
+#define RT5640_REG_SEQ_SFT                     12
+#define RT5640_SEQ1_ST_MASK                    (0x1 << 11) /*RO*/
+#define RT5640_SEQ1_ST_SFT                     11
+#define RT5640_SEQ1_ST_RUN                     (0x0 << 11)
+#define RT5640_SEQ1_ST_FIN                     (0x1 << 11)
+#define RT5640_SEQ2_ST_MASK                    (0x1 << 10) /*RO*/
+#define RT5640_SEQ2_ST_SFT                     10
+#define RT5640_SEQ2_ST_RUN                     (0x0 << 10)
+#define RT5640_SEQ2_ST_FIN                     (0x1 << 10)
+#define RT5640_REG_LV_MASK                     (0x1 << 9)
+#define RT5640_REG_LV_SFT                      9
+#define RT5640_REG_LV_MX                       (0x0 << 9)
+#define RT5640_REG_LV_PR                       (0x1 << 9)
+#define RT5640_SEQ_2_PT_MASK                   (0x1 << 8)
+#define RT5640_SEQ_2_PT_BIT                    8
+#define RT5640_REG_IDX_MASK                    (0xff)
+#define RT5640_REG_IDX_SFT                     0
+
+/* Programmable Register Array Control 2 (0xc9) */
+#define RT5640_REG_DAT_MASK                    (0xffff)
+#define RT5640_REG_DAT_SFT                     0
+
+/* Programmable Register Array Control 3 (0xca) */
+#define RT5640_SEQ_DLY_MASK                    (0xff << 8)
+#define RT5640_SEQ_DLY_SFT                     8
+#define RT5640_PROG_MASK                       (0x1 << 7)
+#define RT5640_PROG_SFT                                7
+#define RT5640_PROG_DIS                                (0x0 << 7)
+#define RT5640_PROG_EN                         (0x1 << 7)
+#define RT5640_SEQ1_PT_RUN                     (0x1 << 6)
+#define RT5640_SEQ1_PT_RUN_BIT                 6
+#define RT5640_SEQ2_PT_RUN                     (0x1 << 5)
+#define RT5640_SEQ2_PT_RUN_BIT                 5
+
+/* Programmable Register Array Control 4 (0xcb) */
+#define RT5640_SEQ1_START_MASK         (0xf << 8)
+#define RT5640_SEQ1_START_SFT                  8
+#define RT5640_SEQ1_END_MASK                   (0xf)
+#define RT5640_SEQ1_END_SFT                    0
+
+/* Programmable Register Array Control 5 (0xcc) */
+#define RT5640_SEQ2_START_MASK         (0xf << 8)
+#define RT5640_SEQ2_START_SFT                  8
+#define RT5640_SEQ2_END_MASK                   (0xf)
+#define RT5640_SEQ2_END_SFT                    0
+
+/* Scramble Function (0xcd) */
+#define RT5640_SCB_KEY_MASK                    (0xff)
+#define RT5640_SCB_KEY_SFT                     0
+
+/* Scramble Control (0xce) */
+#define RT5640_SCB_SWAP_MASK                   (0x1 << 15)
+#define RT5640_SCB_SWAP_SFT                    15
+#define RT5640_SCB_SWAP_DIS                    (0x0 << 15)
+#define RT5640_SCB_SWAP_EN                     (0x1 << 15)
+#define RT5640_SCB_MASK                        (0x1 << 14)
+#define RT5640_SCB_SFT                         14
+#define RT5640_SCB_DIS                         (0x0 << 14)
+#define RT5640_SCB_EN                          (0x1 << 14)
+
+/* Baseback Control (0xcf) */
+#define RT5640_BB_MASK                         (0x1 << 15)
+#define RT5640_BB_SFT                          15
+#define RT5640_BB_DIS                          (0x0 << 15)
+#define RT5640_BB_EN                           (0x1 << 15)
+#define RT5640_BB_CT_MASK                      (0x7 << 12)
+#define RT5640_BB_CT_SFT                       12
+#define RT5640_BB_CT_A                         (0x0 << 12)
+#define RT5640_BB_CT_B                         (0x1 << 12)
+#define RT5640_BB_CT_C                         (0x2 << 12)
+#define RT5640_BB_CT_D                         (0x3 << 12)
+#define RT5640_M_BB_L_MASK                     (0x1 << 9)
+#define RT5640_M_BB_L_SFT                      9
+#define RT5640_M_BB_R_MASK                     (0x1 << 8)
+#define RT5640_M_BB_R_SFT                      8
+#define RT5640_M_BB_HPF_L_MASK         (0x1 << 7)
+#define RT5640_M_BB_HPF_L_SFT                  7
+#define RT5640_M_BB_HPF_R_MASK         (0x1 << 6)
+#define RT5640_M_BB_HPF_R_SFT                  6
+#define RT5640_G_BB_BST_MASK                   (0x3f)
+#define RT5640_G_BB_BST_SFT                    0
+
+/* MP3 Plus Control 1 (0xd0) */
+#define RT5640_M_MP3_L_MASK                    (0x1 << 15)
+#define RT5640_M_MP3_L_SFT                     15
+#define RT5640_M_MP3_R_MASK                    (0x1 << 14)
+#define RT5640_M_MP3_R_SFT                     14
+#define RT5640_M_MP3_MASK                      (0x1 << 13)
+#define RT5640_M_MP3_SFT                       13
+#define RT5640_M_MP3_DIS                       (0x0 << 13)
+#define RT5640_M_MP3_EN                        (0x1 << 13)
+#define RT5640_EG_MP3_MASK                     (0x1f << 8)
+#define RT5640_EG_MP3_SFT                      8
+#define RT5640_MP3_HLP_MASK                    (0x1 << 7)
+#define RT5640_MP3_HLP_SFT                     7
+#define RT5640_MP3_HLP_DIS                     (0x0 << 7)
+#define RT5640_MP3_HLP_EN                      (0x1 << 7)
+#define RT5640_M_MP3_ORG_L_MASK                (0x1 << 6)
+#define RT5640_M_MP3_ORG_L_SFT         6
+#define RT5640_M_MP3_ORG_R_MASK                (0x1 << 5)
+#define RT5640_M_MP3_ORG_R_SFT         5
+
+/* MP3 Plus Control 2 (0xd1) */
+#define RT5640_MP3_WT_MASK                     (0x1 << 13)
+#define RT5640_MP3_WT_SFT                      13
+#define RT5640_MP3_WT_1_4                      (0x0 << 13)
+#define RT5640_MP3_WT_1_2                      (0x1 << 13)
+#define RT5640_OG_MP3_MASK                     (0x1f << 8)
+#define RT5640_OG_MP3_SFT                      8
+#define RT5640_HG_MP3_MASK                     (0x3f)
+#define RT5640_HG_MP3_SFT                      0
+
+/* 3D HP Control 1 (0xd2) */
+#define RT5640_3D_CF_MASK                      (0x1 << 15)
+#define RT5640_3D_CF_SFT                       15
+#define RT5640_3D_CF_DIS                       (0x0 << 15)
+#define RT5640_3D_CF_EN                        (0x1 << 15)
+#define RT5640_3D_HP_MASK                      (0x1 << 14)
+#define RT5640_3D_HP_SFT                       14
+#define RT5640_3D_HP_DIS                       (0x0 << 14)
+#define RT5640_3D_HP_EN                        (0x1 << 14)
+#define RT5640_3D_BT_MASK                      (0x1 << 13)
+#define RT5640_3D_BT_SFT                       13
+#define RT5640_3D_BT_DIS                       (0x0 << 13)
+#define RT5640_3D_BT_EN                                (0x1 << 13)
+#define RT5640_3D_1F_MIX_MASK                  (0x3 << 11)
+#define RT5640_3D_1F_MIX_SFT                   11
+#define RT5640_3D_HP_M_MASK                    (0x1 << 10)
+#define RT5640_3D_HP_M_SFT                     10
+#define RT5640_3D_HP_M_SUR                     (0x0 << 10)
+#define RT5640_3D_HP_M_FRO                     (0x1 << 10)
+#define RT5640_M_3D_HRTF_MASK                  (0x1 << 9)
+#define RT5640_M_3D_HRTF_SFT                   9
+#define RT5640_M_3D_D2H_MASK                   (0x1 << 8)
+#define RT5640_M_3D_D2H_SFT                    8
+#define RT5640_M_3D_D2R_MASK                   (0x1 << 7)
+#define RT5640_M_3D_D2R_SFT                    7
+#define RT5640_M_3D_REVB_MASK                  (0x1 << 6)
+#define RT5640_M_3D_REVB_SFT                   6
+
+/* Adjustable high pass filter control 1 (0xd3) */
+#define RT5640_2ND_HPF_MASK                    (0x1 << 15)
+#define RT5640_2ND_HPF_SFT                     15
+#define RT5640_2ND_HPF_DIS                     (0x0 << 15)
+#define RT5640_2ND_HPF_EN                      (0x1 << 15)
+#define RT5640_HPF_CF_L_MASK                   (0x7 << 12)
+#define RT5640_HPF_CF_L_SFT                    12
+#define RT5640_1ST_HPF_MASK                    (0x1 << 11)
+#define RT5640_1ST_HPF_SFT                     11
+#define RT5640_1ST_HPF_DIS                     (0x0 << 11)
+#define RT5640_1ST_HPF_EN                      (0x1 << 11)
+#define RT5640_HPF_CF_R_MASK                   (0x7 << 8)
+#define RT5640_HPF_CF_R_SFT                    8
+#define RT5640_ZD_T_MASK                       (0x3 << 6)
+#define RT5640_ZD_T_SFT                                6
+#define RT5640_ZD_F_MASK                       (0x3 << 4)
+#define RT5640_ZD_F_SFT                                4
+#define RT5640_ZD_F_IM                         (0x0 << 4)
+#define RT5640_ZD_F_ZC_IM                      (0x1 << 4)
+#define RT5640_ZD_F_ZC_IOD                     (0x2 << 4)
+#define RT5640_ZD_F_UN                         (0x3 << 4)
+
+/* HP calibration control and Amp detection (0xd6) */
+#define RT5640_SI_DAC_MASK                     (0x1 << 11)
+#define RT5640_SI_DAC_SFT                      11
+#define RT5640_SI_DAC_AUTO                     (0x0 << 11)
+#define RT5640_SI_DAC_TEST                     (0x1 << 11)
+#define RT5640_DC_CAL_M_MASK                   (0x1 << 10)
+#define RT5640_DC_CAL_M_SFT                    10
+#define RT5640_DC_CAL_M_CAL                    (0x0 << 10)
+#define RT5640_DC_CAL_M_NOR                    (0x1 << 10)
+#define RT5640_DC_CAL_MASK                     (0x1 << 9)
+#define RT5640_DC_CAL_SFT                      9
+#define RT5640_DC_CAL_DIS                      (0x0 << 9)
+#define RT5640_DC_CAL_EN                       (0x1 << 9)
+#define RT5640_HPD_RCV_MASK                    (0x7 << 6)
+#define RT5640_HPD_RCV_SFT                     6
+#define RT5640_HPD_PS_MASK                     (0x1 << 5)
+#define RT5640_HPD_PS_SFT                      5
+#define RT5640_HPD_PS_DIS                      (0x0 << 5)
+#define RT5640_HPD_PS_EN                       (0x1 << 5)
+#define RT5640_CAL_M_MASK                      (0x1 << 4)
+#define RT5640_CAL_M_SFT                       4
+#define RT5640_CAL_M_DEP                       (0x0 << 4)
+#define RT5640_CAL_M_CAL                       (0x1 << 4)
+#define RT5640_CAL_MASK                        (0x1 << 3)
+#define RT5640_CAL_SFT                         3
+#define RT5640_CAL_DIS                         (0x0 << 3)
+#define RT5640_CAL_EN                          (0x1 << 3)
+#define RT5640_CAL_TEST_MASK                   (0x1 << 2)
+#define RT5640_CAL_TEST_SFT                    2
+#define RT5640_CAL_TEST_DIS                    (0x0 << 2)
+#define RT5640_CAL_TEST_EN                     (0x1 << 2)
+#define RT5640_CAL_P_MASK                      (0x3)
+#define RT5640_CAL_P_SFT                       0
+#define RT5640_CAL_P_NONE                      (0x0)
+#define RT5640_CAL_P_CAL                       (0x1)
+#define RT5640_CAL_P_DAC_CAL                   (0x2)
+
+/* Soft volume and zero cross control 1 (0xd9) */
+#define RT5640_SV_MASK                         (0x1 << 15)
+#define RT5640_SV_SFT                          15
+#define RT5640_SV_DIS                          (0x0 << 15)
+#define RT5640_SV_EN                           (0x1 << 15)
+#define RT5640_SPO_SV_MASK                     (0x1 << 14)
+#define RT5640_SPO_SV_SFT                      14
+#define RT5640_SPO_SV_DIS                      (0x0 << 14)
+#define RT5640_SPO_SV_EN                       (0x1 << 14)
+#define RT5640_OUT_SV_MASK                     (0x1 << 13)
+#define RT5640_OUT_SV_SFT                      13
+#define RT5640_OUT_SV_DIS                      (0x0 << 13)
+#define RT5640_OUT_SV_EN                       (0x1 << 13)
+#define RT5640_HP_SV_MASK                      (0x1 << 12)
+#define RT5640_HP_SV_SFT                       12
+#define RT5640_HP_SV_DIS                       (0x0 << 12)
+#define RT5640_HP_SV_EN                        (0x1 << 12)
+#define RT5640_ZCD_DIG_MASK                    (0x1 << 11)
+#define RT5640_ZCD_DIG_SFT                     11
+#define RT5640_ZCD_DIG_DIS                     (0x0 << 11)
+#define RT5640_ZCD_DIG_EN                      (0x1 << 11)
+#define RT5640_ZCD_MASK                        (0x1 << 10)
+#define RT5640_ZCD_SFT                         10
+#define RT5640_ZCD_PD                          (0x0 << 10)
+#define RT5640_ZCD_PU                          (0x1 << 10)
+#define RT5640_M_ZCD_MASK                      (0x3f << 4)
+#define RT5640_M_ZCD_SFT                       4
+#define RT5640_M_ZCD_RM_L                      (0x1 << 9)
+#define RT5640_M_ZCD_RM_R                      (0x1 << 8)
+#define RT5640_M_ZCD_SM_L                      (0x1 << 7)
+#define RT5640_M_ZCD_SM_R                      (0x1 << 6)
+#define RT5640_M_ZCD_OM_L                      (0x1 << 5)
+#define RT5640_M_ZCD_OM_R                      (0x1 << 4)
+#define RT5640_SV_DLY_MASK                     (0xf)
+#define RT5640_SV_DLY_SFT                      0
+
+/* Soft volume and zero cross control 2 (0xda) */
+#define RT5640_ZCD_HP_MASK                     (0x1 << 15)
+#define RT5640_ZCD_HP_SFT                      15
+#define RT5640_ZCD_HP_DIS                      (0x0 << 15)
+#define RT5640_ZCD_HP_EN                       (0x1 << 15)
+
+
+/* Codec Private Register definition */
+/* 3D Speaker Control (0x63) */
+#define RT5640_3D_SPK_MASK                     (0x1 << 15)
+#define RT5640_3D_SPK_SFT                      15
+#define RT5640_3D_SPK_DIS                      (0x0 << 15)
+#define RT5640_3D_SPK_EN                       (0x1 << 15)
+#define RT5640_3D_SPK_M_MASK                   (0x3 << 13)
+#define RT5640_3D_SPK_M_SFT                    13
+#define RT5640_3D_SPK_CG_MASK                  (0x1f << 8)
+#define RT5640_3D_SPK_CG_SFT                   8
+#define RT5640_3D_SPK_SG_MASK                  (0x1f)
+#define RT5640_3D_SPK_SG_SFT                   0
+
+/* Wind Noise Detection Control 1 (0x6c) */
+#define RT5640_WND_MASK                        (0x1 << 15)
+#define RT5640_WND_SFT                         15
+#define RT5640_WND_DIS                         (0x0 << 15)
+#define RT5640_WND_EN                          (0x1 << 15)
+
+/* Wind Noise Detection Control 2 (0x6d) */
+#define RT5640_WND_FC_NW_MASK          (0x3f << 10)
+#define RT5640_WND_FC_NW_SFT                   10
+#define RT5640_WND_FC_WK_MASK          (0x3f << 4)
+#define RT5640_WND_FC_WK_SFT                   4
+
+/* Wind Noise Detection Control 3 (0x6e) */
+#define RT5640_HPF_FC_MASK                     (0x3f << 6)
+#define RT5640_HPF_FC_SFT                      6
+#define RT5640_WND_FC_ST_MASK                  (0x3f)
+#define RT5640_WND_FC_ST_SFT                   0
+
+/* Wind Noise Detection Control 4 (0x6f) */
+#define RT5640_WND_TH_LO_MASK          (0x3ff)
+#define RT5640_WND_TH_LO_SFT                   0
+
+/* Wind Noise Detection Control 5 (0x70) */
+#define RT5640_WND_TH_HI_MASK                  (0x3ff)
+#define RT5640_WND_TH_HI_SFT                   0
+
+/* Wind Noise Detection Control 8 (0x73) */
+#define RT5640_WND_WIND_MASK                   (0x1 << 13) /* Read-Only */
+#define RT5640_WND_WIND_SFT                    13
+#define RT5640_WND_STRONG_MASK         (0x1 << 12) /* Read-Only */
+#define RT5640_WND_STRONG_SFT                  12
+enum {
+       RT5640_NO_WIND,
+       RT5640_BREEZE,
+       RT5640_STORM,
+};
+
+/* Dipole Speaker Interface (0x75) */
+#define RT5640_DP_ATT_MASK                     (0x3 << 14)
+#define RT5640_DP_ATT_SFT                      14
+#define RT5640_DP_SPK_MASK                     (0x1 << 10)
+#define RT5640_DP_SPK_SFT                      10
+#define RT5640_DP_SPK_DIS                      (0x0 << 10)
+#define RT5640_DP_SPK_EN                       (0x1 << 10)
+
+/* EQ Pre Volume Control (0xb3) */
+#define RT5640_EQ_PRE_VOL_MASK         (0xffff)
+#define RT5640_EQ_PRE_VOL_SFT                  0
+
+/* EQ Post Volume Control (0xb4) */
+#define RT5640_EQ_PST_VOL_MASK         (0xffff)
+#define RT5640_EQ_PST_VOL_SFT                  0
+
+
+
+/* System Clock Source */
+#define RT5640_SCLK_S_MCLK 0
+#define RT5640_SCLK_S_PLL1 1
+#define RT5640_SCLK_S_PLL1_TK 2
+#define RT5640_SCLK_S_RCCLK 3
+
+/* PLL1 Source */
+#define RT5640_PLL1_S_MCLK 0
+#define RT5640_PLL1_S_BCLK1 1
+#define RT5640_PLL1_S_BCLK2 2
+#define RT5640_PLL1_S_BCLK3 3
+
+
+enum {
+       RT5640_AIF1,
+       RT5640_AIF2,
+       RT5640_AIF3,
+       RT5640_AIFS,
+};
+
+enum {
+       RT5640_U_IF1 = 0x1,
+       RT5640_U_IF2 = 0x2,
+       RT5640_U_IF3 = 0x4,
+};
+
+enum {
+       RT5640_IF_123,
+       RT5640_IF_132,
+       RT5640_IF_312,
+       RT5640_IF_321,
+       RT5640_IF_231,
+       RT5640_IF_213,
+       RT5640_IF_113,
+       RT5640_IF_223,
+       RT5640_IF_ALL,
+};
+
+enum {
+       RT5640_DMIC_DIS,
+       RT5640_DMIC1,
+       RT5640_DMIC2,
+};
+
+struct rt5640_pll_code {
+       bool m_bp; /* Indicates bypass m code or not. */
+       int m_code;
+       int n_code;
+       int k_code;
+};
+
+struct rt5640_priv {
+       struct snd_soc_codec *codec;
+
+       int aif_pu;
+       int sysclk;
+       int sysclk_src;
+       int lrck[RT5640_AIFS];
+       int bclk[RT5640_AIFS];
+       int master[RT5640_AIFS];
+
+       int pll_src;
+       int pll_in;
+       int pll_out;
+
+       int dmic_en;
+       int dsp_sw;
+};
+
+
+#endif /* __RT5640_H__ */