drm/radeon/kms: rename gpu_reset to asic_reset
Jerome Glisse [Tue, 9 Mar 2010 14:45:11 +0000 (14:45 +0000)]
Patch rename gpu_reset to asic_reset in prevision of having
gpu_reset doing more stuff than just basic asic reset.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

15 files changed:
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/r300.c
drivers/gpu/drm/radeon/r420.c
drivers/gpu/drm/radeon/r520.c
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/radeon_asic.h
drivers/gpu/drm/radeon/radeon_device.c
drivers/gpu/drm/radeon/radeon_fence.c
drivers/gpu/drm/radeon/rs400.c
drivers/gpu/drm/radeon/rs600.c
drivers/gpu/drm/radeon/rs690.c
drivers/gpu/drm/radeon/rv515.c

index 3070e59..7672f11 100644 (file)
@@ -492,7 +492,7 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
        return false;
 }
 
-int evergreen_gpu_reset(struct radeon_device *rdev)
+int evergreen_asic_reset(struct radeon_device *rdev)
 {
        /* FIXME: implement for evergreen */
        return 0;
index 845c8f3..8bb9109 100644 (file)
@@ -1863,7 +1863,7 @@ bool r100_gpu_is_lockup(struct radeon_device *rdev)
        return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
 }
 
-int r100_gpu_reset(struct radeon_device *rdev)
+int r100_asic_reset(struct radeon_device *rdev)
 {
        uint32_t status;
 
@@ -3512,7 +3512,7 @@ int r100_resume(struct radeon_device *rdev)
        /* Resume clock before doing reset */
        r100_clock_startup(rdev);
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
                        RREG32(R_0007C0_CP_STAT));
@@ -3581,7 +3581,7 @@ int r100_init(struct radeon_device *rdev)
                        return r;
        }
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev,
                        "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
index 9825fb1..7d5de5d 100644 (file)
@@ -449,7 +449,7 @@ bool r300_gpu_is_lockup(struct radeon_device *rdev)
        return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
 }
 
-int r300_gpu_reset(struct radeon_device *rdev)
+int r300_asic_reset(struct radeon_device *rdev)
 {
        uint32_t status;
 
@@ -1333,7 +1333,7 @@ int r300_resume(struct radeon_device *rdev)
        /* Resume clock before doing reset */
        r300_clock_startup(rdev);
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
                        RREG32(R_0007C0_CP_STAT));
@@ -1404,7 +1404,7 @@ int r300_init(struct radeon_device *rdev)
                        return r;
        }
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev,
                        "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
index 0b8603c..061553a 100644 (file)
@@ -234,7 +234,7 @@ int r420_resume(struct radeon_device *rdev)
        /* Resume clock before doing reset */
        r420_clock_resume(rdev);
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
                        RREG32(R_0007C0_CP_STAT));
@@ -315,7 +315,7 @@ int r420_init(struct radeon_device *rdev)
                }
        }
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev,
                        "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
index 3c44b8d..3ade473 100644 (file)
@@ -209,7 +209,7 @@ int r520_resume(struct radeon_device *rdev)
        /* Resume clock before doing reset */
        rv515_clock_startup(rdev);
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
                        RREG32(R_0007C0_CP_STAT));
@@ -246,7 +246,7 @@ int r520_init(struct radeon_device *rdev)
                return -EINVAL;
        }
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev,
                        "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
index a09c062..24fd545 100644 (file)
@@ -874,7 +874,7 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev)
        return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
 }
 
-int r600_gpu_reset(struct radeon_device *rdev)
+int r600_asic_reset(struct radeon_device *rdev)
 {
        return r600_gpu_soft_reset(rdev);
 }
index a3d13c3..3cc5820 100644 (file)
@@ -748,7 +748,7 @@ struct radeon_asic {
        int (*suspend)(struct radeon_device *rdev);
        void (*vga_set_state)(struct radeon_device *rdev, bool state);
        bool (*gpu_is_lockup)(struct radeon_device *rdev);
-       int (*gpu_reset)(struct radeon_device *rdev);
+       int (*asic_reset)(struct radeon_device *rdev);
        void (*gart_tlb_flush)(struct radeon_device *rdev);
        int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
        int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
@@ -1157,7 +1157,7 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
-#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
+#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
@@ -1290,7 +1290,7 @@ extern void r600_scratch_init(struct radeon_device *rdev);
 extern int r600_blit_init(struct radeon_device *rdev);
 extern void r600_blit_fini(struct radeon_device *rdev);
 extern int r600_init_microcode(struct radeon_device *rdev);
-extern int r600_gpu_reset(struct radeon_device *rdev);
+extern int r600_asic_reset(struct radeon_device *rdev);
 /* r600 irq */
 extern int r600_irq_init(struct radeon_device *rdev);
 extern void r600_irq_fini(struct radeon_device *rdev);
index 7e21985..011ac6d 100644 (file)
@@ -135,7 +135,7 @@ static struct radeon_asic r100_asic = {
        .resume = &r100_resume,
        .vga_set_state = &r100_vga_set_state,
        .gpu_is_lockup = &r100_gpu_is_lockup,
-       .gpu_reset = &r100_gpu_reset,
+       .asic_reset = &r100_asic_reset,
        .gart_tlb_flush = &r100_pci_gart_tlb_flush,
        .gart_set_page = &r100_pci_gart_set_page,
        .cp_commit = &r100_cp_commit,
@@ -174,7 +174,7 @@ static struct radeon_asic r200_asic = {
        .resume = &r100_resume,
        .vga_set_state = &r100_vga_set_state,
        .gpu_is_lockup = &r100_gpu_is_lockup,
-       .gpu_reset = &r100_gpu_reset,
+       .asic_reset = &r100_asic_reset,
        .gart_tlb_flush = &r100_pci_gart_tlb_flush,
        .gart_set_page = &r100_pci_gart_set_page,
        .cp_commit = &r100_cp_commit,
@@ -212,7 +212,7 @@ static struct radeon_asic r300_asic = {
        .resume = &r300_resume,
        .vga_set_state = &r100_vga_set_state,
        .gpu_is_lockup = &r300_gpu_is_lockup,
-       .gpu_reset = &r300_gpu_reset,
+       .asic_reset = &r300_asic_reset,
        .gart_tlb_flush = &r100_pci_gart_tlb_flush,
        .gart_set_page = &r100_pci_gart_set_page,
        .cp_commit = &r100_cp_commit,
@@ -251,7 +251,7 @@ static struct radeon_asic r300_asic_pcie = {
        .resume = &r300_resume,
        .vga_set_state = &r100_vga_set_state,
        .gpu_is_lockup = &r300_gpu_is_lockup,
-       .gpu_reset = &r300_gpu_reset,
+       .asic_reset = &r300_asic_reset,
        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
        .gart_set_page = &rv370_pcie_gart_set_page,
        .cp_commit = &r100_cp_commit,
@@ -289,7 +289,7 @@ static struct radeon_asic r420_asic = {
        .resume = &r420_resume,
        .vga_set_state = &r100_vga_set_state,
        .gpu_is_lockup = &r300_gpu_is_lockup,
-       .gpu_reset = &r300_gpu_reset,
+       .asic_reset = &r300_asic_reset,
        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
        .gart_set_page = &rv370_pcie_gart_set_page,
        .cp_commit = &r100_cp_commit,
@@ -328,7 +328,7 @@ static struct radeon_asic rs400_asic = {
        .resume = &rs400_resume,
        .vga_set_state = &r100_vga_set_state,
        .gpu_is_lockup = &r300_gpu_is_lockup,
-       .gpu_reset = &r300_gpu_reset,
+       .asic_reset = &r300_asic_reset,
        .gart_tlb_flush = &rs400_gart_tlb_flush,
        .gart_set_page = &rs400_gart_set_page,
        .cp_commit = &r100_cp_commit,
@@ -367,7 +367,7 @@ static struct radeon_asic rs600_asic = {
        .resume = &rs600_resume,
        .vga_set_state = &r100_vga_set_state,
        .gpu_is_lockup = &r300_gpu_is_lockup,
-       .gpu_reset = &r300_gpu_reset,
+       .asic_reset = &r300_asic_reset,
        .gart_tlb_flush = &rs600_gart_tlb_flush,
        .gart_set_page = &rs600_gart_set_page,
        .cp_commit = &r100_cp_commit,
@@ -406,7 +406,7 @@ static struct radeon_asic rs690_asic = {
        .resume = &rs690_resume,
        .vga_set_state = &r100_vga_set_state,
        .gpu_is_lockup = &r300_gpu_is_lockup,
-       .gpu_reset = &r300_gpu_reset,
+       .asic_reset = &r300_asic_reset,
        .gart_tlb_flush = &rs400_gart_tlb_flush,
        .gart_set_page = &rs400_gart_set_page,
        .cp_commit = &r100_cp_commit,
@@ -445,7 +445,7 @@ static struct radeon_asic rv515_asic = {
        .resume = &rv515_resume,
        .vga_set_state = &r100_vga_set_state,
        .gpu_is_lockup = &r300_gpu_is_lockup,
-       .gpu_reset = &rv515_gpu_reset,
+       .asic_reset = &rv515_asic_reset,
        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
        .gart_set_page = &rv370_pcie_gart_set_page,
        .cp_commit = &r100_cp_commit,
@@ -484,7 +484,7 @@ static struct radeon_asic r520_asic = {
        .resume = &r520_resume,
        .vga_set_state = &r100_vga_set_state,
        .gpu_is_lockup = &r300_gpu_is_lockup,
-       .gpu_reset = &rv515_gpu_reset,
+       .asic_reset = &rv515_asic_reset,
        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
        .gart_set_page = &rv370_pcie_gart_set_page,
        .cp_commit = &r100_cp_commit,
@@ -524,7 +524,7 @@ static struct radeon_asic r600_asic = {
        .cp_commit = &r600_cp_commit,
        .vga_set_state = &r600_vga_set_state,
        .gpu_is_lockup = &r600_gpu_is_lockup,
-       .gpu_reset = &r600_gpu_reset,
+       .asic_reset = &r600_asic_reset,
        .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
        .gart_set_page = &rs600_gart_set_page,
        .ring_test = &r600_ring_test,
@@ -561,7 +561,7 @@ static struct radeon_asic rs780_asic = {
        .resume = &r600_resume,
        .cp_commit = &r600_cp_commit,
        .vga_set_state = &r600_vga_set_state,
-       .gpu_reset = &r600_gpu_reset,
+       .asic_reset = &r600_asic_reset,
        .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
        .gart_set_page = &rs600_gart_set_page,
        .ring_test = &r600_ring_test,
@@ -597,7 +597,7 @@ static struct radeon_asic rv770_asic = {
        .suspend = &rv770_suspend,
        .resume = &rv770_resume,
        .cp_commit = &r600_cp_commit,
-       .gpu_reset = &r600_gpu_reset,
+       .asic_reset = &r600_asic_reset,
        .gpu_is_lockup = &r600_gpu_is_lockup,
        .vga_set_state = &r600_vga_set_state,
        .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
@@ -636,7 +636,7 @@ static struct radeon_asic evergreen_asic = {
        .resume = &evergreen_resume,
        .cp_commit = NULL,
        .gpu_is_lockup = &evergreen_gpu_is_lockup,
-       .gpu_reset = &evergreen_gpu_reset,
+       .asic_reset = &evergreen_asic_reset,
        .vga_set_state = &r600_vga_set_state,
        .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
        .gart_set_page = &rs600_gart_set_page,
index ce2f3e4..53ebcac 100644 (file)
@@ -61,7 +61,7 @@ uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 void r100_vga_set_state(struct radeon_device *rdev, bool state);
 bool r100_gpu_is_lockup(struct radeon_device *rdev);
-int r100_gpu_reset(struct radeon_device *rdev);
+int r100_asic_reset(struct radeon_device *rdev);
 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
@@ -145,7 +145,7 @@ extern void r300_fini(struct radeon_device *rdev);
 extern int r300_suspend(struct radeon_device *rdev);
 extern int r300_resume(struct radeon_device *rdev);
 extern bool r300_gpu_is_lockup(struct radeon_device *rdev);
-extern int r300_gpu_reset(struct radeon_device *rdev);
+extern int r300_asic_reset(struct radeon_device *rdev);
 extern void r300_ring_start(struct radeon_device *rdev);
 extern void r300_fence_ring_emit(struct radeon_device *rdev,
                                struct radeon_fence *fence);
@@ -214,7 +214,7 @@ void rs690_bandwidth_update(struct radeon_device *rdev);
  */
 int rv515_init(struct radeon_device *rdev);
 void rv515_fini(struct radeon_device *rdev);
-int rv515_gpu_reset(struct radeon_device *rdev);
+int rv515_asic_reset(struct radeon_device *rdev);
 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 void rv515_ring_start(struct radeon_device *rdev);
@@ -255,7 +255,7 @@ int r600_copy_dma(struct radeon_device *rdev,
 int r600_irq_process(struct radeon_device *rdev);
 int r600_irq_set(struct radeon_device *rdev);
 bool r600_gpu_is_lockup(struct radeon_device *rdev);
-int r600_gpu_reset(struct radeon_device *rdev);
+int r600_asic_reset(struct radeon_device *rdev);
 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
                         uint32_t tiling_flags, uint32_t pitch,
                         uint32_t offset, uint32_t obj_size);
@@ -288,7 +288,7 @@ void evergreen_fini(struct radeon_device *rdev);
 int evergreen_suspend(struct radeon_device *rdev);
 int evergreen_resume(struct radeon_device *rdev);
 bool evergreen_gpu_is_lockup(struct radeon_device *rdev);
-int evergreen_gpu_reset(struct radeon_device *rdev);
+int evergreen_asic_reset(struct radeon_device *rdev);
 void evergreen_bandwidth_update(struct radeon_device *rdev);
 void evergreen_hpd_init(struct radeon_device *rdev);
 void evergreen_hpd_fini(struct radeon_device *rdev);
index 60ec47b..232a307 100644 (file)
@@ -619,7 +619,7 @@ int radeon_device_init(struct radeon_device *rdev,
                /* Acceleration not working on AGP card try again
                 * with fallback to PCI or PCIE GART
                 */
-               radeon_gpu_reset(rdev);
+               radeon_asic_reset(rdev);
                radeon_fini(rdev);
                radeon_agp_disable(rdev);
                r = radeon_init(rdev);
index 3931542..2560740 100644 (file)
@@ -231,7 +231,7 @@ retry:
                if (seq == rdev->fence_drv.last_seq && radeon_gpu_is_lockup(rdev)) {
                        /* good news we believe it's a lockup */
                        dev_warn(rdev->dev, "GPU lockup (last fence id 0x%08X)\n", seq);
-                       r = radeon_gpu_reset(rdev);
+                       r = radeon_asic_reset(rdev);
                        if (r)
                                return r;
                        /* FIXME: what should we do ? marking everyone
index 626aaf0..3deec21 100644 (file)
@@ -432,7 +432,7 @@ int rs400_resume(struct radeon_device *rdev)
        /* setup MC before calling post tables */
        rs400_mc_program(rdev);
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
                        RREG32(R_0007C0_CP_STAT));
@@ -496,7 +496,7 @@ int rs400_init(struct radeon_device *rdev)
                        return r;
        }
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev,
                        "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
index abf824c..c1be20a 100644 (file)
@@ -601,7 +601,7 @@ int rs600_resume(struct radeon_device *rdev)
        /* Resume clock before doing reset */
        rv515_clock_startup(rdev);
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
                        RREG32(R_0007C0_CP_STAT));
@@ -664,7 +664,7 @@ int rs600_init(struct radeon_device *rdev)
                return -EINVAL;
        }
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev,
                        "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
index bbf3da7..ef35e04 100644 (file)
@@ -653,7 +653,7 @@ int rs690_resume(struct radeon_device *rdev)
        /* Resume clock before doing reset */
        rv515_clock_startup(rdev);
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
                        RREG32(R_0007C0_CP_STAT));
@@ -717,7 +717,7 @@ int rs690_init(struct radeon_device *rdev)
                return -EINVAL;
        }
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev,
                        "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
index 1cf233f..2a4c01f 100644 (file)
@@ -227,7 +227,7 @@ int rv515_ga_reset(struct radeon_device *rdev)
        return -1;
 }
 
-int rv515_gpu_reset(struct radeon_device *rdev)
+int rv515_asic_reset(struct radeon_device *rdev)
 {
        uint32_t status;
 
@@ -334,7 +334,7 @@ static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
 
        tmp = RREG32(0x2140);
        seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
-       radeon_gpu_reset(rdev);
+       radeon_asic_reset(rdev);
        tmp = RREG32(0x425C);
        seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
        return 0;
@@ -502,7 +502,7 @@ int rv515_resume(struct radeon_device *rdev)
        /* Resume clock before doing reset */
        rv515_clock_startup(rdev);
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),
                        RREG32(R_0007C0_CP_STAT));
@@ -572,7 +572,7 @@ int rv515_init(struct radeon_device *rdev)
                return -EINVAL;
        }
        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-       if (radeon_gpu_reset(rdev)) {
+       if (radeon_asic_reset(rdev)) {
                dev_warn(rdev->dev,
                        "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
                        RREG32(R_000E40_RBBM_STATUS),